Series battery pack protection circuit, chip and equipment

Abstract

The invention provides a series battery pack protection circuit, chip and equipment. The series battery pack protection circuit comprises a voltage and current protection circuit; the circuit comprises a switched capacitor circuit, a first-stage amplifier, a second-stage pre-amplifier, a latch comparator and switches SW1, SW2 and SW3, wherein the switched capacitor circuit comprises a first unit and a second unit; the first unit is used for receiving positive and negative electrode voltages output by the series battery pack, voltages at the first end and the second end of a peripheral circuit sensing resistor and a reference signal, and is controlled by a first control signal; the second unit is controlled by signals phi 1 and phi 2; the SW1 and the SW2 are controlled by a signal CP1; the second-stage pre-amplifier is controlled by a signal CP3, and the SW3 is controlled by a signal CP2; the latch comparator is controlled by a signal CP4; the voltage and current protection circuit can work in a voltage protection mode or a current protection mode according to different states of each control signal, has current protection and voltage protection functions, and can save circuit area and cost.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a series battery pack protection circuit, chip and device. Background Art

[0002] With the widespread application of new energy electric vehicles, the capacity, safety, health status and endurance of batteries have become the focus of attention. The Battery Management System (BMS) is a device that monitors the status of energy storage batteries. It is mainly used for intelligent management and maintenance of each battery unit, to prevent overcharging and over-discharging of the battery, to extend the battery life, and to monitor the battery status. The voltage protection circuit and current protection circuit in the BMS are usually set separately, resulting in a waste of circuit area. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a series battery pack protection circuit, chip and device, specifically comprising:

[0004] In a first aspect, the present invention provides a series battery pack protection circuit, comprising:

[0005] Voltage and current protection circuit;

[0006] The voltage and current protection circuit includes a switched capacitor circuit, a first-stage amplifier with a double-end input and double-end output having a closed-loop switch, a second-stage pre-amplifier with an input reset switch and a latch comparator, a switch SW1, a switch SW2 and a switch SW3, and the switched capacitor circuit includes a first unit and a second unit;

[0007] The input end of the first unit is used to receive the positive electrode voltage and the negative electrode voltage output by the series battery group, the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor, and the reference signal Vref1, the reference signal Vref2 and the first control signal, and the output end is connected to the second unit;

[0008] The first output terminal and the second output terminal of the second unit are respectively connected to the positive input terminal and the negative input terminal of the first stage amplifier, and the control signal input terminal of the second unit is respectively used to receive the signal φ1 and the signal φ2;

[0009] The first output terminal and the second output terminal of the first stage amplifier are respectively connected to the reverse input terminal and the forward input terminal of the second stage pre-amplifier;

[0010] The positive input terminal and the first output terminal, the negative input terminal and the second output terminal of the first stage amplifier are respectively connected across the switch SW1 and the switch SW2. The switch SW1 and the switch SW2 are controlled by the signal CP1. When the signal CP1 is at a high level, the switch SW1 and the switch SW2 are turned on.

[0011] The positive input terminal and the negative input terminal of the second stage preamplifier are connected across the switch SW3, the enable terminal is used to receive the signal CP3, and the output terminals are respectively connected to the input terminals of the latch comparator. The switch SW3 is controlled by the signal CP2. When the signal CP2 is at a high level, the switch SW3 is turned on.

[0012] The enable terminal of the latch comparator is used to receive the signal CP4;

[0013] The first unit transmits the positive and negative voltages output by the series battery pack and the reference signal Vref1 to the second unit according to the first control signal, so that the voltage and current protection circuit operates in the current protection mode according to the switching states of switches SW1, SW2 and SW3, and signals CP3, CP4, φ1 and φ2, or transmits the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor and the reference signal Vref2 to the second unit according to the first control signal, so that the voltage and current protection circuit operates in the voltage protection mode according to the switching states of switches SW1, SW2 and SW3, and signals CP3, CP4, φ1 and φ2.

[0014] In a second aspect, the present invention further provides a chip, comprising any series battery pack protection circuit provided in the first aspect.

[0015] In a third aspect, the present invention further provides a chip, including any chip provided in the second aspect.

[0016] Beneficial effects of the present invention:

[0017] The series battery pack protection circuit, chip and device provided by the present invention include: a voltage and current protection circuit; the voltage and current protection circuit includes a switch capacitor circuit, a first-stage amplifier with a double-end input and double-end output with a closed-loop switch, a second-stage pre-amplifier with an input reset switch and a latch comparator, a switch SW1, a switch SW2 and a switch SW3, and the switch capacitor circuit includes a first unit and a second unit; the input end of the first unit is used to receive the positive electrode voltage and the negative electrode voltage output by the series battery pack, the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor, and the reference signal Vref1 , reference signal Vref2 and the first control signal, and the output ends are connected to the second unit; the first output end and the second output end of the second unit are respectively connected to the positive input end and the negative input end of the first stage amplifier, and the control signal input end of the second unit is used to receive the signal Φ1 and the signal Φ2 respectively; the first output end and the second output end of the first stage amplifier are respectively connected to the negative input end and the positive input end of the second stage pre-amplifier; the positive input end and the first output end, the negative input end and the second output end of the first stage amplifier are respectively connected across the switch SW1 and the switch SW2, and the switch SW1 and the switch SW2 are controlled by the signal CP1, When the signal CP1 is at a high level, the switches SW1 and SW2 are turned on; the positive input terminal and the negative input terminal of the second-stage preamplifier are connected across the switch SW3, the enable terminal is used to receive the signal CP3, and the output terminals are respectively connected to the input terminals of the latch comparator. The switch SW3 is controlled by the signal CP2. When the signal CP2 is at a high level, the switch SW3 is turned on; the enable terminal of the latch comparator is used to receive the signal CP4; the first unit transmits the positive and negative voltages output by the series battery pack and the reference signal Vref1 to the second unit according to the first control signal, so that the voltage and current protection circuit can be turned on according to the switch SW1 and the switch SW2. The switching states of switch SW2 and switch SW3, as well as signal CP3, signal CP4, signal φ1 and signal φ2, operate in a current protection mode, or, according to the first control signal, transmit the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor to the second unit, as well as the reference signal Vref2, so that the voltage-current protection circuit operates in a voltage protection mode according to the switching states of switch SW1, switch SW2 and switch SW3, as well as signal CP3, signal CP4, signal φ1 and signal φ2, and can have both current protection and voltage protection functions, thereby saving circuit area and cost.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of an application scenario of a series battery pack protection circuit provided by the present invention;

[0020] Figure 2A schematic diagram of the structure of a voltage and current protection circuit provided by the present invention;

[0021] Figure 3 A schematic structural diagram of a second unit of a switched capacitor circuit provided by the present invention;

[0022] Figure 4 A timing diagram of a voltage and current protection circuit provided by the present invention;

[0023] Figure 5 A schematic diagram of the structure of a switched capacitor provided by the present invention;

[0024] Figure 6 A schematic diagram of the structure of a first-stage amplifier provided by the present invention;

[0025] Figure 7 A schematic diagram of the structure of a second-stage pre-amplifier provided by the present invention;

[0026] Figure 8 A schematic diagram of the structure of a latch comparator provided by the present invention;

[0027] Fig. 9 A schematic diagram of the structure of a discharge short-circuit overcurrent protection circuit provided by the present invention;

[0028] Fig.10 A schematic structural diagram of an over-temperature protection circuit provided by the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0030] Figure 1 A schematic diagram of an application scenario of a series battery pack protection circuit provided by the present invention, including a peripheral circuit and a series battery pack protection circuit. The peripheral circuit includes 12 series battery pack outputs, an RC filter network, a current sensing resistor R SENSE , high-side charging switch tube CHW and discharge switch tube DSW. The RC filter circuit is used to reduce the noise interference of the output voltage input signal of the series battery pack. The two ends of the current sensing resistor SRN and SRP are connected to the series battery pack protection circuit. The peripheral current flows through the resistor R SENSE The series battery pack protection circuit generates a voltage drop by measuring the resistance R SENSE The voltage drop is used to detect the charge and discharge current state of the circuit. CHG is connected to the gate of CSW to control the switching state of the charging switch tube; DSG is connected to the gate of DSW to control the switching state of the discharging switch tube.

[0031] The series battery pack protection circuit may specifically include a voltage and current protection circuit, a short circuit overcurrent protection circuit, an overtemperature protection circuit, a digital control circuit, and a switch drive circuit. The output voltage signal of the series battery pack is selected through a high-voltage multiplexer, and the two output ports respectively output the positive and negative voltages of the selected series battery pack output and transmit them to the voltage and current protection circuit. The current sensing resistor R SENSE The input voltage at both ends is also input into the voltage and current protection circuit to realize overcurrent protection of charging and discharging. At the same time, these two input ends are also connected to the short-circuit protection circuit. The overtemperature protection circuit uses the internal proportional to absolute temperature (PTAT) current to determine whether the circuit has an overtemperature risk. After the output signal of the above protection circuit passes through the digital control circuit and the high-side switch drive circuit, the switch state of the peripheral circuit charge and discharge tube is controlled through the DSG and CHG outputs to realize the protection management of the output of the series battery pack.

[0032] Figure 2 A schematic diagram of a series battery pack protection circuit provided by the present invention is shown in FIG. Figure 2 As shown, the circuit comprises:

[0033] Voltage and current protection circuit.

[0034] The voltage and current protection circuit includes a switched capacitor circuit 21, a first stage amplifier 22 with a double-ended input and double-ended output having a closed-loop switch, a second stage pre-amplifier 23 with an input reset switch and a latch comparator 24, a switch SW1, a switch SW2 and a switch SW3.

[0035] The switched capacitor circuit 21 includes a first unit 211 and a second unit 212 .

[0036] The input ends of the first unit 211 are respectively used to receive the positive electrode voltage Vn and the negative electrode voltage Vp output by the series battery group, the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor, as well as the reference signal Vref1, the reference signal Vref2 and the first control signal, and the output ends are connected to the second unit.

[0037] The first output terminal and the second output terminal of the second unit 212 are respectively connected to the positive input terminal and the negative input terminal of the first stage amplifier 22, and the control signal input terminal of the second unit 212 is respectively used to receive the signal φ1 and the signal φ2.

[0038] The first output terminal and the second output terminal of the first stage amplifier 22 are connected to the inverting input terminal and the non-inverting input terminal of the second stage pre-amplifier 23 respectively.

[0039] The positive input terminal and the first output terminal, the negative input terminal and the second output terminal of the first stage amplifier 22 are respectively connected to the switch SW1 and the switch SW2. The switch SW1 and the switch SW2 are controlled by the signal CP1. When the signal CP1 is at a high level, the switch SW1 and the switch SW2 are turned on.

[0040] The positive input terminal and the negative input terminal of the second stage pre-amplifier 23 are connected across the switch SW3 , the enable terminal is used to receive the signal CP3 , and the output terminal is connected to the input terminal of the latch comparator 24 .

[0041] The enable terminal of the latch comparator 24 is used to receive the signal CP4. The switch SW3 is controlled by the signal CP2. When the signal CP2 is at a high level, the switch SW3 is turned on.

[0042] The first unit 211 transmits the positive and negative voltages output by the series battery pack and the reference signal Vref1 to the second unit 212 according to the first control signal, so that the voltage and current protection circuit operates in the current protection mode according to the switching states of the switches SW1, SW2 and SW3, and the signals CP3, CP4, φ1 and φ2, or transmits the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor and the reference signal Vref2 to the second unit 212 according to the first control signal, so that the voltage and current protection circuit operates in the voltage protection mode according to the switching states of the switches SW1, SW2 and SW3, and the signals CP3, CP4, φ1 and φ2.

[0043] Specifically, when the signal CP3 is at a high level, the second-stage pre-amplifier 23 works normally; when the signal CP4 is at a high level, the latch comparator 24 works normally.

[0044] The circuit can have both current protection and voltage protection functions, saving circuit area and cost.

[0045] Comparators can compare the input voltage with the threshold voltage and are commonly used integrated circuit modules in BMS. Comparators can be divided into continuous time comparators and discrete time comparators. Continuous time comparators can get output results at any time, while discrete time comparators are driven by clocks and can only output comparison results within a certain period of time of the clock. Switched capacitor comparator is a discrete time comparator. Switched capacitor comparators are often used in analog-to-digital converters (ADCs). By combining comparators and switched capacitor circuits, they can automatically zero DC offset voltages and compare differential signals with single-ended circuits. Most of the current research focuses on how to improve the speed and accuracy of switched capacitor comparators. However, switched capacitor comparators have the problem of relatively single structure and comparison mode. Switched capacitor comparators usually use the low offset characteristics of switched capacitor circuits to directly compare the input voltage with the reference voltage, or, according to the characteristics of capacitor charge sharing, control the connection relationship between the capacitor array and the reference voltage, change the comparison threshold, and achieve a more accurate comparison result. However, the maximum comparison threshold in this way can only be the reference voltage, which cannot meet the needs of different scenarios.

[0046] Furthermore, the present invention Figure 2 Based on the circuit shown in FIG. 1 , a circuit structure of a second unit is also provided, such as Figure 3 As shown, the second unit includes:

[0047] Switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7 and switch K8, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 and capacitor C6.

[0048] The first end of the switch K1 , the first end of the switch K2 , and the first end of the switch K3 , as well as the first end of the switch K6 , the first end of the switch K7 , and the first end of the switch K8 are all connected to the first unit.

[0049] The first end of the capacitor C1 is respectively connected to the second end of the switch K1 and the second end of the switch K2, and the second end of the capacitor C1 is respectively connected to the second end of the capacitor C2, the second end of the capacitor C6 and the positive input end of the first stage amplifier.

[0050] The first end of the capacitor C2 is connected to the switch K3 and the switch K4 respectively.

[0051] The first end of the capacitor C3 is respectively connected to the second end of the switch K5 and the second end of the switch K6, and the second end of the capacitor C3 is respectively connected to the second end of the capacitor C4, the second end of the capacitor C5 and the negative input end of the first stage amplifier.

[0052] The first end of the capacitor C4 is connected to the switch K7 and the switch K8 respectively.

[0053] The switches K1 , K3 , K5 and K7 are controlled by the signal φ1 . When the signal φ1 is at a high level, the switches K1 , K3 , K5 and K7 are turned on.

[0054] The switches K2 , K3 , K6 and K8 are controlled by the signal φ2 . When the signal φ2 is at a high level, the switches K2 , K3 , K6 and K8 are turned on.

[0055] Combine the following Figure 4 The timing diagram shown in the figure provides detailed information Figure 2 The working sequence of the voltage and current protection circuit shown in the figure specifically includes:

[0056] In any cycle:

[0057] At time t1, signal φ2 reaches the falling edge; at time t2, signal φ1 and signal φ2 are at a low level, and signal CP1 reaches the rising edge; at time t3, signal φ1 reaches the rising edge; at time t4, signal CP1 reaches the falling edge; at time t5, signal φ1 reaches the falling edge; at time t6, signal CP2 reaches the rising edge; at time t7, signal φ2 reaches the rising edge; at time t8, signal CP2 reaches the falling edge, and signal CP3 reaches the rising edge at the same time; at time t9, signal CP4 reaches the rising edge; at time t10, signal CP3 and signal CP4 reach the falling edge at the same time.

[0058] Optional, in Figure 3 In the circuit shown, the capacitance of capacitor C1 is equal to the capacitance of capacitor C4, the capacitance of capacitor C2 is equal to the capacitance of capacitor C3, and the capacitance of capacitor C5 is equal to the capacitance of capacitor C6.

[0059] When the signal φ1 is at a high level and the signal φ2 is at a low level, the lower plate of the capacitor C1 is connected to the reverse voltage Vn, the lower plate of the capacitor C2 is connected to the reference voltage V-ref, the lower plate of the capacitor C3 is connected to the ground GND, and the lower plate of the capacitor C4 is connected to the forward voltage Vp. When the signal φ1 is at a low level and the signal φ2 is at a high level, the capacitor C1 is connected to the forward voltage Vp, the lower plate of the capacitor C2 is connected to the ground GND, the lower plate of the capacitor C3 is connected to the reference voltage V-ref, and the lower plate of the capacitor C4 is connected to the reverse voltage Vn.

[0060] Among them, when the reverse voltage Vn is the negative electrode voltage output by the series battery group, the forward voltage Vp is the positive electrode voltage output by the series battery group, and the reference voltage V-ref is the reference signal Vref1; when the reverse voltage Vn is the voltage SRN on the second end of the peripheral circuit sensing resistor, the forward voltage Vp is the voltage SRP on the first end of the peripheral circuit sensing resistor, and the reference voltage V-ref is the reference signal Vref2.

[0061] Combine the following Figure 4 right Figure 3 The principle of the circuit shown is analyzed:

[0062] The switched capacitor circuit converts the first output signal V o1 Output to the positive input terminal of the first stage amplifier, the second output signal V o2 The output is sent to the inverting input of the first-stage amplifier. The first-stage amplifier has common-mode feedback. Assuming that the common-mode feedback voltage is VREF, at time t2, the first-stage amplifier closes the loop and charges the capacitor upper plate voltage to VREF (i.e. Figure 3 The voltage values ​​of the two output signals Vo1 and Vo2 in the circuit are set to VREF), and the closed loop can store the DC input offset voltage through capacitors C5 and C6, reducing the impact of the offset voltage and improving the comparison accuracy. At t6, the two input ports of the second-stage pre-amplifier are short-circuited and reset to eliminate the impact of residual charge in the circuit. Until t7, the voltage on the upper plate of each capacitor changes. At this time, the voltage at the positive input end of the first-stage amplifier is:

[0063]

[0064] Among them, C1, C2 and C5 represent Figure 3 The capacitance values ​​of capacitors C1, C2 and C5, Vp and Vn respectively represent Figure 3 The voltage values ​​of Vp and Vn, Vref represents Figure 3 V-ref is the voltage value of the first stage amplifier, and Vin1 represents the voltage value of the positive input terminal of the first stage amplifier.

[0065] The voltage at the inverting input of the first stage amplifier is:

[0066]

[0067] Among them, C3, C4 and C6 represent Figure 3 In FIG. 1 , the capacitances of capacitors C3, C4 and C6 are shown in FIG. 1 , and Vin2 represents the voltage value at the inverting input terminal of the first-stage amplifier.

[0068] The absolute values ​​of the above two formulas are the same. To achieve the comparison effect, the following conditions must be met:

[0069] V n <V p ,

[0070] The voltage difference between the two ends of the first stage amplifier input is:

[0071]

[0072] After a simple transformation, we get:

[0073]

[0074] Among them, the coefficient A satisfies:

[0075] Keep the coefficient A unchanged, that is, the value of the capacitor C1 remains unchanged, and the sum of the value of the capacitor C2 and the value of the capacitor C5 remains unchanged.

[0076] When the value of the capacitor C1 is equal to the value of the capacitor C2, that is, C1 = C2, the comparison threshold is the reference voltage.

[0077] By changing the value of capacitor C2, the threshold value of the comparator changes as follows:

[0078]

[0079] in, ΔC2 Indicates the change in capacitance of capacitor C2.

[0080] It is easy to see that when the reference voltage and the capacitance C1 are fixed, the step size of the threshold is given by ΔC2 Determine the minimum step size of the threshold:

[0081]

[0082] The maximum range of the threshold value can be:

[0083]

[0084] At time t8, the second-stage pre-amplifier starts to work, at time t9, the latch comparator starts to work, and at time t10, the second-stage pre-amplifier and the latch comparator are turned off at the same time, and the comparison is completed.

[0085] Through the above analysis, it can be seen that the circuit structure provided by the present invention, when the reference voltage is fixed, uses the switched capacitor circuit and the timing control logic to realize the multi-level selection of the comparison threshold of the comparator, and the comparison threshold voltage range is not limited to the reference voltage. The level interval of the threshold can be achieved by adjusting the capacitance of a single capacitor in the switched capacitor circuit.

[0086] To further demonstrate the beneficial effects of the present invention, the present invention also provides a set of comparative quantitative analysis data between the present invention and SAR ADC. Since the present invention directly compares the output results and does not have a digital feedback module, the concept of bit number is not involved. The letter M represents the number of unit capacitors connected to the input voltage. Referring to Table 1, when the reference voltage Vref is determined, compared with the traditional SAR ADC, the threshold step size of the present invention is not affected by the total capacitance size and can be adjusted by the size of a single capacitor. At the same time, the threshold change range is adjusted by the capacitance size, which is larger than the threshold range of the traditional SAR ADC and has strong operability.

[0087] Table 1 Circuit parameter comparison table

[0088]

[0089] The switch capacitor circuit provided by the present invention can not only realize voltage protection, but also current protection. In practical applications, the voltage difference between the positive and negative electrodes of the battery varies in the range of about 0-5V, and the voltage difference between the positive and negative electrodes of the peripheral circuit current sensing resistor varies in the range of 0-0.2V, and the fluctuations of the two in the circuit are different. Therefore, when comparing and measuring the two, the selection of reference voltage and capacitance value is different.

[0090] For ease of understanding, the present invention Figure 3 A specific example is also provided based on Figure 5 , the switched capacitor circuit comprises:

[0091] Switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, switch S8, switch S9, switch S10, switch S11, switch S12, switch S13, switch S14, switch S15, switch S16, switch S17, switch S18, switch S19, switch S20, and capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, and capacitor C24.

[0092] The fixed end of the switch S1 is connected to the first end of the capacitor C7, the first active end is used to receive the negative voltage output by the series battery group, the second active end is used to receive the positive voltage output by the series battery group, and the third active end is grounded.

[0093] The fixed end of switch S2 is connected to the first end of capacitor C8, the first active end is used to receive the voltage on the second end of the peripheral circuit sensing resistor, the second active end is used to receive the voltage on the first end of the peripheral circuit sensing resistor, and the third active end is grounded.

[0094] The fixed ends of switch S3, switch S4, switch S5, switch S6, switch S7, switch S8 and switch S9 are respectively connected to the first ends of capacitors C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14 and capacitor C15, the first active ends are all connected to the fixed end of switch S10, and the second active ends are all grounded.

[0095] The first active end of the switch S10 is used for receiving the reference signal Vref2 , and the second active end of the switch S10 is used for receiving the reference signal Vref1 .

[0096] The fixed end of the switch S11 is connected to the second end of the capacitor C16, the first active end is used to receive the negative voltage output by the series battery group, the second active end is used to receive the positive voltage output by the series battery group, and the third active end is grounded.

[0097] The fixed end of switch S12 is connected to the second end of capacitor C17, the first active end is used to receive the voltage on the second end of the peripheral circuit sensing resistor, the second active end is used to receive the voltage on the first end of the peripheral circuit sensing resistor, and the third active end is grounded.

[0098] The fixed ends of switch S13, switch S14, switch S15, switch S16, switch S17, switch S18 and switch S19 are respectively connected to the second ends of capacitors C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23 and capacitor C24, the first active ends are all connected to the fixed end of switch S20, and the second active ends are all grounded.

[0099] The first active end of the switch S20 is used for receiving the reference signal Vref1 , and the second active end of the switch S20 is used for receiving the reference signal Vref2 .

[0100] Among them, the capacitance values ​​of capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, and capacitor C24 are 24c, 60c, c, 2c, 4c, 8c, 16c, 32c, 64c, 24c, 60c, c, 2c, 4c, 8c, 16c, 32c, and 64c, respectively, where c represents the unit capacitance value. Figure 3 The circuit shown and Figure 5 In the circuit shown, capacitor C7 is equivalent to Figure 3 The capacitors C1, C9, C10, C11, C12, C13 and C14 in the figure are equivalent to Figure 3 The capacitor C6 and capacitor C15 are equivalent to Figure 3 C2 and capacitor C16 are equivalent to Figure 3The capacitor C4, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21 and capacitor C22 correspond to Figure 3 The capacitor C5 and capacitor C23 are equivalent to Figure 3 C3 in.

[0101] When measuring and comparing the battery voltage, the reference voltage is selected as Vref2, the input voltage is connected to the capacitor with a capacitance of 24C, namely C7 and C16, the lower plates are connected, and the lower plates of the capacitors with a capacitance of 60C, C8 and C17, are grounded. At this time, the threshold of the circuit is The switch can be used to control the capacitance to adjust the threshold value. The threshold step is The threshold range is

[0102] When measuring and comparing the battery charge and discharge current, the input voltage is connected to the 60C capacitor, namely C8 and C17, the lower plates are connected, the 24C capacitors C7 and C16 lower plates are grounded, and the reference voltage is selected as Vref1. The threshold step size is The threshold range is

[0103] Furthermore, the present invention also provides a schematic diagram of the structure of a first-stage amplifier, such as Figure 6 As shown, the first stage amplifier includes: PMOS tube M P1-6 、PMOS tube M P2-6 、PMOS tube M P3-6 、PMOS tube M P4-6 、PMOS tube M P5-6 、PMOS tube M P6-6 、PMOS tube M P7-6 、PMOS tube M P8-6 And PMOS tube M P9-6 ; NMOS tube M N1-6 、NMOS tube M N2-6 、NMOS tube M N3-6 、NMOS tube M N4-6 、NMOS tube M N7-6 and NMOS tube M N8-6 .

[0104] PMOS tube M P8-6 And PMOS tube M P9-6 For the input pair, PMOS tube M P3-6 And PMOS tube M P6-6 The gate is connected to the common mode reference voltage V REF , PMOS tube M P2-6 And PMOS tube M P5-6 The gate terminals are connected to the two ends of the output respectively. When the common mode voltage of the double-end output is normal, the NMOS tube MN1-6 and NMOS tube M N2-6 When the common-mode voltage of the dual-end output is higher than the common-mode reference voltage, the NMOS tube M N1-6 The current in the path decreases, and the NMOS tube M N2-6 The current in the path increases, the voltage at point A increases, and the output common-mode voltage decreases, achieving the effect of negative feedback stabilizing the common-mode voltage. N7-6 and NMOS tube M N8-6 As diodes connected in reverse, they limit the output swing, thereby meeting the input swing requirement of the subsequent pre-amplifier.

[0105] Furthermore, the present invention also provides a schematic diagram of the structure of a second-stage pre-amplifier, such as Figure 7 As shown, the second stage pre-amplifier includes: PMOS tube M P1-7 、PMOS tube M P2-7 、PMOS tube M P3-7 、PMOS tube M P4-7 、PMOS tube M P5-7 、PMOS tube M P6-7 、PMOS tube M P7-7 And PMOS tube M P8-7 ; NMOS tube M N1-7 、NMOS tube M N2-7 、NMOS tube M N3-7 、NMOS tube M N4-7 、NMOS tube M N5-7 、NMOS tube M N6-7 、NMOS tube M PN7-7 and NMOS tube M N8-7 .

[0106] Among them, the PMOS tube M P1-7 、PMOS tube M P2-7 、PMOS tube M P3-7 、PMOS tube M P4-7 、PMOS tube M P5-7 、PMOS tube M P6-7 、PMOS tube M P7-7 And PMOS tube M P8-7 ; NMOS tube M N1-7 、NMOS tube M N2-7 、NMOS tube M N3-7 、NMOS tube M N4-7 、NMOS tube M N5-7 、NMOS tube M N6-7 、NMOS tube M N7-7 and NMOS tube M N8-7As a switch tube, its gate terminal is connected to the enable terminal. When the enable terminal signal is at a low level, the comparator works normally, and the input is amplified and output through two stages.

[0107] Furthermore, the present invention also provides a schematic diagram of the structure of a latch comparator, such as Figure 8 As shown, the latch comparator includes: PMOS tube M P1-8 、PMOS tube M P2-8 、PMOS tube M P3-8 、PMOS tube M P4-8 、PMOS tube M P5-8 、PMOS tube M P6-8 And PMOS tube M P7-8 ; NMOS tube M N1-8 、NMOS tube M N2-8 、NMOS tube M N3-8 、NMOS tube M N4-8 and NMOS tube M N5-8 .

[0108] Among them, the PMOS tube M P1-8 、PMOS tube M P2-8 、PMOS tube M P7-8 、NMOS tube M N3-8 、NMOS tube M N4-8 and NMOS tube M N5-8 As a switch tube controlled by an enable signal, when the enable signal is at a high level, the comparator works normally. The comparator realizes positive feedback through a cross-coupling connection to increase the speed of the comparator, and both ends of the output are connected to the latch input.

[0109] The voltage and current protection circuit provided by the present invention uses a switch capacitor circuit and a timing control logic to realize multiple gear selection of the comparison threshold of the comparator when the reference voltage is fixed, and the comparison threshold voltage range is not limited to the reference voltage. The gear interval of the threshold can be realized by adjusting the capacitance of a single capacitor in the switch capacitor circuit.

[0110] Furthermore, the series battery pack protection circuit also includes:

[0111] Discharge short circuit overcurrent protection circuit.

[0112] like Fig. 9 As shown, the discharge short circuit overcurrent protection circuit includes current source I1 and current source I2, resistor R, PMOS tube M p1-9 And PMOS tube M p2-9 , and comparator U1.

[0113] The first terminals of the current source I1 and the current source I2 are both used to receive the power source VDD.

[0114] The second end of the current source I2 is connected to the first end of the resistor R.

[0115] PMOS tube M p1-9 The gate is connected to the second end of the peripheral circuit sensing resistor, the source is respectively connected to the second end of the current source I1 and the positive input end of the comparator U1, and the drain is grounded.

[0116] PMOS tube M p2-9 The gate is connected to the first end of the peripheral circuit sensing resistor, the source is respectively connected to the second end of the resistor R and the negative input end of the comparator U1, and the drain is grounded.

[0117] Optional, PMOS tube M p1-9 And PMOS tube M p2-9 The same size.

[0118] Specifically, for the overcurrent protection circuit in the battery discharge short circuit state, the input voltage SRN>SRP, where the bias current I1=I2, the PMOS tube M p1-9 And PMOS tube M p2-9 The tubes are of the same size, ensuring that when the current is the same, the source voltage difference of the two tubes is the same as the input voltage difference. By adjusting the resistance R value or the bias current size, different threshold comparisons can be achieved, where the threshold value V TH =I·R, to achieve the comparison of input voltage, when input SRN<SRP+V TH , output low level, the circuit discharges normally at this time, when input SRN>SRP+V TH , outputs a high level, and after being processed by the digital circuit, triggers the overcurrent protection in the discharge state.

[0119] The short-circuit overcurrent protection circuit provided by the present invention realizes voltage comparison with adjustable threshold value by controlling the bias current and the resistance value.

[0120] Furthermore, the series battery pack protection circuit further includes:

[0121] Over temperature protection circuit.

[0122] like Fig.10 As shown, the over-temperature protection circuit includes resistors R1 and R2, NMOS tube M N1 , comparator U2, and inverter N1 and inverter N2.

[0123] The first end of the resistor R2 is used to receive the PATA current in the series battery pack protection circuit, and the second end is connected to the first end of the resistor R1 and the NMOS transistor M N1 Drain connection.

[0124] The second end of the resistor R1 and the NMOS tube M N1 The source is grounded.

[0125] The positive input terminal of the comparator U2 is connected to the first end of the resistor R2, and the negative input terminal is used to receive the reference voltage V REF , the output end is connected to the input end of the inverter N1.

[0126] The output end of the inverter N1 is connected to the input end of the inverter N2 and the NMOS tube M N1 The gate connection.

[0127] In the figure I PTAT = k·T, where k is the positive temperature correlation coefficient and T is the temperature. PTAT It is proportional to the temperature. Under normal temperature conditions, the NMOS tube M N1 The switch is turned on, and the positive input voltage of comparator U2 is I PTAT R2, at this time I PTAT ·R2<V REF , the output voltage is low. When the temperature exceeds a certain value, I PTAT R2>V REF , the output voltage jumps to a high level, indicating that the circuit is in an over-temperature state, triggering the over-temperature protection. At the same time, the NMOS tube M N1 The gate terminal becomes low level, the comparator U2 is reset, and the NMOS tube M N1 Shutdown, the positive input voltage of comparator U2 becomes I PTAT ·(R1+R2). Only when the temperature drops, I PTAT (R1+R2)<V REF When the over-temperature protection is released, the output will jump back to low level.

[0128] The over-temperature protection circuit of the present invention changes the input voltage by changing the resistance value of the input resistor, and then the comparator compares the voltage to realize the judgment of the over-temperature state, which ensures that after the over-temperature protection is triggered, the output of the over-temperature protection circuit will not change due to temperature fluctuations, enhances the stability of the over-temperature protection, ensures the effectiveness of the over-temperature protection release, and meets the actual application needs.

[0129] The present invention further provides a chip, comprising the series battery pack protection circuit provided by any of the above embodiments.

[0130] The present invention also provides an electronic device, comprising the chip provided by the above embodiment.

[0131] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0132] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A series battery pack protection circuit, characterized in that: include: Voltage and current protection circuit; The voltage and current protection circuit comprises a switched capacitor circuit, a first-stage amplifier with a double-end input and double-end output having a closed-loop switch, a second-stage pre-amplifier and a latch comparator having an input reset switch, a switch SW1, a switch SW2 and a switch SW3, and the switched capacitor circuit comprises a first unit and a second unit; The input end of the first unit is used to receive the positive electrode voltage and the negative electrode voltage output by the series battery group, the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor, and the reference signal Vref1, the reference signal Vref2 and the first control signal, and the output end is connected to the second unit; The first output terminal and the second output terminal of the second unit are respectively connected to the positive input terminal and the negative input terminal of the first stage amplifier, and the control signal input terminal of the second unit is respectively used to receive the signal Φ1 and the signal Φ2; The first output terminal and the second output terminal of the first stage amplifier are respectively connected to the reverse input terminal and the forward input terminal of the second stage pre-amplifier; The positive input terminal and the first output terminal, the negative input terminal and the second output terminal of the first stage amplifier are respectively connected across the switch SW1 and the switch SW2. The switch SW1 and the switch SW2 are controlled by a signal CP1. When the signal CP1 is at a high level, the switch SW1 and the switch SW2 are turned on. The positive input terminal and the negative input terminal of the second stage preamplifier are connected across the two ends of the switch SW3, the enable terminal is used to receive the signal CP3, and the output terminals are respectively connected to the input terminals of the latch comparator. The switch SW3 is controlled by the signal CP2. When the signal CP2 is at a high level, the switch SW3 is turned on. The enable terminal of the latch comparator is used to receive the signal CP4; The first unit transmits the positive and negative voltages output by the series battery group and the reference signal Vref1 to the second unit according to the first control signal, so that the voltage and current protection circuit operates in the current protection mode according to the switching states of the switches SW1, SW2 and SW3, and the signals CP3, CP4, φ1 and φ2, or transmits the voltage SRP on the first end and the voltage SRN on the second end of the peripheral circuit sensing resistor and the reference signal Vref2 to the second unit according to the first control signal, so that the voltage and current protection circuit operates in the voltage protection mode according to the switching states of the switches SW1, SW2 and SW3, and the signals CP3, CP4, φ1 and φ2.

2. The circuit according to claim 1, characterized in that The second unit comprises: Switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7 and switch K8, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5 and capacitor C6; The first end of the switch K1, the first end of the switch K2, the first end of the switch K3, the first end of the switch K6, the first end of the switch K7, and the first end of the switch K8 are all connected to the first unit; The first end of the capacitor C1 is respectively connected to the second end of the switch K1 and the second end of the switch K2, and the second end of the capacitor C1 is respectively connected to the second end of the capacitor C2, the second end of the capacitor C6 and the positive input end of the first stage amplifier; The first end of the capacitor C2 is connected to the switch K3 and the switch K4 respectively; The first end of the capacitor C3 is connected to the second end of the switch K5 and the second end of the switch K6 respectively, and the second end of the capacitor C3 is connected to the second end of the capacitor C4, the second end of the capacitor C5 and the negative input end of the first stage amplifier respectively; The first end of the capacitor C4 is connected to the switch K7 and the switch K8 respectively; The switch K1, the switch K3, the switch K5 and the switch K7 are controlled by the signal φ1. When the signal φ1 is at a high level, the switch K1, the switch K3, the switch K5 and the switch K7 are turned on. The switch K2 , the switch K3 , the switch K6 , and the switch K8 are controlled by the signal φ2 . When the signal φ2 is at a high level, the switch K2 , the switch K3 , the switch K6 , and the switch K8 are turned on.

3. The circuit according to claim 2, characterized in that The capacitance of the capacitor C1 is equal to the capacitance of the capacitor C4, the capacitance of the capacitor C2 is equal to the capacitance of the capacitor C3, and the capacitance of the capacitor C5 is equal to the capacitance of the capacitor C6.

4. The circuit according to claim 2 or 3, characterized in that Also includes: Discharge short circuit overcurrent protection circuit; The discharge short circuit overcurrent protection circuit includes a current source I1 and a current source I2, a resistor R, a PMOS tube M p1-8 And PMOS tube M p2-8 , and comparator U1; The first ends of the current source I1 and the current source I2 are both used to receive a power source VDD; The second end of the current source I2 is connected to the first end of the resistor R; The PMOS tube M p1-8 The gate is connected to the second end of the peripheral circuit sensing resistor, the source is respectively connected to the second end of the current source I1 and the positive input end of the comparator U1, and the drain is grounded; The PMOS tube M p2-8 The gate is connected to the first end of the peripheral circuit sensing resistor, the source is respectively connected to the second end of the resistor R and the negative input end of the comparator U1, and the drain is grounded.

5. The circuit according to claim 4, characterized in that The PMOS tube M p1-8 And PMOS tube M p2-8 The same size.

6. The circuit according to claim 2 or 3, characterized in that: Also includes: Over temperature protection circuit; The over-temperature protection circuit includes a resistor R1 and a resistor R2, an NMOS tube M N1 , comparator U2, and inverter N1 and inverter N2; The first end of the resistor R2 is used to receive the PATA current in the series battery pack protection circuit, and the second end is connected to the first end of the resistor R1 and the NMOS transistor M N1 The drain connection of The second end of the resistor R1 and the NMOS tube M N1 The source is grounded; The positive input terminal of the comparator U2 is connected to the first end of the resistor R2, and the negative input terminal is used to receive the reference voltage V REF , the output end is connected to the input end of the inverter N1; The output end of the inverter N1 is connected to the input end of the inverter N2 and the NMOS transistor M1. N1 The gate connection.

7. The circuit according to claim 1, characterized in that The voltage and current protection circuit comprises: Switch S1, switch S2, switch S3, switch S4, switch S5, switch S6, switch S7, switch S8, switch S9, switch S10, switch S11, switch S12, switch S13, switch S14, switch S15, switch S16, switch S17, switch S18, switch S19, switch S20, and capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, capacitor C24; The fixed end of the switch S1 is connected to the first end of the capacitor C7, the first active end is used to receive the negative voltage output by the series battery group, the second active end is used to receive the positive voltage output by the series battery group, and the third active end is grounded; The fixed end of the switch S2 is connected to the first end of the capacitor C8, the first active end is used to receive the voltage on the second end of the peripheral circuit sensing resistor, the second active end is used to receive the voltage on the first end of the peripheral circuit sensing resistor, and the third active end is grounded; The fixed ends of the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8 and the switch S9 are respectively connected to the first ends of the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14 and the capacitor C15, the first active ends are all connected to the fixed end of the switch S10, and the second active ends are all grounded; The first active end of the switch S10 is used to receive the reference signal Vref2, and the second active end is used to receive the reference signal Vref1; The fixed end of the switch S11 is connected to the second end of the capacitor C16, the first active end is used to receive the negative voltage output by the series battery group, the second active end is used to receive the positive voltage output by the series battery group, and the third active end is grounded; The fixed end of the switch S12 is connected to the second end of the capacitor C17, the first active end is used to receive the voltage on the second end of the peripheral circuit sensing resistor, the second active end is used to receive the voltage on the first end of the peripheral circuit sensing resistor, and the third active end is grounded; The fixed ends of the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18 and the switch S19 are respectively connected to the second ends of the capacitor C18, the capacitor C19, the capacitor C20, the capacitor C21, the capacitor C22, the capacitor C23 and the capacitor C24, the first active ends are all connected to the fixed end of the switch S20, and the second active ends are all grounded; The first active end of the switch S20 is used to receive a reference signal Vref1 , and the second active end of the switch S20 is used to receive a reference signal Vref2 .

8. The circuit according to claim 2 or 3, characterized in that: The working sequence of the switch capacitor circuit includes: In any cycle: At time t1, the signal φ2 reaches a falling edge; At time t2, the signal φ1 and the signal φ2 are at a low level, and the signal CP1 reaches a rising edge; At time t3, the signal φ1 reaches a rising edge; At time t4, the signal CP1 reaches a falling edge; At time t5, the signal φ1 reaches a falling edge; At time t6, signal CP2 reaches the rising edge; At time t7, the signal φ2 reaches a rising edge; At time t8, the signal CP2 reaches a falling edge, and the signal CP3 reaches a rising edge; At time t9, the signal CP4 reaches a rising edge; At time t10, the signal CP3 and the signal CP4 reach falling edges simultaneously.

9. A chip, characterized in that: A series battery pack protection circuit comprising the circuit described in any one of claims 1-8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

Images