Low-power-consumption battery management system

Abstract

The invention relates to a battery management system, in particular to a low-power-consumption battery management system which comprises a plurality of battery sampling chips AFE, a plurality of slave control units CSC and a master control unit BMU. The battery sampling chip AFE is used for acquiring voltage, current and temperature data of the single battery, sending the data to the corresponding slave control unit CSC, and entering a low-power-consumption state when an effective command is not received for a long time; the slave control unit CSC is used for collecting the voltage, current and temperature data, sent by the battery sampling chip AFE, of the single battery, sending the data to the master control unit BMU, and sending a wake-up signal, a register read-write command and an ADC measurement command to the corresponding battery sampling chip AFE when the data of the single battery needs to be measured; the master control unit BMU is used for processing the data sent by each slave control unit CSC and executing an advanced control algorithm; the technical scheme provided by the invention can effectively overcome the defect of relatively high energy consumption of the battery management system.

Description

Technical Field

[0001] The invention relates to a battery management system, and in particular to a low-power consumption battery management system. Background Art

[0002] The battery management system is an electronic control device for large battery packs that can monitor and control the operating status of the battery pack to prevent various faults such as overcharging, over-discharging, and overcurrent, thereby extending the service life of the battery pack. Battery management systems are widely used in electric vehicles, energy storage systems, solar panels and other fields.

[0003] Existing battery management systems usually consist of two parts: hardware and software. The hardware part mainly includes battery pack voltage and current measurement circuits, temperature sensors, fuses, relays and other electrical components; the software part is mainly responsible for real-time monitoring of the battery pack status, controlling the charging and discharging process, and realizing fault diagnosis and alarm functions. In today's pursuit of efficient energy utilization, low-power energy efficiency optimization is also an important research direction. How to effectively reduce the energy consumption of the battery management system by optimizing circuit design, adopting more efficient switching devices and introducing advanced control strategies has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a low-power consumption battery management system, which can effectively overcome the defect of high energy consumption of the battery management system in the prior art.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] A low-power battery management system, comprising a plurality of battery sampling chips AFE, a plurality of slave control units CSC and a master control unit BMU;

[0009] The battery sampling chip AFE collects the voltage, current and temperature data of the battery cells and sends the data to the corresponding slave control unit CSC. At the same time, it enters a low power consumption state when no valid commands are received for a long time.

[0010] The slave control unit CSC collects the voltage, current and temperature data of the battery cells sent by the battery sampling chip AFE, and sends the data to the master control unit BMU. At the same time, when the battery cell data needs to be measured, it sends a wake-up signal, register read and write commands and ADC measurement commands to the corresponding battery sampling chip AFE;

[0011] The master control unit BMU processes the data sent by each slave control unit CSC, executes advanced control algorithms, and communicates with other systems.

[0012] Preferably, the controller state machine of the battery sampling chip AFE includes the first power-on reset state POR1, the initialization state INIT, the standby state STANDBY, the sampling measurement state MEASURE, the low power consumption state SLP and the second power-on reset state POR2;

[0013] The first power-on reset state POR1, in which the initialization enable bit trim_en in the register rtn_reg is retained as 0, the battery sampling chip AFE enters the first power-on reset state POR1 after power-on, and waits for the clock to stabilize and the reset to be released before entering the initialization state INIT, and at the same time directly enters the second power-on reset state POR2 after power-on reset;

[0014] In the initialization state INIT, the battery sampling chip AFE reads the initialization value trim of the clock crystal oscillator and ADC from the one-time programmable device OTP, and adjusts the parameters of the clock crystal oscillator and ADC. At the same time, the initialization value trim is saved in the reserved register rtn_reg, and the initialization enable bit trim_en in the reserved register rtn_reg is set to 1, indicating that the initialization value trim stored in the reserved register rtn_reg is the valid initialization value of the clock crystal oscillator and ADC. After the parameter adjustment is completed, it enters the standby state STANDBY;

[0015] Waiting for the ready state STANDBY, when receiving the ADC measurement command, enter the sampling measurement state MEASURE, when the watchdog timer WDT times out, enter the low power state SLP, and directly read the initialization value trim from the reserved register rtn_reg when it is not the first power-on, and adjust the parameters of the clock crystal oscillator and ADC;

[0016] The sampling measurement state MEASURE collects the voltage, current and temperature data of the battery cell and sends the data to the corresponding slave control unit CSC. After the measurement is completed, it returns to the standby state STANDBY;

[0017] In the low power state SLP, a power-off signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power off. In this state, the initialization enable bit trim_en in the register rtn_reg is retained as 1. When the analog wake-up module wkp1 receives the wake-up signal sent by the corresponding slave control unit CSC, a power-on enable signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power on, and enters the second power-on reset state POR2;

[0018] The second power-on reset state POR2 waits for the clock to stabilize and the reset to be released before entering the standby state STANDBY.

[0019] Preferably, the battery sampling chip AFE includes a battery cell VBAT, a front-end regulator Pre-regulator, an NPN transistor, an analog part ana, a digital part dig, a reserved register rtn_reg, an analog power control module pwr_ctrl, an analog wake-up module wkp1, a first voltage regulator LDO1 and a second voltage regulator LDO2;

[0020] The battery cell VBAT is connected to the input end of the front-end regulator Pre-regulator, the input end of the first voltage regulator LDO1, and the collector of the NPN transistor. The output end of the front-end regulator Pre-regulator is connected to the base of the NPN transistor through the switch SW1. The emitter of the NPN transistor is connected to the analog part ana and the input end of the second voltage regulator LDO2. The output end of the second voltage regulator LDO2 is connected to the digital part dig.

[0021] The output end of the first voltage regulator LDO1 is connected to the retention register rtn_reg and the analog wake-up module wkp1 through the switch SW2 and the switch SW3 respectively, and the output end of the first voltage regulator LDO1 is connected to the analog power control module pwr_ctrl.

[0022] Preferably, when the battery sampling chip AFE is in a low power consumption state SLP or does not receive a wake-up signal after first power-on, a power off signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the switch SW1 to be disconnected, the NPN transistor is not turned on, and the analog part ana and the digital part dig are powered off;

[0023] When the battery sampling chip AFE is in the first power-on reset state POR1 or the second power-on reset state POR2, a power-on signal is sent to the analog power control module pwr_ctrl, the analog power control module pwr_ctrl controls the switch SW1 to be closed, the NPN transistor is turned on, the battery cell VBAT supplies power to the analog part ana, and at the same time, the battery cell VBAT supplies power to the digital part dig through the second voltage regulator LDO2.

[0024] Preferably, after the battery sampling chip AFE is powered on for the first time, the analog power control module pwr_ctrl controls the switch SW2 to be normally closed, and the battery cell VBAT supplies power to the retention register rtn_reg through the first voltage regulator LDO1, so that the retention register rtn_reg retains the stored initialization value trim.

[0025] Preferably, the analog power control module pwr_ctrl controls the switch SW3 to be normally closed, and the battery cell VBAT supplies power to the analog wake-up module wkp1 through the first voltage regulator LDO1, so that the analog wake-up module wkp1 can receive the wake-up signal sent by the corresponding slave control unit CSC at any time.

[0026] Preferably, the battery sampling chip AFE communicates with the corresponding slave control unit CSC in SPI mode, the slave control unit CSC communicates with the master control unit BMU in wired or wireless mode, and the battery sampling chip AFE supplies power to the corresponding slave control unit CSC.

[0027] (III) Beneficial effects

[0028] Compared with the prior art, the low-power battery management system provided by the present invention can effectively reduce the leakage current of the battery sampling chip AFE by optimizing circuit design, adopting more efficient switching devices and introducing advanced control strategies, so that the leakage current of the battery sampling chip AFE is reduced to 2μA, thereby significantly reducing the energy consumption of the battery management system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a schematic diagram of the system of the present invention;

[0031] Figure 2It is a schematic diagram of the controller state machine of the battery sampling chip AFE in the present invention;

[0032] Figure 3 It is a schematic diagram of the structure of the battery sampling chip AFE in the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] A low power battery management system, such as Figure 1 As shown, it includes multiple battery sampling chips AFE, multiple slave control units CSC and a master control unit BMU;

[0035] The battery sampling chip AFE collects the voltage, current and temperature data of the battery cells and sends the data to the corresponding slave control unit CSC. At the same time, it enters a low power consumption state when no valid commands are received for a long time.

[0036] The slave control unit CSC collects the voltage, current and temperature data of the battery cells sent by the battery sampling chip AFE, and sends the data to the master control unit BMU. At the same time, when the battery cell data needs to be measured, it sends a wake-up signal, register read and write commands and ADC measurement commands to the corresponding battery sampling chip AFE;

[0037] The master control unit BMU processes the data sent by each slave control unit CSC, executes advanced control algorithms (such as state estimation, fault diagnosis, charging strategy optimization, etc.), and communicates with other systems.

[0038] In the technical solution of the present application, the battery sampling chip AFE communicates with the corresponding slave control unit CSC in SPI mode, the slave control unit CSC communicates with the master control unit BMU in wired (such as SPI) or wireless (such as Bluetooth) mode, and the battery sampling chip AFE supplies power to the corresponding slave control unit CSC.

[0039] like Figure 2 As shown, the controller state machine of the battery sampling chip AFE includes the first power-on reset state POR1, the initialization state INIT, the standby ready state STANDBY, the sampling measurement state MEASURE, the low power consumption state SLP and the second power-on reset state POR2;

[0040] The first power-on reset state POR1, in which the initialization enable bit trim_en in the register rtn_reg is retained as 0, the battery sampling chip AFE enters the first power-on reset state POR1 after power-on, and waits for the clock to stabilize and the reset to be released before entering the initialization state INIT, and at the same time directly enters the second power-on reset state POR2 after power-on reset;

[0041] In the initialization state INIT, the battery sampling chip AFE reads the initialization value trim of the clock crystal oscillator and ADC from the one-time programmable device OTP, and adjusts the parameters of the clock crystal oscillator and ADC. At the same time, the initialization value trim is saved in the reserved register rtn_reg, and the initialization enable bit trim_en in the reserved register rtn_reg is set to 1, indicating that the initialization value trim stored in the reserved register rtn_reg is the valid initialization value of the clock crystal oscillator and ADC. After the parameter adjustment is completed, it enters the standby state STANDBY;

[0042] Waiting for the ready state STANDBY, when receiving the ADC measurement command, enter the sampling measurement state MEASURE, when the watchdog timer WDT times out, enter the low power state SLP, and directly read the initialization value trim from the reserved register rtn_reg when it is not the first power-on, and adjust the parameters of the clock crystal oscillator and ADC;

[0043] The sampling measurement state MEASURE collects the voltage, current and temperature data of the battery cell and sends the data to the corresponding slave control unit CSC. After the measurement is completed, it returns to the standby state STANDBY;

[0044] In the low power state SLP, a power-off signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power off. In this state, the initialization enable bit trim_en in the register rtn_reg is retained as 1. When the analog wake-up module wkp1 receives the wake-up signal sent by the corresponding slave control unit CSC, a power-on enable signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power on, and enters the second power-on reset state POR2;

[0045] The second power-on reset state POR2 waits for the clock to stabilize and the reset to be released before entering the standby state STANDBY.

[0046] like Figure 3As shown, the battery sampling chip AFE includes a battery cell VBAT, a front-end regulator Pre-regulator, an NPN transistor, an analog part ana, a digital part dig, a reserved register rtn_reg, an analog power control module pwr_ctrl, an analog wake-up module wkp1, a first voltage regulator LDO1 and a second voltage regulator LDO2;

[0047] The battery cell VBAT is connected to the input end of the front-end regulator Pre-regulator, the input end of the first voltage regulator LDO1, and the collector of the NPN transistor. The output end of the front-end regulator Pre-regulator is connected to the base of the NPN transistor through the switch SW1. The emitter of the NPN transistor is connected to the analog part ana and the input end of the second voltage regulator LDO2. The output end of the second voltage regulator LDO2 is connected to the digital part dig.

[0048] The output end of the first voltage regulator LDO1 is connected to the retention register rtn_reg and the analog wake-up module wkp1 through the switch SW2 and the switch SW3 respectively, and the output end of the first voltage regulator LDO1 is connected to the analog power control module pwr_ctrl.

[0049] 1) When the battery sampling chip AFE is in the low power state SLP or does not receive a wake-up signal after the first power-on, it sends a power shutdown signal to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the switch SW1 to be disconnected, the NPN transistor is not turned on, and the analog part ana and the digital part dig are powered off;

[0050] When the battery sampling chip AFE is in the first power-on reset state POR1 or the second power-on reset state POR2, a power-on signal is sent to the analog power control module pwr_ctrl, the analog power control module pwr_ctrl controls the switch SW1 to close, the NPN transistor is turned on, the battery cell VBAT supplies power to the analog part ana, and the battery cell VBAT supplies power to the digital part dig through the second voltage regulator LDO2.

[0051] 2) After the battery sampling chip AFE is powered on for the first time, the analog power control module pwr_ctrl controls the switch SW2 to be normally closed, and the battery cell VBAT supplies power to the retention register rtn_reg through the first voltage regulator LDO1, so that the retention register rtn_reg retains the stored initialization value trim.

[0052] 3) The analog power control module pwr_ctrl controls the switch SW3 to be normally closed, and the battery cell VBAT supplies power to the analog wake-up module wkp1 through the first voltage regulator LDO1, so that the analog wake-up module wkp1 can receive the wake-up signal sent by the corresponding slave control unit CSC at any time.

[0053] In the technical solution of the present application, by optimizing the circuit design, adopting more efficient switching devices and introducing advanced control strategies, the leakage current of the battery sampling chip AFE can be effectively reduced, so that the leakage current of the battery sampling chip AFE is reduced to 2μA, thereby significantly reducing the energy consumption of the battery management system.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low power consumption battery management system, characterized in that: It includes multiple battery sampling chips AFE, multiple slave control units CSC and a master control unit BMU; The battery sampling chip AFE collects the voltage, current and temperature data of the battery cells and sends the data to the corresponding slave control unit CSC. At the same time, it enters a low power consumption state when no valid commands are received for a long time. The slave control unit CSC collects the voltage, current and temperature data of the battery cells sent by the battery sampling chip AFE, and sends the data to the master control unit BMU. At the same time, when the battery cell data needs to be measured, it sends a wake-up signal, register read and write commands and ADC measurement commands to the corresponding battery sampling chip AFE; The master control unit BMU processes the data sent by each slave control unit CSC, executes advanced control algorithms, and communicates with other systems.

2. The low power consumption battery management system according to claim 1, characterized in that: The controller state machine of the battery sampling chip AFE includes the first power-on reset state POR1, the initialization state INIT, the standby state STANDBY, the sampling measurement state MEASURE, the low power consumption state SLP and the second power-on reset state POR2; The first power-on reset state POR1, in which the initialization enable bit trim_en in the register rtn_reg is retained as 0, the battery sampling chip AFE enters the first power-on reset state POR1 after power-on, and waits for the clock to stabilize and the reset to be released before entering the initialization state INIT, and at the same time directly enters the second power-on reset state POR2 after power-on reset; In the initialization state INIT, the battery sampling chip AFE reads the initialization value trim of the clock crystal oscillator and ADC from the one-time programmable device OTP, and adjusts the parameters of the clock crystal oscillator and ADC. At the same time, the initialization value trim is saved in the reserved register rtn_reg, and the initialization enable bit trim_en in the reserved register rtn_reg is set to 1, indicating that the initialization value trim stored in the reserved register rtn_reg is the valid initialization value of the clock crystal oscillator and ADC. After the parameter adjustment is completed, it enters the standby state STANDBY; Waiting for the ready state STANDBY, when receiving the ADC measurement command, enter the sampling measurement state MEASURE, when the watchdog timer WDT times out, enter the low power state SLP, and directly read the initialization value trim from the reserved register rtn_reg when it is not the first power-on, and adjust the parameters of the clock crystal oscillator and ADC; The sampling measurement state MEASURE collects the voltage, current and temperature data of the battery cell and sends the data to the corresponding slave control unit CSC. After the measurement is completed, it returns to the standby state STANDBY; In the low power state SLP, a power-off signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power off. In this state, the initialization enable bit trim_en in the register rtn_reg is retained as 1. When the analog wake-up module wkp1 receives the wake-up signal sent by the corresponding slave control unit CSC, a power-on enable signal is sent to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the battery sampling chip AFE to power on, and enters the second power-on reset state POR2; The second power-on reset state POR2 waits for the clock to stabilize and the reset to be released before entering the standby state STANDBY.

3. The low power consumption battery management system according to claim 2, characterized in that: The battery sampling chip AFE includes a battery cell VBAT, a front-end regulator Pre-regulator, an NPN transistor, an analog part ana, a digital part dig, a reserved register rtn_reg, an analog power control module pwr_ctrl, an analog wake-up module wkp1, a first voltage regulator LDO1 and a second voltage regulator LDO2; The battery cell VBAT is connected to the input end of the front-end regulator Pre-regulator, the input end of the first voltage regulator LDO1, and the collector of the NPN transistor. The output end of the front-end regulator Pre-regulator is connected to the base of the NPN transistor through the switch SW1. The emitter of the NPN transistor is connected to the analog part ana and the input end of the second voltage regulator LDO2. The output end of the second voltage regulator LDO2 is connected to the digital part dig. The output end of the first voltage regulator LDO1 is connected to the retention register rtn_reg and the analog wake-up module wkp1 through the switch SW2 and the switch SW3 respectively, and the output end of the first voltage regulator LDO1 is connected to the analog power control module pwr_ctrl.

4. The low power consumption battery management system according to claim 3, characterized in that: When the battery sampling chip AFE is in a low power consumption state SLP or does not receive a wake-up signal after first power-on, it sends a power off signal to the analog power control module pwr_ctrl, and the analog power control module pwr_ctrl controls the switch SW1 to be disconnected, the NPN transistor is not turned on, and the analog part ana and the digital part dig are powered off; When the battery sampling chip AFE is in the first power-on reset state POR1 or the second power-on reset state POR2, a power-on signal is sent to the analog power control module pwr_ctrl, the analog power control module pwr_ctrl controls the switch SW1 to be closed, the NPN transistor is turned on, the battery cell VBAT supplies power to the analog part ana, and at the same time, the battery cell VBAT supplies power to the digital part dig through the second voltage regulator LDO2.

5. The low power consumption battery management system according to claim 3, characterized in that: After the battery sampling chip AFE is powered on for the first time, the analog power control module pwr_ctrl controls the switch SW2 to be normally closed, and the battery cell VBAT supplies power to the retention register rtn_reg through the first voltage regulator LDO1, so that the retention register rtn_reg retains the stored initialization value trim.

6. The low power consumption battery management system according to claim 3, characterized in that: The analog power control module pwr_ctrl controls the switch SW3 to be normally closed, and the battery cell VBAT supplies power to the analog wake-up module wkp1 through the first voltage regulator LDO1, so that the analog wake-up module wkp1 can receive the wake-up signal sent by the corresponding slave control unit CSC at any time.

7. The low power consumption battery management system according to claim 1, characterized in that: The battery sampling chip AFE communicates with the corresponding slave control unit CSC in SPI mode, the slave control unit CSC communicates with the master control unit BMU in wired or wireless mode, and the battery sampling chip AFE supplies power to the corresponding slave control unit CSC.

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