Sampling hold circuit
By connecting the negative capacitance module with the sampling switch module in parallel, the signal bandwidth and band load capacity of the sampling and holding circuit are improved, and the problem of insufficient sampling accuracy and speed in the prior art is solved, thereby achieving higher signal stability and accuracy.
Patent Information
- Application Number
- CN202411264254.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2024-12-13
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing sampling and holding circuits have insufficient signal bandwidth and band load capacity, resulting in insufficient sampling accuracy and speed to prevent distortion and noise interference of the signal during analog-to-digital conversion.
By connecting the negative capacitance module in parallel with the first sampling switch module and the second sampling switch module, the total equivalent load capacitance per unit follower output is smaller than the sampling capacitor, increasing the signal bandwidth and load capacity, and improving the sampling accuracy and speed .
It achieves higher signal bandwidth and band load capacity, improves sampling accuracy and speed, reduces noise and interference in the conversion process, and ensures signal stability and accuracy.
Smart Images
Figure CN119135177A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of sample-and-hold circuits, and in particular to a sample-and-hold circuit. Background Art
[0002] The sample-and-hold circuit (SHA) is an important component of the analog-to-digital converter (ADC). It plays a key role in signal processing, data acquisition and communication systems.
[0003] In many electronic and electrical systems, analog signals need to be converted into digital signals for processing and analysis by digital systems. This process is called analog-to-digital conversion. The sample-and-hold circuit ensures that the analog signal can be accurately sampled before analog-to-digital conversion without losing any important signal information.
[0004] By sampling the analog signal and holding its value, the sample-and-hold circuit can prevent the signal from being distorted during the quantization process, ensure the stability of the signal during the conversion process, and improve the overall accuracy of the analog-to-digital conversion because it reduces noise and interference during the conversion process.
[0005] The bandwidth performance, linearity and stability of the sampling and holding circuit are the main indicators that need to be considered in circuit design. Increasing the signal bandwidth and load capacity of the sampling circuit has a positive effect on improving the sampling accuracy and sampling speed.
[0006] Therefore, in view of the shortcomings of the prior art, it is necessary to provide a sample-and-hold circuit to solve the shortcomings of the prior art. Summary of the invention
[0007] The purpose of the present invention is to avoid the shortcomings of the prior art and provide a sampling and holding circuit. The sampling and holding circuit connects a negative capacitance module in parallel with a first sampling switch module, a second sampling switch module and a sampling capacitor, so that the total equivalent load capacitance of the output end of the unit follower is less than the sampling capacitance during the sampling stage, that is, the total equivalent capacitance = the absolute value of the sampling capacitance minus the capacitance of the negative capacitance module, thereby increasing the signal bandwidth and load capacity of the sampling and holding circuit and improving the sampling accuracy and sampling speed of the sampling and holding circuit.
[0008] The above-mentioned purpose of the present invention is achieved through the following technical means.
[0009] A sampling and holding circuit is provided, comprising a unit follower, a negative capacitance module, a first sampling switch module, a second sampling switch module and a sampling capacitor, wherein a first input terminal of the unit follower and a second input terminal of the unit follower are connected to a differential input signal, a first output terminal of the unit follower and a second output terminal of the unit follower are connected to the negative capacitance module, the unit follower is simultaneously connected to an input terminal of the first sampling switch module and an input terminal of the second sampling switch module, and an output terminal of the first sampling switch module and an output terminal of the second sampling switch module are simultaneously connected to the sampling capacitor.
[0010] Specifically, the negative capacitance module includes a first NMOS tube, a second NMOS tube, a first capacitor, a first bias current source and a second bias current source. The drain of the first NMOS tube is connected to the gate of the second NMOS tube, the drain of the second NMOS tube is connected to the gate of the first NMOS tube, the source level of the first NMOS tube and the source level of the second NMOS tube are simultaneously connected to the first capacitor, the source level of the first NMOS tube is simultaneously connected to the first bias current source, and the source level of the second NMOS tube is simultaneously connected to the second bias current source.
[0011] Preferably, the first capacitor is a mom capacitor.
[0012] The present invention connects the negative capacitance module in parallel with the first sampling switch module, the second sampling switch module and the sampling capacitor, so that the total equivalent load capacitance of the output end of the unit follower is less than the sampling capacitance during the sampling stage, that is, the total equivalent capacitance = the sampling capacitance - the absolute value of the capacitance of the negative capacitance module, thereby increasing the signal bandwidth and load capacity of the sampling and holding circuit, and improving the sampling accuracy and sampling speed of the sampling and holding circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The present invention is further described with reference to the accompanying drawings, but the contents in the accompanying drawings do not constitute any limitation to the present invention.
[0014] Figure 1 The present invention is a schematic diagram of the structure of a sampling and holding circuit.
[0015] Figure 2 It is a circuit diagram of a sampling and holding circuit of the present invention.
[0016] Figure 3 The present invention is a circuit diagram of a negative capacitance module of a sample-and-hold circuit.
[0017] Figure 4 The circuit diagram of a follower of a sampling and holding circuit of the present invention is DETAILED DESCRIPTION
[0018] The present invention is further described in conjunction with the following examples.
[0019] Example 1.
[0020] like Figure 1-4 As shown, a sample-and-hold circuit includes a unit follower I0, a negative capacitance module I2, a first sampling switch module S1, a second sampling switch module S2 and a sampling capacitor I3, wherein the first input terminal in+ of the unit follower I0 and the second input terminal in- of the unit follower I0 are connected to a differential input signal, the first output terminal out+ of the unit follower I0 and the second output terminal out- of the unit follower I0 are connected to the negative capacitance module I2, the unit follower I0 is simultaneously connected to the input terminal of the first sampling switch module S1 and the input terminal of the second sampling switch module S2, and the output terminal of the first sampling switch module S1 and the output terminal of the second sampling switch module S2 are simultaneously connected to the sampling capacitor I3.
[0021] The unit follower I0 is a dual differential structure, whose input end is connected to the differential input signal, the positive phase first output end out+ is connected to one end of the negative capacitance module I2 and to the input end of the first sampling switch module S1, and the reverse second input end is connected to the other end of the negative capacitance module I2 and to the input end of the second sampling switch module S2, so that the output of the unit follower I0 can change with the change of the differential input signal. In the figure, the two ends of the first sampling switch module S1 are P5 and P6 respectively, and the two ends of the second sampling switch module S2 are P7 and P8 respectively.
[0022] The negative capacitor module I2 has two ports, namely a first port P1 and a second port P2. The first port P1 and the second port P2 are directly connected to the two output terminals of the unit follower I0. The voltage across the negative capacitor module I2 can change with the change of the differential input signal voltage.
[0023] The negative capacitance module I2 includes a first NMOS tube M1, a second NMOS tube M2, a first capacitor C1, a first bias current source bias1 and a second bias current source bias2. The drain of the first NMOS tube M1 is connected to the gate of the second NMOS tube M2, the drain of the second NMOS tube M2 is connected to the gate of the first NMOS tube M1, the source level of the first NMOS tube M1 and the source level of the second NMOS tube M2 are simultaneously connected to the first capacitor C1, the source level of the first NMOS tube M1 is simultaneously connected to the first bias current source bias1, and the source level of the second NMOS tube is simultaneously connected to the second bias current source bias2.
[0024] When the first sampling switch module S1 and the second sampling switch module S2 are closed, the sampling capacitor I3 is connected to the first output terminal out+ and the second output terminal out- of the unit follower I0, and the output voltage of the sampling capacitor I3 changes with the voltage change of the differential input signal. When the first sampling switch module S1 and the second sampling switch module S2 are disconnected, the sampling capacitor I3 is disconnected from the unit follower I0, and the voltage across the sampling capacitor I3 remains unchanged.
[0025] The negative capacitance module I2 is composed of a first NMOS transistor M1 and a second NMOS transistor M2 forming a cross-coupling pair, and the source terminals of the two NMOS transistors are simultaneously connected to the first capacitor C1, thereby realizing an equivalent negative capacitance.
[0026] The unit follower I0 adopts a single-stage NMOS tube common source amplifier structure, has the characteristics of high swing and low power consumption, and can be used for low voltage working conditions. It includes a third NMOS tube M3, a fourth NMOS tube M4, a third bias current source bias3 and a fourth bias current source bias4.
[0027] When the input signal connected to the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 changes, since the currents of the third bias current source bias3 and the fourth bias current source bias4 do not change, the sources out+ and out- of the third NMOS tube M3 and the fourth NMOS tube M4 will change respectively following the gate voltage changes of the third NMOS tube M3 and the fourth NMOS tube M4.
[0028] The first port P1 of the negative capacitor module I2 is connected to the positive first output terminal out+ of the unit follower I0, and the second port P2 is connected to the negative second output terminal out- of the unit follower. The voltage Vtb of the first capacitor C1 rises for positive charging, and Vtb drops for reverse charging. When the voltage of the first port P1 increases and the voltage of the second port P2 decreases, the source voltage of the first NMOS tube M1 decreases, the source voltage of the second NMOS tube increases, and the first capacitor C1 is reversely charged. When the voltage of the first port P1 decreases and the voltage of the second port P2 increases, the source voltage of the first NMOS tube M1 increases, the source voltage of the second NMOS tube M2 decreases, and the capacitor C1 is positively charged, which is equivalent to a negative capacitor.
[0029] The positive-phase first output terminal out+ and the negative-phase second output terminal out- of the unit follower I0 are respectively connected to the first port P1 and the second port P2 of the negative capacitor module I2. The sampling capacitor I3 has two ports, namely the third port P3 and the fourth port P4. At the same time, the first port P1 is connected to the third port P3 of the sampling capacitor I3 through the first sampling switch module S1, and the second port P2 is connected to the fourth port P4 of the sampling capacitor I3 through the second sampling switch module S2. When the first sampling switch module S1 and the second sampling switch module S2 are closed, the sampling capacitor I3 and the negative capacitor module I2 are connected in parallel, and their equivalent capacitance is the load capacitance of the unit follower I0. At this time, the output signal is equal to the output of the unit follower I0. When the first sampling switch module S1 and the second sampling switch S2 are disconnected, the output signal maintains the voltage value at the last moment before the first sampling switch module S1 and the second sampling switch S2 are disconnected.
[0030] The first capacitor is a mom capacitor.
[0031] The use of mom capacitors can save costs while maintaining the effect of equivalent negative capacitance.
[0032] The present invention connects the negative capacitance module in parallel with the first sampling switch module, the second sampling switch module and the sampling capacitor, so that the total equivalent load capacitance of the output end of the unit follower is less than the sampling capacitance during the sampling stage, that is, the total equivalent capacitance = the sampling capacitance - the absolute value of the capacitance of the negative capacitance module, thereby increasing the signal bandwidth and load capacity of the sampling and holding circuit, and improving the sampling accuracy and sampling speed of the sampling and holding circuit.
[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.
Claims
1. A sample-and-hold circuit, characterized in that: The invention comprises a unit follower, a negative capacitance module, a first sampling switch module, a second sampling switch module and a sampling capacitor, wherein the first input terminal of the unit follower and the second input terminal of the unit follower are connected to a differential input signal, the first output terminal of the unit follower and the second output terminal of the unit follower are connected to the negative capacitance module, the unit follower is simultaneously connected to the input terminal of the first sampling switch module and the input terminal of the second sampling switch module, and the output terminal of the first sampling switch module and the output terminal of the second sampling switch module are simultaneously connected to the sampling capacitor.
2. A sample-and-hold circuit according to claim 1, characterized in that: The negative capacitance module includes a first NMOS tube, a second NMOS tube, a first capacitor, a first bias current source and a second bias current source, the drain of the first NMOS tube is connected to the gate of the second NMOS tube, the drain of the second NMOS tube is connected to the gate of the first NMOS tube, the source level of the first NMOS tube and the source level of the second NMOS tube are simultaneously connected to the first capacitor, the source level of the first NMOS tube is simultaneously connected to the first bias current source, and the source level of the second NMOS tube is simultaneously connected to the second bias current source.
3. A sample-and-hold circuit according to claim 2, characterized in that: The first capacitor is a mom capacitor.