Readout circuit

Abstract

A readout circuit (110) is presented. The readout circuit (110) is configured for converting the analog sensor charge (112) into a digital output count (114). The readout circuit (110) includes at least one integration and excitation (IAF) circuit (116). The IAF circuit (116) is configured to convert the analog sensor charge (112) to a first digital output count (118). The analog voltage margin after the final IAF period is further processed (120). The readout circuit (110) comprises at least one analog-to-digital converter (ADC) (122). The ADC (122) is configured to convert the analog voltage margin (120) to a second digital output (124). Further, the input charge of the circuit is read out, a photodetector (182) and a method for reading out an analog sensor charge (112) are presented.

Description

Technical Field

[0001] The present invention relates to a readout circuit configured to convert an analog sensor charge into a digital output count, a photodetector, and a method for reading out an analog sensor charge. Specifically, the readout circuit can be used to read out a photodetector, such as a photodetector used in a spectrometer. More specifically, the readout circuit can be used to determine a digital output count of a photoconductor (such as a lead sulfide photoconductor) or a photodiode (such as Si, InGaAs, or SiGe). Other options may also be possible. Background Art

[0002] Spectrometry generally requires separating radiation into spectral wavelength components and measuring the intensity of each component. One method of spectrometry can perform measurements in parallel using a sensor array that reacts to radiation that has been separated into many spectral wavelength components. Many sensor technologies can be used to implement spectral analysis, including lead sulfide (PbS), lead selenide (PbSe), indium gallium arsenide (InGaAs), pyroelectric, etc. Most of these sensor technologies may require measuring a small amount of charge at high resolution. The electronics may first convert the charge from the sensor array into a voltage in a readout integrated circuit (ROIC). The voltage may then be digitized using an analog-to-digital converter (ADC). Both integrated circuits may typically be expensive and consume a lot of power. In addition, the use of separate ROICs and ADCs may require additional circuitry and a longer connection length between the ROIC analog output and the ADC input. These connections may be susceptible to noise pickup from both internal and external sources.

[0003] It is known to use an ROIC and an ADC to convert charge to voltage and then digitize it. Most shunt charge-to-voltage conversion ROICs use a charge amplifier circuit that exploits the linear relationship between the accumulated charge on a capacitor and the voltage. This type of circuit can be used because it provides the flexibility to adjust the output voltage based on the application requirements and inputs, the ability to measure and resolve small charges, and the ability to implement the circuit in most existing mixed-signal IC foundry processes. The ROIC can convert the charge (Q) from the sensor to a voltage (V) by collecting the charge on a capacitor (C) according to the following equation

[0004]

[0005] The maximum voltage may be limited by the IC technology, so the charge-capacitance product must remain below that limit. The flexibility of the ROIC can allow the voltage output to be adjusted to use it in many different applications. Regardless of the maximum charge specified by the sensor and application, the output can be adjusted to utilize a large portion of the maximum voltage specified by the IC. Two methods can be used to control the charge and adjust the charge-to-voltage gain to maximize the output voltage:

[0006] 1) Adjust capacitor values ​​to increase or decrease the voltage to charge conversion ratio and / or

[0007] 2) The charge is adjusted by changing the integration time t, since the charge is related to the sensor current i(t), where

[0008]

[0009] In an IC, multiple capacitor values ​​are often implemented for each channel. The user can select the capacitor value and can adjust the integration time based on the application. The capacitor range is often between tens of femtofarads and tens of picofarads. Smaller capacitors increase the output voltage for a constant charge due to the increased charge-to-voltage gain. The lower limit of capacitance is dictated by the IC technology. Larger capacitors may require more area on the IC, but will increase the dynamic range and reduce the charge-to-voltage gain.

[0010] Measurement noise can be limited by three factors:

[0011] 1) Sensor current noise;

[0012] 2) Noise generated by ROIC;

[0013] 3) ADC quantization noise.

[0014] For all applications, it may be desirable to allow the sensor noise to dominate the noise floor. Therefore, the noise generated by the ROIC and the quantization noise should be kept significantly lower than the sensor noise. For this architecture, the analog voltage output of the charge converter can be connected to the ADC. The ADC can be located within the integrated circuit or as a separate integrated circuit. In either case, due to the large number of signals, the channels are often multiplexed and transmitted serially. Multiplexing may require additional circuitry, and the length of the connections is relatively long, which means that this type of architecture may be susceptible to analog noise pickup from other internal or external sources.

[0015] Furthermore, the complexity, size, and power of the ADC increases rapidly with the bit count. To reduce overall power, cost, and size, a single high-resolution ADC with a high sampling rate is often used rather than using multiple high-resolution ADCs with lower sampling rates.

[0016] A different approach has been commercialized for use with other charge-based sensor array systems. This approach is exemplified by the publication, Dei Michele et al., “Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers,” 2017 IEEE International Conference on Circuits and Systems (ISCAS), IEEE, 2017, and is referred to as an integrate-and-fire circuit (IAF circuit). The linear nature of the charge-to-voltage conversion using a capacitor can be employed. However, it is modified to directly convert the analog current to a digital signal. The capacitor and maximum voltage can be reduced to allow the charge to saturate the output. The circuit can detect saturation and automatically reset the charge-to-voltage conversion. For each saturation event, a counter can be simultaneously incremented by 1. Saturation and counting can continue during the integration period, and after the integration time is over, the counter value is proportional to the input current.

[0017] The digital output can be generated locally by the measurement unit, and a separate ADC may not be required. In fact, each measurement unit can digitize the signal directly into a counter value. The analog signal path may be shorter, and the circuit can run without a clock (ie, asynchronously), which further reduces the noise source. The integration capacitor can be reduced to increase the number of saturation events. Therefore, the area required for the capacitor can be much smaller, and the measurement unit can become smaller. Several capacitors are usually still included to allow the user to adjust the gain. The integration time can be retained to allow the user to fully control the gain and maximize the resolution. Similarly, the ADC can be replaced by a relatively small counter and Schmitt trigger circuit and other logic gates. Such a circuit may require a relatively small area and power and can be replicated for each sensor input. Due to the nature of the circuit, it may be smaller and more energy efficient. Using modern CMOS mixed-signal processes, the power per channel may reach the order of ten μW. Since the size of the capacitor can be reduced and the ADC can be replaced by a counter and Schmitt trigger, the size of the circuit can also be reduced.

[0018] Although the prior art achieves multiple advantages, there are still various technical challenges. Specifically, it is necessary to reduce the size, complexity, cost and power consumption of the parallel charge-to-digital conversion, and further reduce the overall noise of the system. Further, for the IAF circuit, the charge must be large enough to generate enough counts during the integration period to achieve high resolution of the measured signal. In order to achieve 16-bit resolution, more than 65,000 counting events are required. As an example, at a minimum capacitance of 25fF and a saturation voltage of 0.5V, a charge of 820pC will be required to achieve 16-bit resolution. Therefore, for sensors that generate small currents, IAF circuits generally do not generate enough digital resolution.

[0019] Problem to be solved

[0020] Therefore, it is desirable to provide a readout circuit, a photodetector and a method for reading out an analog sensor charge that overcomes the above-mentioned disadvantages of known similar types of devices and methods. In particular, these devices and methods should be suitable for reducing the size, complexity, cost, power consumption and noise of the readout circuit (particularly the photodetector) while still ensuring reliable and accurate readout, in particular the readout of small analog sensor charges. Summary of the invention

[0021] This problem is solved by a readout circuit, a photodetector and a method for reading out an analog sensor charge having the features of the independent claims. Advantageous embodiments are listed in the dependent claims and in the entire description, which can be realized individually or in any arbitrary combination.

[0022] In a first aspect of the present invention, a readout circuit is disclosed.

[0023] As used herein, the term "readout" is a broad term and will be given its ordinary and conventional meaning for a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, the action or process of quantifying and / or processing at least one physical property and / or a change in at least one physical property detected by at least one device (specifically, by at least one measuring device, such as, at least one sensor). The measuring device may specifically include at least one photodetector. The photodetector may specifically include at least one photosensitive area. The readout may include a single readout of a device (such as a sensor). Additionally or alternatively, the readout may include a readout of a group of devices (such as a group of sensors). As used herein, the term "readout circuit" is a broad term and will be given its ordinary and conventional meaning for a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to quantify and / or process at least one physical property and / or a change in at least one physical property detected by at least one measuring device (such as, a sensor). The readout circuit may be configured to read out at least one sensor. In particular, the readout circuit may be configured for reading out at least one photodetector or at least one sensor of a photodetector.

[0024] As used herein, the term "sensor" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, any element or device configured to detect at least one condition or to measure at least one measurement variable. As an example, the sensor may be a photosensitive sensor such as used in a photodetector. However, other options are also possible. Specifically, the sensor may be capable of generating at least one signal (such as a measurement signal) that is a qualitative or quantitative indicator of a measurement variable and / or a measurement attribute (e.g., illumination of the sensor). The signal may be or include an electrical signal, such as an electric current or an electric charge.

[0025] As used herein, the term "photodetector" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a measuring device configured to detect optical radiation, such as for detecting illumination and / or light spots generated by at least one light beam. A photodetector may be and / or may include a photoconductor or a photodiode. A photodetector may include at least one substrate. A single photodetector may be a substrate having at least one single photosensitive area that generates a physical response to illumination of a given wavelength range. The photodetector includes at least one sensor configured to generate an analog sensor charge based on illumination of a photosensitive area of ​​the sensor.

[0026] As used herein, the term "photosensitive region" is a broad term and will be given its ordinary and customary meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a region that is sensitive to illumination, such as an incident light beam. For example, the photosensitive region may be a two-dimensional or three-dimensional region, which may preferably but not necessarily be continuous and / or may form a continuous region. The photosensitive region may include at least one photoconductive material selected from the group consisting of: lead sulfide (PbS); lead selenide (PbSe); mercury cadmium (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); extrinsic semiconductor, organic semiconductor. In particular, the photodetector may include a plurality of sensors, wherein the sensors may be arranged in an array.

[0027] As used herein, the term "light" is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, electromagnetic radiation in one or more of the visible spectrum range, the ultraviolet spectrum range, and the infrared spectrum range. Wherein, in part according to standard ISO-21348, the term "visible spectrum range" generally refers to the spectrum range of 380nm to 760nm. The term "infrared (IR) spectrum range" generally refers to electromagnetic radiation in the range of 760nm to 1000μm, wherein the range of 760nm to 1.4μm is generally referred to as the near infrared (NIR) spectrum range, and the range of 15μm to 1000μm is referred to as the far infrared (FIR) spectrum range. The term "ultraviolet spectrum range" generally refers to electromagnetic radiation in the range of 1nm to 380nm, preferably in the range of 100nm to 380nm. The term "light" may also be expressed as irradiation. Preferably, the illumination as used in the present invention is visible light (ie light in the visible spectral range), and / or infrared light (ie light in the infrared spectral range).

[0028] The photosensitive area can be illuminated by at least one illumination source. The illumination source can, for example, be or include an ambient light source and / or can be or include an artificial illumination source. By way of example, the illumination source can include at least one infrared emitter and / or at least one emitter for visible light and / or at least one emitter for ultraviolet light. By way of example, the illumination source can include at least one light emitting diode and / or at least one laser diode. The illumination source can in particular include one or more of the following illumination sources: a laser, in particular a laser diode, but in principle alternatively or additionally also other types of lasers can be used; a light emitting diode; an incandescent lamp; a neon lamp; a flame source; an organic light source, in particular an organic light emitting diode; a structured light source. Alternatively or additionally, other illumination sources can also be used.

[0029] The illumination source may be any light source having at least one radiation wavelength overlapping with the sensitive wavelength of the photodetector. The illumination source may typically be adapted to emit light in at least one of the following spectral ranges: ultraviolet spectral range, infrared spectral range. Most preferably, at least one illumination source is adapted to emit light in the NIR and IR ranges, preferably in the range of 800nm ​​to 5000nm, most preferably in the range of 1000nm to 4000nm. The illumination source may comprise at least one discontinuous light source. The illumination source may be configured to generate at least one modulated light beam. Alternatively, the illumination source may comprise at least one continuous light source. The light beam generated by the illumination source may be non-modulated and / or may be modulated by another optical device.

[0030] The readout circuit is configured to convert the analog sensor charge into a digital output count. The readout circuit includes at least one integrate and fire (IAF) circuit. The IAF circuit is configured to convert the analog sensor charge into a first digital output count. The readout circuit is further configured to process an analog voltage residual after a final IAF cycle. The readout circuit includes at least one analog-to-digital converter (ADC). The ADC is configured to convert the analog voltage residual into a second digital output.

[0031] As used herein, the term "analog signal" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and will not be limited to a special or custom meaning. The term may specifically refer to, but is not limited to, the continuous progression of a physical quantity. As used herein, the term "analog sensor charge" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and will not be limited to a special or custom meaning. The term may specifically refer to, but is not limited to, the continuous progression of a charge in time. As an example, the analog sensor charge may vary continuously over time by accumulation (e.g., due to irradiation of a photosensitive region of a photodetector). Additionally or alternatively, the analog sensor charge may vary continuously over time, for example, by dissipation (e.g., due to being transmitted to another electrical component).

[0032] As used herein, the term "digital" is a broad term and will be given its ordinary and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a finite or at least countable set of quantized or discrete signal values. As used herein, the term "digital output count" is a broad term and is given its ordinary and customary meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a digital count or digital statistics given by a readout circuit. Specifically, the digital output count may be a count or statistics using at least one of a natural number, a positive integer, and an integer. As an example, the digital output count may start at 0 and increment by 1 for each event that causes the count (e.g., irradiating a photosensitive area of ​​a photodetector with a certain intensity). The digital output count may be given in a Boolean domain, such as by using a binary digit (also referred to as a bit). Other options may also be feasible. The digital output may be output to at least one processor for further processing, such as for evaluating at least one sensor signal to generate measurement data that can be displayed to a user.

[0033] The readout circuit includes at least one integration and excitation circuit (IAF circuit). As used herein, the term "integration and excitation circuit (also referred to as IAF circuit)" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to integrate the incoming analog sensor charge, for example, by using an integrator and, for example, by using a comparator to excite an event signal when the output voltage reaches a predefined quantization threshold. The event may be used to reset the integrator so as to start integrating the incoming analog sensor charge again. The incoming analog sensor charge may, for example, be based on at least one capacitive feedback transimpedance amplifier (CTIA). Different types of IAF circuits are generally known to the skilled person, for example, by the following publication, Dei Michele et al. "Highly linear integrate-and-fire modulators with softreset for low-power high-speed imagers", 2017 IEEE International Conference on Circuits and Systems (ISCAS), IEEE, 2017, which is incorporated herein in its entirety. Without limitation, specific embodiments of the IAF circuit will be further outlined in detail below.

[0034] The IAF circuit is configured to convert the analog sensor charge into a first digital output count.

[0035] The IAF circuit may include at least one integrator. As used herein, the term "integrator" is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to integrate at least one input signal specifically over time. In other words, an integrator may be configured to accumulate input signals over time. Specifically, the integrator may be a current integrator. The integrator may be configured to measure analog sensor charge. The integrator may include at least one of an operational amplifier and a capacitor. The operational amplifier may be an inverting operational amplifier. The operational amplifier and the capacitor may be connected in parallel. The IAF circuit may specifically include at least one capacitor, wherein the IAF circuit may be configured to use a capacitor to adopt a linear property of charge-to-voltage conversion. The integrator may include at least one mixed signal circuit, specifically for resetting the integrator. The integrator may include at least one charge amplifier. Further options are feasible and are generally well known to the technician.

[0036] The input of the op amp can be held at a known voltage, V refThe integrator can be configured to reset the output of the op amp to V after each saturation event. ref The integrator can be configured to operate at a reference voltage V ref The comparator voltage V comp The output of the operational amplifier is integrated between the int Therefore, the output of the operational amplifier V int Can be V ref ≥V int ≥V comp .

[0037] As used herein, the term “integrated voltage (also referred to as V int )” is a broad term and is to be given its ordinary and customary meaning to one of ordinary skill in the art and is not to be limited to a special or custom meaning. The term specifically may refer to, but is not limited to, a voltage output generated by an integrator, specifically an operational amplifier of the integrator.

[0038] As used herein, the term “reference voltage (also referred to as V ref )” is a broad term and shall be given its ordinary and customary meaning to a person of ordinary skill in the art and shall not be limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a predefined voltage used as a reference, specifically for an integrator. The reference voltage may specifically be applied to an operational amplifier of the integrator, specifically to a first of two typical inputs of the operational amplifier. The analog sensor charge may specifically be fed to a second input of the operational amplifier. The output of the operational amplifier may specifically be further fed to the second input via a capacitor.

[0039] As used herein, the term “comparator voltage (also referred to as V comp )” is a broad term and is to be given its ordinary and customary meaning to one of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a predefined voltage used as a reference or threshold, particularly for a comparator.

[0040] Generally, the terms "first", "second" and, if applicable, further numbers are used herein merely as designations and do not indicate an order or ranking. Specifically, the first entity may be different from the second entity. However, the first entity and the second entity may also at least partially include each other, or may also be of at least the same type.

[0041] The IAF circuit may further include at least one comparator configured to determine a saturation event. The comparator may be configured to convert V int With V compSpecifically, the comparator can be configured to detect V int When is equal to V comp The comparator can be configured to int Exceed V comp When an event signal is generated, it is also represented as an event. As used herein, the term "comparator" is a broad term and will be given its ordinary and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to compare at least two input signals (specifically, voltages). The comparator may be configured to generate at least one output signal, specifically a digital output signal, indicating a comparison result (e.g., which input signal is larger). As an example, in the case where the first input voltage is higher than the second input voltage, the comparator may generate an output "HIGH" or "1", and in the case where the first input voltage is lower than the second input voltage, the comparator may generate an output "LOW" or "0". The output signal may be generated continuously over time, specifically for changing the input signal.

[0042] The comparator may be and / or may include at least one Schmitt trigger. The Schmitt trigger may be an inverting or non-inverting Schmitt trigger. As used herein, the term "Schmitt trigger" is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a comparator circuit in which the on threshold and the off threshold offset each other through switch hysteresis. The Schmitt trigger may be configured to compare an input voltage (specifically, a voltage that varies over time) with two threshold voltages (an upper threshold voltage and a lower threshold voltage). Specifically, the Schmitt trigger may be configured to give HIGH or 1 when the input voltage is higher than the upper threshold voltage, and to give LOW or 0 when the input voltage is lower than the lower threshold voltage, wherein the Schmitt trigger may be further configured to maintain the previous output between the upper threshold voltage and the lower threshold voltage. In other words, as long as the input voltage does not exceed one of the two threshold voltages, the output of the Schmitt trigger will not change. However, other options for the comparator are also feasible.

[0043] After reset, the output of the op amp can start at a known voltage, V ref The output of the op amp can decrease as the charge from the sensor is integrated. The output of the op amp can be connected to the comparator V- input. When the output of the op amp / comparator V- input drops below the comparator V+ terminal, the comparator output can switch to HIGH. The switching of the comparator can trigger a reset circuit that pulls the output of the op amp back to the initial voltage state V ref, so that the integration cycle can start again. The change of the comparator output to HIGH can be a saturation event that triggers the reset of the integrator. The comparator output change can in particular increase the counter value by 1 at the same time. In this way, the integration cycle can be counted. Each completed integration cycle can cause the first digital output count to be incremented by 1.

[0044] As used herein, the term "saturation event" is a broad term and will be given its ordinary and customary meaning to those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, saturation or satiation of an electrical component (specifically an integrator, more specifically a capacitor of an integrator).

[0045] The integrating capacitor value affects the frequency of saturation events in the system. Thus, a smaller capacitor generates a higher number of saturation events per second than a larger capacitor. Thus, for the same charge, a smaller capacitor will count more events than a larger capacitor. The capacitance of a capacitor may be defined by the size of the capacitor, such as by the ratio of the area of ​​the capacitor plates divided by the distance between the capacitor plates. The occurrence of a saturation event may refer to a completed integration cycle of the integrator.

[0046] The IAF circuit may further include at least one counter configured to determine the first digital output count by counting saturation events. As used herein, the term "counter" is a broad term and will be given its common and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to count events. In other words, the counter may be configured to store the number of times a particular event has occurred. Specifically, for each determined saturation event, the counter may be incremented by 1. The counter may include at least one output. The counter may be configured to give a count, or in other words, give the number of times a particular event has occurred, specifically in a binary number system. Other options are also feasible. The counter may include at least one input. The input of the counter may be connected to the above-mentioned comparator. Another input of the counter may be connected to a clock, specifically a global clock of a system (e.g., a readout circuit). The counter may include a plurality of triggers connected in cascade. The counter may be a synchronous counter. The trigger may be triggered simultaneously by the clock. However, the counter may also be an asynchronous counter. Other options are also feasible and are generally well known to technicians. The first digital output count (also denoted as the IAF digital output) may represent a positive integer of saturation events for a given input charge. The first digital output count may be proportional to a positive integer of an integration period. Specifically, the counter of the IAF circuit may be a most significant bit (MSB) counter. The MSB counter may be configured to determine the most significant bit of the output of the readout circuit. The readout circuit may include at least one switch for resetting the MSB counter. For example, the MSB counter may include a reset pin to reset the count back to 0.

[0047] The IAF circuit may further include at least one mixed signal circuit configured to convert the output V of the operational amplifier to int Reset to V ref The mixed signal circuit may be connected in parallel to the integrator or the capacitor of the integrator, thereby creating a short circuit when closed. The mixed signal circuit may be an electrical switch or an electromechanical switch. Specifically, the mixed signal circuit may include at least one transmission gate. Resetting the output of the operational amplifier may be a key component of the IAF. The IAF circuit may be configured to ensure that a reset occurs quickly and automatically after each saturation event. After each event, the analog voltage needs to always return to V ref .

[0048] As outlined above, the comparator can be configured to int Reach V compHowever, during the final integration period (also denoted as final IAF period) of integrating the incoming analog sensor charge, there may be margin because the integrated voltage does not reach the quantization threshold V comp (V int >V comp ), so the remainder cannot trigger the triggering of the event and is therefore not counted. As used herein, the term "analog voltage remainder" is a broad term and will be given its ordinary and conventional meaning to one of ordinary skill in the art and is not limited to a special or custom meaning. The term specifically may refer to, but is not limited to, the remainder, remainder, or remnant left after the IAF circuit completes processing of the analog sensor charge, specifically at the end of the final completed integration cycle. The remainder may be one or more of characterized, described, or quantified using at least one analog voltage. The analog voltage remainder may refer to the remainder of the final uncompleted integration cycle.

[0049] The readout circuit is configured to process the analog voltage margin after the final IAF cycle. The IAF circuit can be configured to digitize the analog sensor charge to at least the analog voltage margin. As used herein, the term "digitalization" (including any grammatical variations thereof) is a broad term and will be given its ordinary and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a process for converting or transmitting at least one analog input signal (specifically analog sensor charge) to at least one digital output signal (specifically digital output count). Digitization may include detecting and / or quantizing the analog input signal, specifically so as to subsequently convert it. The non-digitalizable margin may be an entity that is not detectable and / or quantifiable by the IAF circuit. An uncompleted integration cycle may specifically be non-quantifiable by the IAF circuit, and therefore non-digitized by the IAF circuit, while a completed integration cycle may be digitized by incrementing a counter of the IAF circuit. As an example, the analog sensor charge may not be sufficient to generate a completed integration cycle in the IAF circuit, so that the analog sensor charge as a whole may not be digitizable. Therefore, particularly for small analog sensor charges, the IAF circuit may not be sufficient.

[0050] The readout circuit further includes at least one analog-to-digital converter (ADC) configured to convert the analog voltage residue into a second digital output. As used herein, the term "second digital output" is a broad term and will be given its ordinary and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term specifically may refer to, but is not limited to, any digital output proportional to the residue voltage of the final unfinished integration cycle generated by the ADC. For example, the second digital output may be a digital output count. However, other options are also feasible. The second digital output may be proportional to the residue voltage of the final but unfinished integration cycle. The ADC may be a least significant bit (LSB) counter, also referred to as an LSB counter. The LSB counter may be configured to determine the least significant bit of the output of the readout circuit.

[0051] The readout circuit can be configured to determine the combined digital output count by combining the first digital output count and the second digital output. The combined digital output count can be given in a binary number system. The IAF circuit can be configured to determine the most significant bit (MSB), and the ADC can be configured to determine the least significant bit. The counter of the IAF circuit can also be referred to as an MSB counter, and the counter of the ADC can also be referred to as an LSB counter. The M bits of the MSB counter can represent the number of completed integration cycles, and the N bits of the LSB counter can represent the binary completion value of the residual voltage on the IAF. The combined digital value of the MSB and LSB cascade can represent the N+M bit digital resolution. The readout circuit can include at least one output unit or at least one interface. The output unit can be configured to generate at least one output, specifically at least one digital output voltage signal, such as a combined digital output count. The output unit can be configured to pass the output to at least one external device or element, such as to a processor for further evaluation. As an example, the output unit can be configured to identify or mark the most significant bit and / or the least significant bit so that, for example, the processor can correctly assign them. Other options are also feasible.

[0052] The readout circuit further includes at least one analog-to-digital converter (ADC). The ADC is configured to convert the analog voltage margin into a second digital output. As used herein, the term "analog-to-digital converter (also referred to as ADC)" is a broad term and will be given its ordinary and conventional meaning for those of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, a circuit configured to convert or transmit at least one analog input signal (specifically analog sensor charge) into at least one digital output signal (specifically digital output count). Any known ADC architecture can be used for the ADC to convert the analog voltage margin into a second digital output. For example, the ADC may include at least one ADC architecture selected from the group consisting of: a counter ADC, a single slope ADC, a dual slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, a Sigma-Delta ADC. For an embodiment of the ADC, reference is made to "Analog-to-Digital Converter Architectures and Choices for System Design", Brian Black, Analog Dialogue 33-8 (1999). The ADC may have a low resolution, specifically 14 bits or less, more specifically 10 bits or less. It is possible to use a simple ADC that requires little power and requires only a small area.

[0053] For example, the ADC may be a counter type ADC, also known as a counter ADC or a slope ADC or a slope converter. However, as outlined above, other options are also possible and generally known to the skilled person. The ADC may specifically include at least one of a comparator (specifically a Schmitt trigger) and a counter. The V+ terminal of the comparator may be connected to the DAC via a 2 N Step size from V comp Ramp up to V int During the ramp-up period, V comp The voltage may exceed V int The margin voltage and can trigger the comparator output. At this point, the counter may be activated and each remaining V+ step from the DAC increments the counter. The final count on the counter can be the voltage margin V intA digital representation of a value. The readout circuit may include at least one switch for resetting the counter. For example, the counter may include a reset pin to reset the count back to 0. Using a counter-type ADC may allow sharing of a comparator circuit. The ADC and the IAF circuit may share at least one component, specifically at least one comparator. Specifically, the ADC and the IAF circuit may share the above-mentioned Schmitt trigger. For example, a Schmitt trigger connected to an integrator of the IAF circuit may also be used as part of the ADC. Then, an input of the counter of the ADC may be connected to an output of the Schmitt trigger. Another input of the counter of the ADC may be specifically connected to a clock, specifically a global clock of the readout circuit.

[0054] The readout circuit may further include at least one event processor. The event processor may be configured to identify an event generated by the comparator. The event processor may be configured to initiate a reset of the integrator based on an event, such as by initiating a mixed signal circuit. The event processor may be configured to initiate an IAF counter based on an event. The event processor may be configured to initiate a circuit for digitizing an analog voltage margin based on an event, particularly when a counter ADC is used. The event processor may be pre-connected to a counter of the ADC and / or a counter of the IAF circuit. The event processor may be configured to assign the output of the Schmitt trigger to a counter of the ADC and / or a counter of the IAF circuit.

[0055] When integration at the IAF circuit is complete, there may be an analog voltage margin, V, at the output of the op amp. int , so that V ref ≥V int >V comp The IAF circuit can be int Exceed V comp The IAF reset is automatically triggered when the IAF reset is triggered. The margin voltage can be the remaining voltage without triggering the IAF reset. The ADC can quantize the analog voltage margin to produce a value representing the binary completion percentage of the operational amplifier output voltage. The binary value 0 represents the voltage V int , binary value 2 N -1 means value V comp , where N is the number of bits of resolution of the ADC. Between 0 and 2 N ADC values ​​between -1 can represent the analog voltage margin.

[0056] The readout circuit can be configured to read out small analog sensor charges, specifically, analog sensor charges of less than 1 nC, more specifically, less than 1 pC. As explained, specifically, by using an ADC to determine the LSB, small analog sensor charges can also be digitized so that saturation events are not triggered at the integrator of the IAF circuit. This may be specifically related to the readout of a photodetector, or more specifically, to the readout of individual sensors of a photodetector, which may only generate very small photocurrents. The readout circuit can be configured to read out at least one sensor, the at least one sensor being configured to generate an analog sensor charge based on illumination of a photosensitive area of ​​the sensor.

[0057] The readout circuit can be configured to read out multiple sensors configured to generate analog sensor charges based on the illumination of the photosensitive area of ​​the sensor. The sensors can be arranged in an array. As used herein, the term "array" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term can specifically refer to, but is not limited to, the spatial arrangement of elements such as sensors. The array can be a one-dimensional array (e.g., a sequence of sensors along an axis) or a two-dimensional array (e.g., a sensor matrix). The array can also be a three-dimensional array. The array can be a regular array, for example, including a constant distance between elements. The array can be an irregular array, for example, including different distances between elements. The elements within the array can be of the same type or of different types. As an example, an array can include sensors that are sensitive to light at different wavelengths. Other options are also feasible.

[0058] The readout circuit may be a readout integrated circuit (ROIC). The readout circuit may be an integrated circuit (IC), also referred to as a chip or microchip, or the readout circuit may form at least a part of an IC. As known to the technician, an IC typically includes at least one circuit assembled on a substrate, specifically a semiconductor substrate, more specifically a silicon (Si) substrate. The readout circuit may be configured to accumulate at least one sensor current, specifically a photocurrent, wherein the accumulation of the sensor current may generate an analog sensor charge. As an example, the readout circuit may be configured to accumulate photocurrent for each sensor of a photodetector or for a sensor group of a photodetector. The readout circuit may be configured to store or at least buffer the analog sensor charge. The readout circuit may be configured to transfer the analog sensor charge to at least one output terminal, such as an output terminal of an IC, wherein the output terminal may specifically be a digital output terminal. The readout circuit may be a digital readout integrated circuit (DROIC). The DROIC may use on-chip analog-to-digital conversion, specifically for digitizing at least one accumulated photocurrent. The readout circuit may be a digital pixel readout integrated circuit (DPROIC). DPROIC uses on-chip analog-to-digital conversion within each pixel or pixel group, in particular for digitizing at least one accumulated photocurrent, wherein a pixel may in particular refer to a sensor of a photodetector.

[0059] In another aspect of the present invention, a photodetector is disclosed. The photodetector includes at least one sensor configured to generate an analog sensor charge based on irradiation of a photosensitive area of ​​the sensor. The photodetector includes at least one readout circuit according to any of the embodiments disclosed in further detail above or below. Further details and embodiments of the photodetector can refer to the description of the readout circuit above.

[0060] In another aspect of the present invention, a method for reading out an analog sensor charge is disclosed. The method comprises:

[0061] a) providing at least one readout circuit according to any one of the embodiments relating to a readout circuit disclosed in further detail above or below;

[0062] b) converting the analog sensor charge into a first digital output count and an analog voltage margin by using an IAF circuit; and

[0063] c) Converting the analog voltage residue into a second digital output by using an ADC.

[0064] The method may further comprise:

[0065] d) determining a combined digital output count by combining the first digital output count and the second digital output.

[0066] The method may include additional method steps not listed. Further, one or more of the method steps may be performed once or repeatedly. Further, two or more of the method steps may be performed simultaneously or in a time-overlapping manner.

[0067] As used herein, the term "providing" (including any grammatical variations thereof) is a broad term and is to be given its ordinary and customary meaning to one of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, at least one of: manufacturing a readout circuit, producing a readout circuit, using an existing readout circuit, applying an existing readout circuit, and modifying an existing readout circuit.

[0068] The readout may include reading out at least one sensor of a photodetector according to any one of the embodiments of the photodetector disclosed in further detail above or below. The resolution of the readout may be controlled by changing the resolution of the second digital output in step c). As used herein, the term "resolution" is a broad term and will be given its ordinary and conventional meaning to a person of ordinary skill in the art and is not limited to a special or custom meaning. The term may specifically refer to, but is not limited to, an indication of the degree of fine gradation to which a raw analog signal (such as an analog sensor charge or the light intensity irradiating the photodetector) can be digitized. Specifically, the resolution may indicate the degree of fine gradation to which an analog signal can be digitized. Therefore, the higher the resolution, the finer the step size of the digitized signal may be. An "N" bit ADC may increase the resolution of the readout circuit by "N" bits. Therefore, the resolution of the readout circuit may include a positive integer of saturation events and a decimal number associated with a final incomplete integration cycle. A positive integer of a saturation event may be captured by using an IAF circuit. A decimal number associated with a final incomplete integration cycle may be captured by using an ADC. The IAF circuit may have a lower sensitivity to current input or charge input, specifically compared to an ADC. As an example, for sufficiently high currents, the bits from the ADC may be reduced to adjust the resolution. Additionally or alternatively, the gain of the readout, specifically the charge to voltage gain, may be controlled by changing the resolution of the second digital output in step c). The gain may be controlled by utilizing more or fewer bits from the analog voltage margin.

[0069] In another aspect of the invention, the use of a readout circuit according to the invention for reading out one or more sensors in at least one PbS sensor, at least one PbSe sensor or at least one pixelated sensor array comprising a plurality of pixels is disclosed, wherein each of these pixels comprises at least one PbS sensor or a PbSe sensor. In particular, the readout circuit according to the invention can be used in moderate or low bias voltage applications, such as in applications where the device (e.g. sensor node, portable measurement device, device in an explosive environment) is battery powered or needs to be operated at low power, thereby allowing an improvement in the signal-to-noise ratio and thus an improvement in the signal quality. For example, the readout circuit can be used in a spectrometer, a humidity measuring instrument, a thickness measuring instrument, a gas analysis instrument or any other type of equipment using a photoconductor as a sensor element. The readout circuit can be used in an optical sensor. For example, the readout circuit can be used in an optical sensor employing the so-called FiP effect, such as WO 2012 / 110924 A1, WO 2014 / 097181 A1 and WO 2016 / 120392 A1.

[0070] In another aspect of the present invention, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium includes instructions that, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the method-related embodiments disclosed in further detail above or below.

[0071] This article further discloses and proposes a computer program, which includes computer executable instructions for executing the method according to the present invention in one or more embodiments contained in this article when the program is executed on a computer or a computer network. Specifically, the computer program can be stored on a computer readable data carrier and / or a computer readable storage medium.

[0072] As used herein, the terms "computer-readable data carrier" and "computer-readable storage medium" may specifically refer to a non-transitory data storage device, such as a hardware storage medium on which computer-executable instructions are stored. A computer-readable data carrier or storage medium may specifically be or may include a storage medium such as a random access memory (RAM) and / or a read-only memory (ROM).

[0073] Thus, in particular, one, more than one or even all of the method steps as indicated above may be performed by using a computer or a computer network, preferably by using a computer program.

[0074] This article further discloses and proposes a computer program product with program code means, so that when the program is executed on a computer or a computer network, the method according to the present invention in one or more embodiments contained in this article is performed. Specifically, the program code means can be stored on a computer-readable data carrier and / or a computer-readable storage medium.

[0075] This document further discloses and proposes a data carrier having a data structure stored thereon, which, after being loaded into a computer or a computer network (such as loaded into a working memory or a main memory of a computer or a computer network), can execute a method according to one or more embodiments disclosed herein.

[0076] This document further discloses and proposes a computer program product having program code means stored on a machine-readable carrier so that when the program is executed on a computer or computer network, a method according to one or more embodiments disclosed herein is performed. As used herein, a computer program product refers to a program that is a tradable product. The product can generally exist in any format, such as in paper format, or on a computer-readable data carrier and / or a computer-readable storage medium. In particular, the computer program product can be distributed via a data network.

[0077] Finally, a modulated data signal containing instructions readable by a computer system or a computer network for executing a method according to one or more embodiments disclosed herein is disclosed and proposed herein.

[0078] With reference to the computer-implemented aspects of the present invention, one or more or even all of the method steps of the methods according to one or more of the embodiments disclosed herein may be performed using a computer or a computer network. Thus, typically, any of the method steps including the provision and / or manipulation of data may be performed using a computer or a computer network. Typically, these method steps may include any method steps, except for method steps that typically require manual work, such as providing samples and / or performing certain aspects of the actual measurement.

[0079] Specifically, this article further discloses:

[0080] - a computer or a computer network comprising at least one processor, wherein the processor is adapted to execute the method according to one of the embodiments described in this specification,

[0081] - a computer-loadable data structure, which is suitable for performing a method according to one of the embodiments described in this specification when the data structure is executed on a computer,

[0082] - a computer program, wherein the computer program is adapted to perform a method according to one of the embodiments described in this specification when the program is executed on a computer,

[0083] - a computer program comprising program means for executing a method according to one of the embodiments described in this specification when the computer program is executed on a computer or on a computer network,

[0084] - a computer program comprising a program device according to the preceding embodiment, wherein the program device is stored on a computer-readable storage medium,

[0085] - a storage medium, on which a data structure is stored, and wherein the data structure is suitable for executing a method according to one of the embodiments described in the present description after being loaded into a main storage device and / or a working storage device of a computer or a computer network, and

[0086] A computer program product having program code means, wherein the program code means can be stored or stored on a storage medium for performing a method according to one of the embodiments described in the present description when the program code means is executed on a computer or a computer network.

[0087] The apparatus and methods according to the invention may provide a number of advantages over known apparatus and methods. In particular, they may be suitable for reducing the size, complexity, cost, power consumption and noise of the readout circuitry (particularly the photodetector), while still ensuring reliable and accurate readout, in particular the readout of small analog sensor charges. They may further allow a wider dynamic range to be achieved and greater flexibility in selecting the charge to voltage gain. As an example, 16-bit resolution may be achieved over a wider charge range.

[0088] As used herein, the terms "having", "comprise" or "include" or any of their arbitrary grammatical variations are used in a non-exclusive manner. Therefore, these terms can refer to the situation where there are no further features in the entity described in this context in addition to the features introduced by these terms, and can also refer to the situation where one or more further features are present. As an example, the expressions "A has B", "A includes B" and "A contains B" can refer to the situation where there are no other elements in A besides B (that is, the situation where A only and solely consists of B), and can also refer to the situation where there are one or more further elements in entity A in addition to B (such as element C, elements C and D or even further elements).

[0089] Further, it should be noted that the terms "at least one", "one or more", or similar expressions indicating that a feature or element may occur once or more than once are typically used only once when introducing the corresponding feature or element. In most cases, when referring to the corresponding feature or element, the expression "at least one" or "one or more" is not repeated, although in fact the corresponding feature or element may occur once or more than once.

[0090] Further, as used herein, the terms "preferably", "more preferably", "particularly", "more particularly", "specifically", "more specifically" or similar terms are used in conjunction with optional features without limiting the possibilities of alternatives. Therefore, the features introduced by these terms are optional features and are not intended to limit the scope of the claims in any way. As the skilled person will recognize, the present invention can be implemented by using alternative features. Similarly, the features introduced by "in an embodiment of the present invention" or similar expressions are intended to be optional features, without any limitation on alternative embodiments of the present invention, without any limitation on the scope of the present invention, and without any limitation on the possibility of combining the features introduced in this manner with other optional or non-optional features of the present invention.

[0091] Summarizing and without excluding further possible embodiments, the following embodiments may be envisaged:

[0092] Embodiment 1: A readout circuit configured to convert an analog sensor charge into a digital output count, wherein the readout circuit includes at least one integrate and fire (IAF) circuit, wherein the IAF circuit is configured to convert the analog sensor charge into a first digital output count, wherein the readout circuit is further configured to process an analog voltage remainder after a final IAF cycle, wherein the readout circuit includes at least one analog-to-digital converter (ADC), wherein the ADC is configured to convert the analog voltage remainder into a second digital output.

[0093] Embodiment 2: The readout circuit according to the preceding embodiment, wherein the readout circuit is configured to read out small analog sensor charges, specifically, analog sensor charges less than 1 nC, more specifically less than 1 pC.

[0094] Embodiment 3: The readout circuit according to any of the preceding embodiments, wherein the readout circuit is configured to read out at least one sensor, the at least one sensor being configured to generate the analog sensor charge based on illumination of a photosensitive region of the sensor.

[0095] Embodiment 4: The readout circuit according to the previous embodiment, wherein the readout circuit is configured to read out a plurality of sensors configured to generate the analog sensor charge based on illumination of photosensitive areas of the sensors, wherein the sensors are arranged in an array.

[0096] Embodiment 5: A readout circuit according to any one of the two preceding embodiments, wherein the photosensitive area comprises at least one photoconductive material selected from the group consisting of: lead sulfide (PbS); lead selenide (PbSe); mercury cadmium tetrahedron (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); extrinsic semiconductors, organic semiconductors.

[0097] Embodiment 6: A readout circuit according to any one of the preceding embodiments, wherein the readout circuit is configured to determine a combined digital output count by combining the first digital output count and the second digital output, wherein the first digital output count (118) is proportional to a positive integer of an integration period, and wherein the second digital output (124) is proportional to a residual voltage of a final incomplete integration period.

[0098] Embodiment 7: The readout circuit according to any of the preceding embodiments, wherein the IAF circuit is configured to digitize the analog sensor charge to at least the analog voltage margin, wherein the analog voltage margin is a margin that is not digitizable by the IAF circuit.

[0099] Embodiment 8: The readout circuit according to any one of the preceding embodiments, wherein the IAF circuit comprises

[0100] - at least one integrator, wherein the integrator comprises at least one operational amplifier and at least one capacitor, wherein the input of the operational amplifier is maintained at a known voltage V ref , wherein the integrator is configured to reset the output of the operational amplifier to V after each saturation event ref , wherein the integrator is configured to ref The comparator voltage V comp The output of the operational amplifier is integrated to determine the integrated voltage V int ;

[0101] at least one comparator, in particular at least one Schmitt trigger, configured to determine a saturation event;

[0102] - at least one counter configured to determine a first digital output count by counting the saturation events; and

[0103] - at least one mixed signal circuit configured to, after each saturation event, int Reset to V ref .

[0104] Embodiment 9: The readout circuit according to the preceding embodiment, wherein the analog voltage margin is a residual voltage without triggering a saturation event after a final IAF cycle.

[0105] Embodiment 10: A readout circuit according to any one of the preceding embodiments, wherein the ADC comprises at least one ADC architecture selected from the group consisting of: counter-type ADC, single-slope ADC, dual-slope ADC, pipeline ADC, successive approximation register (SAR) ADC, Sigma-Delta ADC.

[0106] Embodiment 11: The readout circuit according to any of the preceding embodiments, wherein the ADC comprises a counter-type ADC, wherein the ADC and the IAF circuit share at least one component, in particular at least one comparator.

[0107] Embodiment 12: The readout circuit according to any one of the preceding embodiments, wherein the ADC has a low resolution, specifically 14 bits or less, more specifically 10 bits or less.

[0108] Embodiment 13: A photodetector comprising

[0109] - at least one sensor configured to generate an analog sensor charge in response to illumination of a photosensitive area of ​​the sensor; and

[0110] - at least one readout circuit according to any of the preceding embodiments.

[0111] Embodiment 14: The photodetector according to the preceding embodiment, wherein the photodetector comprises a plurality of sensors, wherein the sensors are arranged in an array.

[0112] Embodiment 15: A photodetector according to any one of the aforementioned embodiments involving photodetectors, wherein the photosensitive area includes at least one photoconductive material selected from the group consisting of: lead sulfide (PbS); lead selenide (PbSe); mercury cadmium tetrahedron (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); extrinsic semiconductors, organic semiconductors.

[0113] Embodiment 16: A method for reading out an analog sensor charge, the method comprising:

[0114] a) providing at least one readout circuit according to any one of the preceding embodiments relating to a readout circuit;

[0115] b) converting the analog sensor charge into a first digital output count and an analog voltage margin by using an IAF circuit; and

[0116] c) Converting the analog voltage residue into a second digital output by using an ADC.

[0117] Embodiment 17: The method according to the previous embodiment further comprises:

[0118] d) determining a combined digital output count by combining the first digital output count and the second digital output.

[0119] Embodiment 18: The method according to any one of the preceding method embodiments, wherein the reading comprises reading out at least one sensor of at least one photodetector according to any one of the preceding embodiments involving photodetectors.

[0120] Embodiment 19: A method according to any one of the preceding method embodiments, wherein the resolution of the readout is controlled by changing the resolution of the second digital output in step c).

[0121] Embodiment 20: The method according to any one of the preceding method embodiments, wherein the gain of the readout, in particular the charge-to-voltage gain, is controlled by changing the resolution of the second digital count in step c).

[0122] Embodiment 21: A non-transitory computer-readable medium, which includes instructions, which when executed by one or more processors, cause the one or more processors to perform any of the methods described in the preceding embodiments.

[0123] Embodiment 22: Use of a readout circuit according to any one of the aforementioned embodiments relating to a readout circuit for reading out at least one PbS sensor, at least one PbSe sensor, or one or more sensors in at least one pixelated sensor array comprising a plurality of pixels, wherein each of these pixels comprises at least one PbS sensor or a PbSe sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] Other optional features and embodiments are preferably disclosed in more detail in the subsequent description of the embodiments in conjunction with the dependent claims. Wherein, as the skilled person will recognize, the corresponding optional features can be implemented in an independent manner and in any arbitrary feasible combination. The scope of the present invention is not limited by the preferred embodiments. The embodiments are schematically depicted in the accompanying drawings. Wherein, the same reference numerals in these drawings represent the same or functionally equivalent elements.

[0125] In the attached picture:

[0126] Figure 1 An exemplary embodiment of a schematic circuit diagram of a readout circuit is shown;

[0127] FIG. 2A to FIG. 2B Another exemplary embodiment of a schematic circuit diagram of a readout circuit and a corresponding voltage diagram are shown;

[0128] FIG. 3A to FIG. 3B shows experimental results of measurements on an exemplary embodiment of a readout circuit;

[0129] Figure 4 An exemplary embodiment of a photodetector is shown; and

[0130] Figure 5 A flow chart of an exemplary embodiment of a method for reading out an analog sensor charge is shown. DETAILED DESCRIPTION

[0131] Figure 1 An exemplary embodiment of a schematic circuit diagram of a readout circuit 110 is shown. The readout circuit 110 is configured to convert an analog sensor charge 112 into a digital output count 114. The readout circuit 110 includes at least one integrate and fire (IAF) circuit 116. The IAF circuit 116 is configured to convert the analog sensor charge into a first digital output count 118. The readout circuit 110 is further configured to process an analog voltage residual 120 after a final IAF cycle. The readout circuit 110 includes at least one analog-to-digital converter (ADC) 122. The ADC 122 is configured to convert the analog voltage residual into a second digital output 124. The readout circuit 110 may be a circuit configured to quantize and / or process at least one physical property and / or a change in at least one physical property detected by at least one measurement device.

[0132] like Figure 1 As shown, the IAF circuit 116 and the ADC 122 may be separate entities. However, as will be further outlined in detail below, the IAF circuit 116 and the ADC 122 may also at least partially share components. At a minimum, the IAF circuit 116 and the ADC 122 may be connected to each other, or more specifically, their components may be connected to each other. The ADC 122 may be an extension of the IAF circuit 116. In the following, the components of the IAF circuit 116 and the ADC 122 will be referred to as Figure 1 to describe.

[0133] The IAF circuit 116 may be a circuit configured to integrate the incoming analog sensor charge 112 and fire an event 126 when the output voltage reaches a predefined quantization threshold. Event 126 may be used to reset the integrator 128 to start integrating the incoming analog sensor charge 112 again. Different types of IAF circuits are generally known to the skilled person, for example, by the following publication, Dei Michele et al. "Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers", 2017 IEEE International Conference on Circuits and Systems (ISCAS), IEEE, 2017, which is incorporated herein in its entirety. The IAF circuit 116 may include at least one integrator 128. The integrator 128 may be a circuit configured to integrate at least one input signal specifically over time. The integrator 128 may be configured to accumulate the input signal over time. Specifically, the integrator 128 may be a current integrator 128. The integrator 128 may be configured to measure the analog sensor charge 112. The integrator 128 may include at least one of an operational amplifier 130 and a capacitor 132. The operational amplifier 130 may be an inverting operational amplifier 130. The operational amplifier 130 and the capacitor 132 may be connected in parallel. The IAF circuit 116 may specifically include at least one capacitor 132, wherein the IAF circuit 116 may be configured to exploit the linear nature of the charge-to-voltage conversion using the capacitor 132. The integrator 128 may include at least one mixed signal circuit 134, specifically for resetting the integrator 128. Therefore, the IAF circuit 116 may include at least one mixed signal circuit 134, which is configured to reset V after each saturation event 126. int. The mixed signal circuit 134 can be connected in parallel to the integrator 128 or the capacitor 132 of the integrator 128, thereby creating a short circuit when closed. The mixed signal circuit 134 can be an electrical switch or an electromechanical switch. The mixed signal circuit 134 may include at least one transistor, such as a field effect transistor or a bipolar junction transistor. Specifically, the mixed signal circuit 134 may include at least one transmission gate. The reset of the output of the operational amplifier 130 can be a key component of the IAF circuit 116. The IAF circuit 116 can be configured to ensure that the reset occurs quickly and automatically after each saturation event 126. After each event 126, the analog voltage needs to always return to V ref .

[0134] The input of operational amplifier 130 can be maintained at a known voltage V ref Integrator 128 may be configured to reset the output of op amp 130 to V after each saturation event 126. ref The integrator 128 can be configured to ref With the comparator voltage V comp The output of the operational amplifier 130 is integrated to determine the integrated voltage V int Therefore, the output V of the operational amplifier 130 is int Can be V ref ≥V int ≥V comp .

[0135] The IAF circuit 116 may further include at least one comparator 136 configured to int Reach V comp The comparator 136 may be configured to trigger the event 126. The comparator 136 may be configured to compare at least two input signals (specifically voltages, such as V int and V comp ) circuit. The comparator 136 can be configured to generate at least one output signal, specifically a digital output signal, indicating a comparison result (e.g., which input signal is larger). As an example, when the first input voltage is higher than the second input voltage, the comparator 136 can generate an output "HIGH" or "1", and when the first input voltage is lower than the second input voltage, the comparator can generate an output "LOW" or "0". The output signal can be continuously generated over time, specifically for changing the input signal. The comparator 136 can be configured to convert V int With V comp Specifically, the comparator 136 can be configured to detect V int When is equal to V compThe comparator 136 can be configured to int Exceed V comp When an event signal is generated, it is also represented as an event.

[0136] The comparator 136 may be and / or may include at least one Schmitt trigger 138. The Schmitt trigger 138 may be an inverting or non-inverting Schmitt trigger 138. The Schmitt trigger 138 may be a comparator circuit in which the on threshold and the off threshold offset each other through switch hysteresis. The Schmitt trigger 138 may be configured to compare an input voltage (specifically, a voltage that varies over time) with two threshold voltages (an upper threshold voltage and a lower threshold voltage). Specifically, the Schmitt trigger 138 may be configured to give a HIGH or 1 when the input voltage is higher than the upper threshold voltage, and give a LOW or 0 when the input voltage is lower than the lower threshold voltage, wherein the Schmitt trigger 138 may be further configured to maintain the previous output between the upper threshold voltage and the lower threshold voltage. As long as the input voltage does not exceed one of the two threshold voltages, the output of the Schmitt trigger 138 will not change. However, other options for the comparator 136 are also feasible. The comparator 136 may be connected to the output of the integrator 128, specifically to the output of the operational amplifier 130 of the integrator 128. The comparator 136 (particularly the output of the comparator 136) may be further connected to at least one switch controller 140. The switch controller 140 may be configured to control the mixed signal circuit 134 to reset the integrator 128. The readout circuit 110 (particularly the ADC 122) may include at least one switch 141. The switch controller 140 may be configured to control the switch 141.

[0137] The IAF circuit 116 may further include at least one counter 142 configured to determine the first digital output count 118 by counting the saturation events 126. The counter 142 may be a circuit configured to count the events 126. The counter 142 may be configured to store the number of times the specific event 126 has occurred. Specifically, for each determined saturation event 126, the counter 142 may be incremented by 1. The counter 142 may include at least one output terminal. The counter 142 may be configured to give a count. The counter 142 may be configured to give the number of times the specific event 126 has occurred, specifically in a binary number system. The counter 142 may include a plurality of flip-flops connected in cascade. The counter 142 may be a synchronous counter or an asynchronous counter 142. The counter 142 may include at least one input terminal. The input terminal of the counter 142 may be connected to the above-mentioned comparator 136. The readout circuit 110 may include a plurality of counters 142. Specifically, the counter 142 of the IAF circuit 116 may be an MSB counter 144. The MSB counter 144 may be configured to determine the most significant bit (MSB) of the output of the readout circuit 110. The MSB counter 144 may be configured to determine the first digital output count 118. Another input of the MSB counter 144 may be connected to a shutter 146, specifically to a global shutter 146, such as a global shutter 146 shared with the ADC 122 of the readout circuit 110. The global shutter 146 may be configured to transmit at least one signal (specifically a voltage) from the IAF circuit 116 to the ADC 122.

[0138] ADC 122 may be a circuit configured to convert or transmit at least one analog input signal (specifically analog sensor charge 112) to at least one digital output signal (specifically digital output count 114). For example, ADC 122 may be a counter-type ADC 122. However, in principle, any known ADC architecture may be used for ADC 122 to convert the analog voltage margin into a second digital output. For example, the ADC may include at least one ADC architecture selected from the group consisting of: a counter-type ADC, a single slope ADC, a dual slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, a Sigma-Delta ADC. For an embodiment of ADC 122, reference is made to "Analog-to-Digital Converter Architectures and Choices for System Design", Brian Black, Analog Dialogue 33-8 (1999). ADC 122 may have a low resolution, specifically 14 bits or less, more specifically 10 bits or less. It is possible to use a simple ADC that requires little power and only a small area. ADC 122 may specifically include at least one of a comparator 136 (specifically a Schmitt trigger 138) and a counter 142. The V+ terminal of the comparator 136 may be converted to a digital-to-analog converter (DAC) at 2 N Step size from V comp Ramp up to V int During the ramp-up period, V comp The voltage may exceed V int The margin voltage and may trigger the comparator output. At this point, counter 142 may be activated and each remaining V+ step from the DAC increments the counter. The final count on counter 142 may be the voltage margin V int The readout circuit 110 may include at least one switch 141 for resetting the counter 142. For example, the counter 142 may include a reset pin to reset the count back to 0. Using a counter-type ADC may allow for sharing of comparator circuits.

[0139] As already indicated, in principle, the ADC 122 and the IAF circuit 116 may share at least one component, in particular at least one comparator 136. In particular, the ADC 122 and the IAF circuit 116 may share a Schmitt trigger 138. For example, the Schmitt trigger 138 connected to the integrator 128 of the IAF circuit 116 may also be used as part of the ADC 122. However, as described above and as Figure 1As shown, the ADC 122 and the IAF circuit 116 may also be separate entities, which may be connected to each other in particular by using a shutter 146. In particular, the ADC 122 may be an extension of the IAF circuit 116. An input of the comparator 136 of the ADC 122 may be connected to an output of the comparator 136 of the IAF circuit 116 by using the shutter 146. Another input of the comparator 136 of the ADC 122 may be connected to a ramp voltage V ramp , so that the integrated voltage V transmitted from the IAF circuit 116 int Can be compared with V in ADC122 ramp Make a comparison.

[0140] As described above, the ADC 122 may further include at least one counter 142. An input of the counter 142 of the ADC 122 may be connected to an output of the Schmitt trigger 138 of the ADC 122. The counter 142 of the ADC 122 may be an LSB counter 148. The LSB counter 148 may be configured to determine the least significant bit (LSB) of the output of the readout circuit 110. As indicated, an input of the LSB counter 148 may be connected to an output of the comparator 136 of the ADC 122. Another input of the LSB counter 148 may be specifically connected to a clock 150, specifically a global clock 150 of the readout circuit 110. The LSB counter 148 may be a synchronous counter 142 triggered by the clock 150. The LSB counter 148 may be configured to determine a second digital output 124. The second digital output 124 may be any digital output proportional to the residual voltage of the final uncompleted integration cycle generated by the ADC 122. For example, the second digital output 124 may be a digital output count. However, other options are also feasible. Second digital output 124 may be proportional to the residual voltage of the final but incomplete integration cycle. ADC 122 may be a least significant bit (LSB) counter 142, such as LSB counter 148. LSB counter 148 may be configured to determine the least significant bit of the output of readout circuit 110.

[0141] The readout circuit 110 can be configured to determine the combined digital output count 114 by combining the first digital output count 118 and the second digital output 124. The combined digital output count 114 can be given in a binary number system. As described, the IAF circuit 116 can be configured to determine the most significant bit (MSB), and the ADC 122 can be configured to determine the least significant bit (LSB). The M bits of the MSB counter 144 can represent the number of completed integration cycles, and the N bits of the LSB counter 148 can represent the binary completion value of the residual voltage on the IAF. The combined digital value of the MSB and the LSB cascade can represent an N+M bit digital resolution. The readout circuit 110 may include at least one output unit 152 and / or at least one interface, such as to at least one other device, such as for further evaluation. The output unit 152 can be configured to generate at least one output, specifically at least one digital output voltage signal, such as the combined digital output count 114. The output unit 152 can be configured to pass the output to at least one external device or element, such as to a processor for further evaluation. As an example, the output unit 152 can be configured to identify or mark the most significant bit and / or the least significant bit so that, for example, a processor can correctly assign them. The MSB counter 144 and / or the LSB counter 148 can at least partially form the output unit 152. A processor that receives the first digital output count 118 from the MSB counter 144 and the second digital output 124 from the LSB counter 148 can be configured to use the first digital output count 118 from the MSB counter 144 as the most significant bit of the combined digital output count 114, and use the second digital output 124 from the LSB counter 148 as the least significant bit of the combined digital output count.

[0142] In the following, the operation of the readout circuit 110 will be referred to as Figure 1 First, the analog sensor charge 112 can reach the IAF circuit 116, specifically the integrator 128 of the IAF circuit 116. The integrator 128 can be ref With the comparator voltage V comp The analog sensor charge 112 is integrated to determine the integrated voltage V int . Integral voltage V int It can be a voltage output generated by the integrator 128 (specifically, by the operational amplifier 130). The reference voltage V refV may be a predefined voltage used as a reference, in particular a predefined voltage for integrator 128. The reference voltage may be applied in particular to operational amplifier 130, in particular to a first input of two typical inputs of operational amplifier 130. The analog sensor charge 112 may be fed in particular to a second input of operational amplifier 130. The output of operational amplifier 130 may be further fed to the second input via capacitor 132. Due to charge integration and reset, the integrated voltage V int It can be a time-varying triangular signal, such as Figure 1 As the analog sensor charge 112 is directed to the integrator 128, the generated integrated voltage V int can increase over time until the integrator 128 is reset by using the mixed signal circuit 134 of the integrator 128. Establishing and resetting the integrated voltage V int This process may be referred to as a completed integration cycle. As already mentioned, a completed integration cycle may refer to a countable saturation event 126 of the IAF circuit 116. However, if the integration voltage V int is not enough to trigger the saturation event 126 (for example, in the final incomplete integration cycle), the integrated voltage V int It can be maintained as the analog voltage margin 120 without being reset. Therefore, as an example and as Figure 1 As shown, in the final unfinished integration cycle, the remaining integrated voltage V at the output of the operational amplifier 130 is int It may be an analog voltage margin 120 .

[0143] The saturation event 126 may be an electrical component, specifically the integrator 128, more specifically the capacitor 132 of the integrator 128, that is saturated or full. The saturation event 126 may refer to an event of maximum charge on the capacitor 132. Saturation may depend on at least one geometric property of the capacitor 132, specifically the size. The smaller the capacitor 132, the faster saturation may occur, and the more saturation events 126 may occur over time. The capacitance of the capacitor 132 may be defined by the size of the capacitor 132, for example, by the ratio of the area of ​​the capacitor plates divided by the distance between the capacitor plates. The occurrence of the saturation event 126 may refer to a completed integration cycle of the integrator 128. As outlined above, in the event of a saturation event 126, the integrated voltage V int can reach a predefined quantization threshold V comp , and the comparator 136 of the IAF circuit 116 can trigger an event signal that can be counted. Specifically, the IAF circuit 116 can be configured to convert the analog sensor charge 112 into a first digital output count 118 by counting the integration cycles. Each completed integration cycle can increment the first digital output count 118.

[0144] The comparator voltage V comp to determine the saturation event 126. V int V may be fed to the first of two typical inputs of the comparator 136 of the IAF circuit 116. comp The second of the two typical inputs of the comparator 136 of the IAF circuit 116 may be fed to V comp V may be a predefined voltage used as a reference or threshold, specifically for comparator 136 of IAF circuit 116. Comparator 136 of IAF circuit 116 may be configured to set V int With V comp Specifically, the comparator 136 of the IAF circuit 116 can be configured to detect V int When is equal to V comp Specifically, for the corresponding selected V comp , which may indicate a saturation event 126. When a saturation event 126 is detected, the comparator 136 may trigger an event signal, which may be counted by the MSB counter 144. The comparator 136 may be configured to int Reach V comp The saturation event 126 is determined and the event signal is triggered. However, in the final integration period (also denoted as the final IAF period) of integrating the incoming analog sensor charge 112, there may be a margin because the integrated voltage does not reach the quantization threshold V comp (V int <V comp ), so the remainder cannot trigger the excitation of the event and is therefore not counted. The analog voltage remainder 120 can be the remainder, remainder, or remnant left after the IAF circuit 116 completes processing of the analog sensor charge 112 (specifically, at the end of the final completed integration period). The remainder can be one or more of characterized, described, or quantified by using at least one analog voltage. The analog voltage remainder 120 can refer to the remainder of the final uncompleted integration period. The IAF circuit 116 can be configured to digitize the analog sensor charge 112 to at least the analog voltage remainder 120.

[0145] The event signal excited by the comparator 136 of the IAF circuit 116 may be directed to the MSB counter 144. The MSB counter 144 may be configured to count the saturation events 126 and to increment the first digital output count 118 accordingly. The event signal excited by the comparator 136 of the IAF circuit 116 may be further directed to the switch controller 140 for resetting the integrator 128. The analog voltage margin 120 may be directed to the ADC 122 by using the shutter 146 and / or the switch 141 of the ADC 122. At the comparator 136 of the ADC 122, V int With the ramp voltage V ramp For comparison. ramp can be increased and / or decreased. When V ramp Reach V int , a signal may be passed on the LSB counter 148. The LSB counter 148 may then start counting using the clock 150 to generate the second digital output 124. Specifically, when the integration at the IAF circuit 116 is completed, an analog voltage margin V may be present at the output of the operational amplifier 130. int , so that V ref ≥V int >V comp The IAF circuit 116 can be int Exceed V comp The IAF reset is automatically triggered in the case of a reset. The margin voltage may be the remaining voltage without triggering the IAF reset. The ADC 122 may quantize the analog voltage margin 120 to generate a value representing a binary completion percentage of the output voltage of the operational amplifier 130. A binary value of 0 represents a voltage V int , binary value 2 N -1 means value V comp , where N is the number of bits of resolution of ADC 122. Between 0 and 2 N The ADC value between -1 can represent the analog voltage margin 120.

[0146] The first digital output count 118 and the second digital output 124 may then be passed to, for example, a processor for further evaluation of the analog sensor charge 112. The readout circuit 110 may be configured to read out small analog sensor charges 112, specifically, less than 1 nC, more specifically less than 1 pC of analog sensor charge 112. As explained, specifically, by using the ADC 122 to determine the least significant bit, small analog sensor charges 112 that do not trigger a saturation event 126 at the integrator 128 of the IAF circuit 116 may also be digitized.

[0147] Figure 2A and Figure 2BAnother exemplary embodiment of a schematic circuit diagram of the readout circuit 110 and a corresponding voltage signal state diagram are shown. Figure 2A The description of Figure 1 Description. Figure 2A An exemplary embodiment of the readout circuit 110 is shown, in which the IAF circuit 116 and the ADC 122 can share the comparator 136. Therefore, there may no longer be a clear separation between the IAF circuit 116 and the ADC 122 in the readout circuit 110, but both can be integrated into a common circuit. The analog sensor charge 112 can be directed to at least one transmission gate 154. The transmission gate 154 can be configured to direct the analog sensor charge 112 to at least one of the integrator 128 and the virtual integrator. Therefore, the analog sensor charge 112 can be directed from the transmission gate 154 to the integrator 128. The integrator 128 may include an operational amplifier 130 and a capacitor 132, and the operational amplifier may specifically be a capacitive feedback transimpedance amplifier 156. The integrator 128 may generate an integrated voltage V int . Integral voltage V int can be directed to a comparator 136, which can be a Schmitt trigger 138. The comparator 136 can int Exceed V comp The event signal is generated when the analog voltage residual 120 is digitized. The readout circuit 110 may include at least one event processor 158. The event processor 158 may be configured to identify the comparator event 126. Based on the comparator event 126, the event processor 158 may then initiate a reset of the integrator 128, such as by using the switch controller 140. Additionally or alternatively, the event processor 158 may initiate at least one of the counters 142. Additionally or alternatively, the event processor 158 may initiate digitization of the analog voltage residual 120, such as by configuring the comparator 136 for digitizing the analog voltage residual 120. The event processor 158 may set appropriate counter inputs based on the comparator output clocked via the system clock 150. The MSB counter 144 and / or the LSB counter 148 may be connected to at least one clock 150. The MSB counter 144 may be connected to an integration and excitation clock (IAF clock) 160. The LSB counter 148 may be connected to an analog-to-digital converter clock (ADC clock) 162.

[0148] The event processor 158 may be further connected to the switch controller 140. The switch controller 140 may be configured to control at least one switch 141 of the readout circuit 110. Specifically, the switch controller 140 may be configured to control the mixed signal circuit 134 of the readout circuit 110. The readout circuit 110 may include at least one mixed signal circuit 134 for resetting the integrator 128. The readout circuit 110 may include at least one switch 141 configured to reset at least one of the MSB counter 144 and the LSB counter 148, such as for initializing a new readout. The readout circuit 110 may include at least one switch 141 for selectively assigning at least one voltage to at least one component of the readout circuit 110. The readout circuit 110 may include at least one switch 141 for selectively assigning a comparator voltage V comp and / or ramp voltage V ramp Assigned to the comparator 136. The switch controller 140 may be configured to convert the comparator voltage V comp and / or ramp voltage V ramp Assigned to the comparator 136. Specifically, when the comparator 136 is used to determine the saturation event 126, the switch controller 140 can be configured to set the comparator voltage V comp Assigned to the comparator 136. Specifically, when the comparator 136 is used to digitize the analog voltage margin 120, the switch controller 140 can be configured to ramp Assigned to comparator 136. In general, other embodiments of readout circuit 110, such as other interconnections of components of readout circuit 110 or other components of readout circuit 110, are also possible.

[0149] Figure 2B Shows the use of Figure 2A The voltage diagram of the readout circuit 110 during readout is shown in FIG. The top row of the diagram indicates the current control state of the readout circuit 110. First, the readout circuit 110 can be initialized. The initialization state is Figure 2B In the initialization state 162, the MSB counter 144 and the LSB counter 148 may be reset (as shown in the second row of the figure), and the IAF clock 162 may be turned on. The reset of the MSB counter 144 and the LSB counter 148 is Figure 2B 166. Together with the IAF clock 162, a first slave integrator clock 168 and a second slave integrator clock 170 may be started. The initialization state 164 may be followed by an integration and firing state (IAF state) 172 and an end state 174. The IAF state 172 and the end state 174 may cover the integration time T of the readout circuit 110. int, i.e., the time during which the integration period or, respectively, the saturation event 126 may be counted, specifically by using the IAF clock 160. At the end state 174, the analog voltage margin 120 may remain at the integrator 128. Previously, the end of the IAF state 172 may be indicated by the first slave integrator clock 160. The end of the end state 174 may be indicated by the second slave integrator clock 170. After the end state 174, a stop state 176 may follow, in which the IAF clock 160 may be turned off. Up to and including the stop state 176, the comparator voltage V comp can be applied to the comparator 136. Therefore, the reference voltage V ref With V comp The analog sensor charge 112 is integrated between the two, thereby providing an integrated voltage V int Each integration cycle may generate a countable saturation event 126, and at the final uncompleted integration cycle, the analog voltage remainder 120 may remain at the integrator 128, as outlined above. The stop state 178 may be followed by an analog-to-digital converter state (ADC state) 178. At the ADC state 178, the ramp voltage V ramp can be applied to comparator 136. V ramp can increase over time until it equals the analog voltage margin 120, which can again trigger an event signal. However, the ADC counter 162 can now be used to digitize the signal. Finally, a readout state 180 can follow, which gives a determined digital output count 114, where V comp is applied to comparator 136 again, and V int is reset to V ref , as was the case initially.

[0150] Figure 3A and Figure 3B Experimental results of measurements on an exemplary embodiment of the readout circuit 110 are shown. The experiments have been conducted using a prototype system implementing the described readout circuit 110. The exemplary experiments are shown to illustrate the described readout circuit 110 and its advantages. The prototype system uses an IAF circuit 116 followed by an 8-bit counter-type ADC 122. Figure 3A1600 measurements M are shown with a sampling frequency of 1600 Hz, where each measurement M produces a measured ADC count N. The average ADC output μ is 9830 counts, which means an IAF count of 38, or an effective resolution of 5.25 bits. The experiment shows a count standard deviation σ of 9.9. The implied signal-to-noise ratio (SNR) based on the mean and standard deviation is 992 or effectively 9.96 bits. The effective gain of 4.7 bits of resolution is due to the measurement of the analog voltage margin 120 using an 8-bit counter-type ADC 122. The IAF circuit 116 integrates the charge over 500 μs using a capacitor 132 with 50 fF. Calculating the measurement value in terms of charge Q means that the charge amount for each sample reaches 0.9 pC, as shown in FIG. Figure 3B The discrete Fourier transform (DFT) analysis of the measured values ​​is shown in Figure 3C As shown. The root mean square (RMS) charge noise at 16Hz has been measured to be 58aC. At a frequency f of 160Hz, the RMS charge noise has been measured to be 43aC, and at 620Hz, the RMS charge noise is 40aC. These noise densities imply that the FFT 1-Hz bandwidth SNR is 15.392 / √Hz at 16Hz, 20.999 / √Hz at 160Hz, and 22.449 / √Hz at 620Hz. Therefore, the effective number of bits is 13.9, 14.4, 14.5 at 16Hz, 160Hz, and 620Hz, respectively.

[0151] Based on full bandwidth analysis of the ADC output, the readout circuit 110 is shown to improve the SNR from 5.25 bits of effective resolution to 9.96 bits. Analysis of the input analog sensor charge 112 shows a noise measurement floor of 40aC per square root hertz of bandwidth. rms to 58aC rms . A measurement charge of 0.9 pC is sufficient for infrared sensors such as PbS or InGaAs, which have a smaller size suitable for array or matrix type structures. FFT 1-Hz SNR measurement shows that the effective measurement bits are about 15. The readout circuit 110 is implemented with 64 independent ADC measurement channels for parallel readout of 64 sensor elements, and uses an average of 62 μW of power per channel. INL and DNL linearity of less than 1-LSB has been demonstrated for ADC resolutions from 8 to 24 bits. The resolution of the readout circuit 110 is significantly improved by using an 8-bit counter-type ADC 120 instead of just an IAF current counter approach. Compared to the classical approach using ROIC and ADC, the power requirement of the readout circuit 110 is 100 times lower than that of prior art analog front ends (AFEs), such as those from Texas Instruments or Analog Devices.

[0152] Figure 4An exemplary embodiment of a photodetector 182 is shown. The photodetector may be and / or may include a photoconductor or a photodiode. The photodetector 182 includes at least one sensor 184 configured to generate an analog sensor charge 112 based on the illumination of a photosensitive region 186 of the sensor 184. The photodetector 182 includes at least one readout circuit 110 described in any of the embodiments involving the readout circuit 110 disclosed in further detail above or below. The photodetector 182 may be a measuring device configured to detect optical radiation (such as for detecting illumination and / or light spots generated by at least one light beam 188). The photodetector 182 may include at least one substrate. A single photodetector 182 may be a substrate having at least one single photosensitive region 186 that generates a physical response to illumination of a given wavelength range. The photodetector 182 may include at least one housing 190 that surrounds at least one component of the photodetector 182, such as at least one sensor 184 or the readout circuit 110. The housing 190 may include at least one window 192 for transmitting optical radiation, such as the light beam 188 , specifically to the at least one sensor 184 .

[0153] The sensor 184 may be any element or device configured to detect at least one condition or to measure at least one measurement variable. The sensor 184 may be, for example, a light-sensitive sensor 184 used in the photodetector 182. Specifically, the sensor 184 may be capable of generating at least one signal (such as a measurement signal) that is a qualitative or quantitative indicator of a measurement variable and / or a measurement property (e.g., illumination of the sensor 184). The signal may be or include an electrical signal, such as an electric current or an electric charge. The photosensitive region 186 may be a region that is sensitive to illumination, such as an incident light beam 188. For example, the photosensitive region 186 may be a two-dimensional or three-dimensional region, which may preferably, but not necessarily, be continuous and / or may form a continuous region. The photosensitive region may include at least one photoconductive material selected from the group consisting of: lead sulfide (PbS); lead selenide (PbSe); mercury cadmium (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); extrinsic semiconductor, organic semiconductor. Specifically, the photodetector 182 may include a plurality of sensors 184, wherein the sensors 184 may be arranged in an array.

[0154] As described above, the readout circuit 110 may be specifically configured to read out a small analog sensor charge 112. This may be specifically related to the readout of the photodetector 182, or more specifically, to the readout of individual sensors 184 of the photodetector 182, which may only generate a small photocurrent. The readout circuit 110 may be configured to read out at least one sensor 182 configured to generate an analog sensor charge 112 based on the illumination of a photosensitive area 186 of the sensor 184. The readout circuit 110 may be configured to read out a plurality of sensors 184 configured to generate an analog sensor charge 112 based on the illumination of a photosensitive area 186 of the sensor 184. The sensors 184 may be arranged in an array. An array may be a spatial arrangement of elements such as the sensors 184. The array may be a one-dimensional array (e.g., a sequence of sensors along an axis) or a two-dimensional array (e.g., a sensor matrix). The array may also be a three-dimensional array. The array may be a regular array, for example, including a constant distance between elements. The array may be an irregular array, for example, including different distances between elements. The elements within the array may be of the same type or of different types. As an example, the array may include sensors 184 having light sensitivity to different wavelengths.

[0155] The readout circuit 110 may be a readout integrated circuit (ROIC). The readout circuit 110 may be an integrated circuit (IC), also referred to as a chip or microchip, or the readout circuit 110 may form at least a part of an IC. As known to the skilled person, an IC typically comprises at least one circuit assembled on a substrate, in particular a semiconductor substrate, more particularly a silicon (Si) substrate. The readout circuit 110 may be configured to accumulate at least one sensor current, in particular a photocurrent, wherein the accumulation of the sensor current may generate an analog sensor charge 112. The readout circuit 110 may be configured to accumulate the photocurrent for each sensor 184 of the photodetector 182 or for a sensor group 184 of the photodetector 182. The readout circuit 110 may be configured to store or at least buffer the analog sensor charge 112. The readout circuit 110 may be configured to transmit the analog sensor charge 112 to at least one output, such as an output of the IC, wherein the output may in particular be a digital output. The readout circuit 110 may be a digital readout integrated circuit (DROIC). The DROIC may use on-chip analog-to-digital conversion, specifically for digitizing at least one accumulated photocurrent. The readout circuit 110 may be a digital pixel readout integrated circuit (DPROIC). The DPROIC uses on-chip analog-to-digital conversion within each pixel or pixel group, specifically for digitizing at least one accumulated photocurrent, wherein a pixel may specifically refer to a sensor 184 of a photodetector 182.

[0156] Figure 5 A flow chart of an exemplary embodiment of a method for reading out analog sensor charge 112 is shown. The method comprises:

[0157] a) (indicated by reference numeral 194) providing at least one readout circuit 110 according to any of the embodiments involving the readout circuit 110 disclosed in further detail above or below;

[0158] b) (denoted by reference numeral 196) converting the analog sensor charge 112 into a first digital output count 118 and an analog voltage margin 120 by using the IAF circuit 116; and

[0159] c) (denoted by reference numeral 198 ) converting the analog voltage residual 120 into a second digital output 124 by using the ADC 122 .

[0160] The method may further comprise:

[0161] d) (denoted by reference numeral 200 ) determining a combined digital output count 118 by combining the first digital output count 118 and the second digital output 124 .

[0162] The method may include additional method steps not listed. Further, one or more of the method steps may be performed once or repeatedly. Further, two or more of the method steps may be performed simultaneously or in a time-overlapping manner. The readout may include reading out at least one sensor 184 of at least one photodetector 182 according to any of the embodiments involving the photodetector 182 disclosed in further detail above or below. The resolution of the readout may be controlled by changing the resolution of the second digital output 124 in step c). The gain of the readout, in particular the charge-to-voltage gain, may be controlled by changing the resolution of the second digital output 124 in step c).

[0163] List of Reference Numerals

[0164] 110 Readout circuit

[0165] 112 Analog sensor charge

[0166] 114 Digital output counts

[0167] 116 Integrate and Activate Circuit (IAF Circuit)

[0168] 118 First digital output count

[0169] 120 Analog voltage margin

[0170] 122 Analog-to-digital converter (ADC)

[0171] 124 Second digital output

[0172] 126 Events

[0173] 128 Integrator

[0174] 130 Operational Amplifier

[0175] 132 Capacitor

[0176] 134 Mixed Signal Circuits

[0177] 136 Comparator

[0178] 138 Schmitt trigger

[0179] 140 Switch Controller

[0180] 141 Switch

[0181] 142 Counter

[0182] 144 Most Significant Bit Counter (MSB Counter)

[0183] 146 Shutter

[0184] 148 Least Significant Bit Counter (LSB Counter)

[0185] 150 clock

[0186] 152 Output Units

[0187] 154 Transmission Gate

[0188] 156 Capacitive Feedback Transimpedance Amplifier (CTIA)

[0189] 158 Event Handler

[0190] 160 Integration and Firing Clock (IAF Clock)

[0191] 162 Analog-to-digital converter clock (ADC clock)

[0192] 164 Initialization state

[0193] 166 Reset

[0194] 168 First slave integrator clock

[0195] 170 Second slave integrator clock

[0196] 172 Integration and Excitation State (IAF State)

[0197] 174 End state

[0198] 176 Stop state

[0199] 178 Analog-to-digital converter status (ADC status)

[0200] 180 Reading status

[0201] 182 Photodetector

[0202] 184 Sensors

[0203] 186 Photosensitive Area

[0204] 188 Beam

[0205] 190 Housing

[0206] 192 Window

[0207] 194 Step a)

[0208] 196 Step b)

[0209] 198 Step c)

[0210] 200 Step d)

Claims

1. A readout circuit (110) configured to convert an analog sensor charge (112) into a digital output count (114), wherein: The readout circuit (110) includes at least one integrate and fire (IAF) circuit (116), wherein the IAF circuit (116) is configured to convert the analog sensor charge (112) into a first digital output count (118), wherein the readout circuit (110) is further configured to process an analog voltage remainder (120) after a final IAF cycle, wherein the readout circuit (110) includes at least one analog-to-digital converter (ADC) (122), wherein the ADC (122) is configured to convert the analog voltage remainder (120) into a second digital output (124).

2. The readout circuit (110) according to the preceding claim, wherein The readout circuit (110) is configured to read out a small analog sensor charge (112).

3. The readout circuit (110) according to any one of the preceding claims, wherein: The readout circuit (110) is configured to read out at least one sensor (184) configured to generate the analog sensor charge (112) in response to illumination of a photosensitive region (186) of the sensor (184).

4. The readout circuit (110) according to any one of the preceding claims, wherein The readout circuit (110) is configured to determine a combined digital output (114) by combining the first digital output count (118) and the second digital output (124), wherein the first digital output count (118) is proportional to a positive integer of an integration period, and wherein the second digital output (124) is proportional to a residual voltage of a final uncompleted integration period.

5. The readout circuit (110) according to any one of the preceding claims, wherein The IAF circuit (116) includes - at least one integrator (128), wherein the integrator (128) comprises at least one operational amplifier and at least one capacitor, wherein the input of the operational amplifier is maintained at a known voltage V ref , wherein the integrator (128) is configured to reset the output of the operational amplifier to V after each saturation event (126) ref , wherein the integrator (128) is configured to ref With the comparator voltage V comp The output of the operational amplifier is integrated to determine the integrated voltage V int ; - at least one comparator (136) configured to determine a saturation event (126); - at least one counter (142) configured to determine the first digital output count (118) by counting the saturation events (126); and - at least one mixed signal circuit (134) configured to, after each saturation event (126), int Reset to Vref.

6. Readout circuit (110) according to the preceding claim, wherein The simulated voltage margin is the remaining voltage after the final IAF cycle without triggering a saturation event (126).

7. The readout circuit (110) according to any one of the preceding claims, wherein The ADC (122) includes at least one ADC architecture selected from the group consisting of: counter-type ADC, single slope ADC, dual slope ADC, pipeline ADC, successive approximation register (SAR) ADC, Sigma-Delta ADC.

8. The readout circuit (110) according to any one of the preceding claims, wherein: The ADC (122) comprises a counter-type ADC, wherein the ADC and the IAF circuit share at least one component.

9. A photodetector (182), comprising: - at least one sensor (184) configured to generate an analog sensor charge (112) in response to illumination of a photosensitive area (186) of the sensor (184); and - at least one readout circuit (110) according to any of the preceding claims.

10. A photodetector (182) according to any one of the preceding claims relating to a photodetector (182), wherein: The photosensitive region (186) includes at least one photoconductive material selected from the group consisting of: lead sulfide (PbS); lead selenide (PbSe); mercury cadmium (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimonide (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); extrinsic semiconductors, organic semiconductors.

11. A method for reading out an analog sensor charge (112), the method comprising: a) providing at least one readout circuit (110) according to any of the preceding claims relating to a readout circuit (110); b) converting the analog sensor charge (112) into a first digital output count (118) and an analog voltage margin (120) by using the IAF circuit (116); and c) converting the analog voltage margin (120) into a second digital output (124) count by using the ADC (122).

12. The method according to the preceding claim, further comprising: d) determining a combined digital output count (114) by combining the first digital output count (118) and the second digital output (124).

13. A non-transitory computer readable medium comprising instructions which, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the preceding method-related claims.

14. Use of a readout circuit (110) according to any of the preceding claims relating to a readout circuit (110) for reading out at least one PbS sensor, at least one PbSe sensor or one or more sensors of at least one pixelated sensor array comprising a plurality of pixels, wherein Each of these pixels includes at least one PbS sensor or PbSe sensor.

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