Overlay precision measuring method and semiconductor device

Abstract

The invention provides an overlay precision measuring method and a semiconductor device, and belongs to the field of semiconductors. The overlay precision measuring method comprises the following steps: providing a semiconductor structure, wherein projections of a first overlay mark, a second overlay mark and a third overlay mark in the vertical direction have overlapped areas; the first overlay mark, the second overlay mark and the third overlay mark which form the overlapping area are used for detecting the overlay precision after the current metal layer and the previous metal layer as well as the through hole layer and the previous metal layer are etched. The first overlay mark, the second overlay mark and the third overlay mark are arranged, and the projection of the first overlay mark, the projection of the second overlay mark and the projection of the third overlay mark in the vertical direction have overlapped areas. Therefore, overlay precision measurement after etching among the three layers can be carried out at the same time. And the difficulty of overlay precision measurement after etching between the two metal layers and between the front metal layers by the through holes is reduced. Meanwhile, the measurement cost is reduced, and the measurement efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an overlay accuracy measurement method and a semiconductor device. Background Art

[0002] As the size of integrated circuit devices decreases, the design and process complexity continues to increase, and the requirements for semiconductor manufacturing process control are also increasing, so more precise measurements are needed.

[0003] Overlay is a very important control parameter of photolithography process. Especially for some key photolithography layers, there are very high requirements for the measurement and control of overlay accuracy. Figure 1 As shown, Figure 1 This is a schematic diagram of the main cross-sectional structure of the semiconductor structure after dual Damascene etching. As can be seen from the figure, through the structural relationship between the two metal layers and the through-hole layer, it can be seen that under normal circumstances, it is impossible to see the boundary of the first metal layer through the through-hole layer, so it is impossible to measure it using conventional SEM methods. Therefore, when optical measurement methods are usually used for overlay accuracy measurement after dual Damascene lithography, this measurement method is easily affected by the thickness of the previous film, the asymmetry of the measured graphic cross section, etc., resulting in inaccurate measurement results. The etching process also often introduces some additional overlay errors at the crystal edge due to plasma directionality issues. The above reasons will cause the overlay accuracy measurement results after lithography to have certain errors compared to the overlay accuracy in the final device. Therefore, in some key layers, electron beam measurement overlay accuracy (SEM OVL) needs to be corrected after etching.

[0004] In the back-end copper interconnection process of semiconductor structures, two metal layers are connected by metal layers filled with through holes. It is difficult to measure the overlay accuracy between two metal layers and between through holes and the previous metal layer after etching. It often requires the use of some special electron beam measurement tools (such as APM's ProV) to use high voltage to measure through the dielectric layer, which is costly and cannot be used on a large scale.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide an overlay accuracy measurement method and a semiconductor device to solve the problem that it is difficult to measure the overlay accuracy between two metal layers and between the front metal layer after etching of the through hole in the back-end copper interconnection process of the semiconductor structure.

[0007] In order to solve the above technical problems, the present invention provides a method for measuring overlay accuracy, comprising:

[0008] A semiconductor structure is provided, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer;

[0009] Forming a plurality of first set engraving marks on the current metal layer, forming a plurality of second set engraving marks on the through-hole layer, and forming a plurality of third set engraving marks on the front metal layer, wherein projections of the first set engraving marks, the second set engraving marks, and the third set engraving marks in a vertical direction have an overlapping area;

[0010] The first overlay mark, the second overlay mark and the third overlay mark forming the overlapping area are used to detect the overlay accuracy after etching of the current metal layer and the previous metal layer, and the through hole layer and the previous metal layer.

[0011] Preferably, the projection of the first overlay mark in the vertical direction is a first stripe pattern, the projection of the second overlay mark in the vertical direction is a second stripe pattern, and the projection of the third overlay mark in the vertical direction is a third stripe pattern.

[0012] Preferably, the first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on at least one side in the transverse direction.

[0013] Preferably, the first stripe pattern, the second stripe pattern and the third stripe pattern completely overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on both sides in the transverse direction.

[0014] Preferably, the central axes of the first strip-shaped pattern, the second strip-shaped pattern and the third strip-shaped pattern along the longitudinal direction coincide with each other.

[0015] Preferably, the first bar-shaped figure, the second bar-shaped figure and the third bar-shaped figure are all rectangular.

[0016] Preferably, the width of the first bar pattern along the transverse direction is greater than the width of the second bar pattern along the transverse direction, and the width of the second bar pattern along the transverse direction is greater than the width of the third bar pattern along the transverse direction.

[0017] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:

[0018] A semiconductor structure, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer;

[0019] A plurality of first set engraving marks are formed on the current metal layer, a plurality of second set engraving marks are formed on the through-hole layer, and a plurality of third set engraving marks are formed on the front metal layer, wherein projections of the first set engraving marks, the second set engraving marks, and the third set engraving marks in a vertical direction have an overlapping area;

[0020] The first overlay mark, the second overlay mark and the third overlay mark forming the overlapping area are used to detect the overlay accuracy after etching of the current metal layer and the previous metal layer, and the through hole layer and the previous metal layer.

[0021] Preferably, the projection of the first overlay mark in the vertical direction is a first stripe pattern, the projection of the second overlay mark in the vertical direction is a second stripe pattern, and the projection of the third overlay mark in the vertical direction is a third stripe pattern.

[0022] Preferably, the first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on at least one side in the transverse direction.

[0023] Compared with the prior art, the overlay accuracy measurement method of the present invention has the following advantages:

[0024] The overlay accuracy measurement method provided by the present invention is that the first overlay mark, the second overlay mark and the third overlay mark are set, and the projections of the first overlay mark, the second overlay mark and the third overlay mark in the vertical direction have overlapping areas. According to the actual process, the key dimensions of the current metal layer (Mx), the through hole layer (Vx) and the front metal layer (Mx-1) are reasonably designed, and the overlay accuracy measurement after etching between the two metal layers and between the through hole and the front metal layer can be performed using a conventional electron beam measurement tool. After etching, the boundaries of the current metal layer (Mx), the through hole layer (Vx) and the front metal layer (Mx-1) can be clearly captured using a conventional electron beam measurement tool, so that the overlay accuracy measurement after etching between the three layers can be performed simultaneously. The difficulty of overlay accuracy measurement after etching between the two metal layers and between the through hole and the front metal layer is reduced. At the same time, the measurement cost is also reduced and the measurement efficiency is improved.

[0025] In addition, the measurement pattern has another advantage, which is that different positions of the same pattern can be used to simultaneously measure the overlay accuracy between two metal layers and between the through hole and the previous metal layer after etching, which further improves the efficiency of measurement and reduces the difficulty of measurement.

[0026] The semiconductor device provided by the present invention and the overlay accuracy measurement method provided by the present invention belong to the same inventive concept. Therefore, the semiconductor device provided by the present invention has at least all the advantages of the overlay accuracy measurement method provided by the present invention, and is convenient for measuring the overlay accuracy after etching between two metal layers and between the through hole and the previous metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a main cross-sectional structure of a semiconductor structure after dual damascene etching in one embodiment of the present invention;

[0028] Figure 2 is a flow chart of a method for measuring overlay accuracy in one embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of the structure of a first set of engraved marks, a second set of engraved marks and a third set of engraved marks in one embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of a laminated mark formed by a first set of engraved marks, a second set of engraved marks and a third set of engraved marks in one embodiment of the present invention;

[0031] Figure 5 is an electron scanning image of a semiconductor structure passing through in one embodiment of the present invention;

[0032] In the figure,

[0033] 100-laminated mark; 10-first set of engraved marks;

[0034] 20 - second set of engraved marks; 30 - third set of engraved marks. DETAILED DESCRIPTION

[0035] In order to make the purpose, advantages and features of the present invention clearer, the overlay accuracy measurement method and semiconductor device proposed by the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0037] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0038] Ginseng Figure 3 As shown, it should be noted that the term "longitudinal direction" herein refers to the direction of arrow b, that is, the direction of the length of the first set of engraved marks 10, the second set of engraved marks 20 and the third set of engraved marks 30. The term "lateral direction" refers to the direction of arrow c, that is, the direction of the width of the first set of engraved marks 10, the second set of engraved marks 20 and the third set of engraved marks 30. The term "vertical direction" refers to the direction perpendicular to the plane formed by arrows b and c, that is, the direction perpendicular to the etching plane of the semiconductor structure.

[0039] In the prior art, it is difficult to measure the overlay accuracy between two metal layers and between a through hole and a front metal layer in the back-end copper interconnection process of a semiconductor structure. The existing measurement method is costly and cannot be used on a large scale, and the measurement efficiency is low.

[0040] The core idea of ​​the present invention is to provide an overlay accuracy measurement method, which can improve the overlay accuracy measurement accuracy between two metal layers and between a through hole and a front metal layer after etching, and the measurement method is simple.

[0041] In order to realize the above idea, the present invention provides a method for measuring overlay accuracy. Figures 1 to 5 A specific implementation of the disclosed overlay accuracy measurement method includes the following steps S1 to S3.

[0042] Step S1: providing a semiconductor structure, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer.

[0043] Specifically, refer to Figure 1 and Figure 2 As shown, a semiconductor structure is provided, wherein the semiconductor structure is formed with a current metal layer (abbreviated as "Mx"), a via layer (abbreviated as "Vx"), and a front metal layer (abbreviated as "Mx-1"). The semiconductor structure is subjected to a back-end copper interconnection process. The metal material of the current metal layer and the front metal layer can be copper metal. The metal filled in the through hole in the via layer can be tungsten metal. The current metal layer and the front metal layer are interconnected through the metal tungsten deposited on the via layer.

[0044] Step S2: forming a plurality of first set engraving marks 10 on the current metal layer, forming a plurality of second set engraving marks 20 on the through hole layer, and forming a plurality of third set engraving marks 30 on the front metal layer, wherein the projections of the first set engraving marks 10, the second set engraving marks 20 and the third set engraving marks 30 in the vertical direction have an overlapping area a.

[0045] Specifically, refer to Figures 2 to 5 As shown, a plurality of first overlay marks 10 are formed on the current metal layer (Mx). That is, one or more first overlay marks 10 are formed on the current metal layer. In order to improve the accuracy of overlay precision measurement, it is preferred that a plurality of first overlay marks 10 are formed. A plurality of second overlay marks 20 are formed on the through-hole layer. A plurality of third overlay marks 30 are formed on the front metal layer. Similarly, a plurality of second overlay marks 20 and a plurality of third overlay marks 30 are preferably provided. Further preferably, the number of the first overlay mark 10, the second overlay mark 20 and the third overlay mark 30 is equal.

[0046] The projections of the first set of engraved marks 10, the second set of engraved marks 20 and the third set of engraved marks 30 in the vertical direction have an overlapping area a. That is, the first set of engraved marks 10, the second set of engraved marks 20 and the third set of engraved marks 30 form an overlapping area a on the etching plane. That is, a plurality of first set of engraved marks 10, the second set of engraved marks 20 and the third set of engraved marks 30 form a plurality of overlapping areas a on the etching plane, constituting an overlay mark 100.

[0047] The projection of the first set of engraved marks 10 in the vertical direction is a first stripe pattern, the projection of the second set of engraved marks 20 in the vertical direction is a second stripe pattern, and the projection of the third set of engraved marks 30 in the vertical direction is a third stripe pattern. The first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area a, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area a do not overlap on at least one side in the transverse direction. That is, the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on one side in the transverse direction, or do not overlap on both sides. Preferably, the central axis of the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area overlap in the longitudinal direction. And the first stripe pattern, the second stripe pattern and the third stripe pattern completely overlap in the longitudinal direction, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on both sides in the transverse direction. That is, the following is formed. Figure 4 A laminated marker 100 is shown.

[0048] Furthermore, the first stripe pattern, the second stripe pattern and the third stripe pattern are all rectangular. The width of the first stripe pattern along the transverse direction is greater than the width of the second stripe pattern along the transverse direction, and the width of the second stripe pattern along the transverse direction is greater than the width of the third stripe pattern along the transverse direction.

[0049] Step S3: forming the first overlay mark 10, the second overlay mark 20 and the third overlay mark 30 in the overlapping area for detecting the overlay accuracy between the current metal layer and the previous metal layer, and between the through hole layer and the previous metal layer after etching.

[0050] Specifically, refer to Figures 2 to 5 As shown, the semiconductor structure after etching of the copper interconnection process is scanned by an electronic scanning environment, and the following is obtained: Figure 5 The structure shown. Figure 5 It can be seen from the scanned image shown that the overlay accuracy measurement method disclosed in this embodiment reasonably designs the key dimensions of the current metal layer (Mx), the through-hole layer (Vx) and the front metal layer (Mx-1) according to the actual process, and can use conventional electron beam measurement tools (such as: CD SEM) to perform overlay accuracy measurement after etching between two metal layers, and between the through hole and the front metal layer. After etching, the use of CD SEM can clearly capture the boundaries of the current metal layer (Mx), the through-hole layer (Vx) and the front metal layer (Mx-1), so as to perform overlay accuracy measurement after etching between the three layers at the same time. The difficulty of overlay accuracy measurement after etching between two metal layers, and between the through hole and the front metal layer is reduced. At the same time, the measurement cost is also reduced and the measurement efficiency is improved.

[0051] In addition, the measurement pattern has another advantage, which is that different positions of the same pattern can be used to simultaneously measure the overlay accuracy between two metal layers and between the through hole and the previous metal layer after etching, which further improves the efficiency of measurement and reduces the difficulty of measurement.

[0052] To realize the above-mentioned concept, the embodiment also discloses a semiconductor device, including: a semiconductor structure, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer. A plurality of first overlay marks 10 are formed on the current metal layer, a plurality of second overlay marks 20 are formed on the through-hole layer, and a plurality of third overlay marks 30 are formed on the front metal layer, wherein the projections of the first overlay marks 10, the second overlay marks 20 and the third overlay marks 30 in the vertical direction have an overlapping area a. The first overlay marks 10, the second overlay marks 20 and the third overlay marks 30 forming the overlapping area a are used to detect the overlay accuracy of the current metal layer and the front metal layer, and the through-hole layer and the front metal layer after etching.

[0053] The projection of the first engraved mark 10 in the vertical direction is a first stripe pattern, the projection of the second engraved mark 20 in the vertical direction is a second stripe pattern, and the projection of the third engraved mark 30 in the vertical direction is a third stripe pattern.

[0054] The first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area, wherein the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap in at least one side in the transverse direction.

[0055] In summary, the above embodiments have detailed the overlay accuracy measurement method and different configurations of semiconductor devices. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above implementations. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for measuring overlay accuracy, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer; Forming a plurality of first set engraving marks on the current metal layer, forming a plurality of second set engraving marks on the through-hole layer, and forming a plurality of third set engraving marks on the front metal layer, wherein projections of the first set engraving marks, the second set engraving marks, and the third set engraving marks in a vertical direction have an overlapping area; The first overlay mark, the second overlay mark and the third overlay mark forming the overlapping area are used to detect the overlay accuracy between the current metal layer and the previous metal layer, and between the through hole layer and the previous metal layer after etching.

2. The overlay accuracy measurement method according to claim 1, characterized in that: The projection of the first overlay mark in the vertical direction is a first stripe pattern, the projection of the second overlay mark in the vertical direction is a second stripe pattern, and the projection of the third overlay mark in the vertical direction is a third stripe pattern.

3. The overlay accuracy measurement method according to claim 2, characterized in that: The first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap in at least one side in the transverse direction.

4. The overlay accuracy measurement method according to claim 2, characterized in that: The first stripe pattern, the second stripe pattern and the third stripe pattern completely overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap on both sides in the transverse direction.

5. The overlay accuracy measurement method according to claim 2, characterized in that: The central axes of the first stripe pattern, the second stripe pattern and the third stripe pattern coincide with each other along the longitudinal direction.

6. The overlay accuracy measurement method according to any one of claims 2 to 5, characterized in that: The first bar-shaped figure, the second bar-shaped figure and the third bar-shaped figure are all rectangular.

7. The overlay accuracy measurement method according to claim 6, characterized in that: The width of the first stripe pattern along the transverse direction is greater than the width of the second stripe pattern along the transverse direction, and the width of the second stripe pattern along the transverse direction is greater than the width of the third stripe pattern along the transverse direction.

8. A semiconductor device, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is formed with a current metal layer, a through-hole layer and a front metal layer, wherein the current metal layer and the front metal layer are interconnected by metal deposited through the through-hole layer; A plurality of first set engraving marks are formed on the current metal layer, a plurality of second set engraving marks are formed on the through-hole layer, and a plurality of third set engraving marks are formed on the front metal layer, wherein projections of the first set engraving marks, the second set engraving marks, and the third set engraving marks in a vertical direction have an overlapping area; The first overlay mark, the second overlay mark and the third overlay mark forming the overlapping area are used to detect the overlay accuracy between the current metal layer and the previous metal layer, and between the through hole layer and the previous metal layer after etching.

9. The semiconductor device according to claim 8, characterized in that The projection of the first overlay mark in the vertical direction is a first stripe pattern, the projection of the second overlay mark in the vertical direction is a second stripe pattern, and the projection of the third overlay mark in the vertical direction is a third stripe pattern.

10. The semiconductor device according to claim 9, characterized in that The first stripe pattern, the second stripe pattern and the third stripe pattern at least partially overlap in the longitudinal direction to form an overlapping area, and the first stripe pattern, the second stripe pattern and the third stripe pattern in the overlapping area do not overlap in at least one side in the transverse direction.

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