Wear leveling method and memory storage device

Abstract

The invention provides a wear leveling method and a memory storage device. The wear leveling method is used for a rewritable nonvolatile memory module. And the rewritable nonvolatile memory module comprises a plurality of entity erasing units. The wear leveling method comprises the following steps: judging whether each entity erasing unit meets a preset condition or not on the basis of erasing times and written-in time of each entity erasing unit; if the current entity erasing unit meeting the preset condition exists in the multiple entity erasing units, whether the current entity erasing unit is fully written or not is judged; and if the current entity erasing unit is not fully written, executing a first wear leveling operation on the current entity erasing unit, and if the current entity erasing unit is fully written, executing a second wear leveling operation on the current entity erasing unit.

Description

Technical Field

[0001] The present invention relates to the technical field of storage management, and in particular to a wear leveling method and a memory storage device. Background Art

[0002] Smart phones, tablet computers and personal computers have grown rapidly in the past few years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable multimedia devices listed above because they are non-volatile, power-saving, small in size, and have no mechanical structure.

[0003] The conventional wear leveling method is to move data to physical erase units with a higher number of erases, so that physical erase units with a lower number of erases can be put into use, so as to average the number of times the physical erase units in the rewritable non-volatile memory module are used. In order to respond to the actual situation in use, the wear leveling strategy is finely adjusted to more effectively extend the service life of the memory storage device. How to improve the effect of wear leveling is a technical problem that technicians in this field are eager to solve. Summary of the invention

[0004] An exemplary embodiment of the present invention provides a wear leveling method and a memory storage device, which can improve the service life and data stability of the memory storage device.

[0005] An exemplary embodiment of the present invention provides a wear leveling method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, and the wear leveling method includes: judging whether each of the plurality of physical erasing units meets a preset condition based on the number of erasure times and the writing time of each of the plurality of physical erasing units; if there is a current physical erasing unit that meets the preset condition among the plurality of physical erasing units, judging whether the current physical erasing unit is full; if the current physical erasing unit is not full, performing a first wear leveling operation on the current physical erasing unit; and if the current physical erasing unit is full, performing a second wear leveling operation on the current physical erasing unit.

[0006] In an exemplary embodiment of the present invention, if the current physical erasure unit is not fully written, the wear leveling method further includes: determining whether the current physical erasure unit stores valid data; if the current physical erasure unit stores valid data, performing a first wear leveling operation on the current physical erasure unit; if the current physical erasure unit does not store valid data, associating the current physical erasure unit with an idle pool.

[0007] In an exemplary embodiment of the present invention, the step of determining whether each of the plurality of physical erasing units satisfies the preset condition based on the number of erasures and the written time of each of the plurality of physical erasing units includes: determining whether the difference between the number of erasures of each of the plurality of physical erasing units and the average number of erasures is greater than a preset threshold; if there is at least one physical erasing unit among the plurality of physical erasing units whose difference is greater than the preset threshold, determining whether the written time of each of the at least one physical erasing unit is greater than a preset time threshold; and if there is the current physical erasing unit among the at least one physical erasing unit whose written time is greater than the preset time threshold, determining that the current physical erasing unit satisfies the preset condition.

[0008] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: selecting a physical erase unit with the highest erase count from an idle pool as a first target physical erase unit; and moving all data of the current physical erase unit to the first target physical erase unit.

[0009] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: determining whether there is an unfilled first target physical erase unit; and if there is no unfilled first target physical erase unit, selecting a physical erase unit with the highest number of erase times from an idle pool as the first target physical erase unit, and moving all data in the current physical erase unit to the first target physical erase unit.

[0010] In an exemplary embodiment of the present invention, the step of performing the first wear leveling operation includes: if there is an unfilled first target physical erase unit, determining whether the remaining capacity of the unfilled first target physical erase unit is sufficient to store all the data in the current physical erase unit; if so, moving all the data in the current physical erase unit to the unfilled first target physical erase unit; and if not, selecting the physical erase unit with the highest number of erase times from the idle pool as the first target physical erase unit, and moving all the data in the current physical erase unit to the first target physical erase unit.

[0011] In an exemplary embodiment of the present invention, the step of performing the second wear leveling operation includes: determining whether there is an unfilled second target physical erase unit; and if there is no unfilled second target physical erase unit, selecting a physical erase unit with the highest number of erase times from an idle pool as the second target physical erase unit, and moving valid data in the current physical erase unit to the second target physical erase unit.

[0012] In an exemplary embodiment of the present invention, the step of performing the second wear leveling operation includes: if there is a second target physical erase unit that is not full, determining whether the remaining capacity of the second target physical erase unit that is not full is sufficient to store the valid data in the current physical erase unit; if so, moving the valid data in the current physical erase unit to the second target physical erase unit that is not full; and if not, selecting the physical erase unit with the highest number of erase times from the idle pool as the second target physical erase unit, and moving the valid data in the current physical erase unit to the second target physical erase unit that is not full and the second target physical erase unit in sequence.

[0013] In an exemplary embodiment of the present invention, the wear leveling method further includes: obtaining a plurality of erasure times of the plurality of physical erasure units; and calculating the average erasure time according to the plurality of erasure times.

[0014] The exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical erasing units. The memory control circuit unit is used to determine whether each of the plurality of physical erasing units meets a preset condition based on the number of erasures and the written time of each of the plurality of physical erasing units. If there is a current physical erasing unit that meets the preset condition among the plurality of physical erasing units, the memory control circuit unit is also used to determine whether the current physical erasing unit is full. If the current physical erasing unit is not full, the memory control circuit unit is also used to perform a first wear leveling operation on the current physical erasing unit. If the current physical erasing unit is full, the memory control circuit unit is also used to perform a second wear leveling operation on the current physical erasing unit.

[0015] In an exemplary embodiment of the present invention, if the current physical erasing unit is not fully written, the memory control circuit unit is also used to determine whether the current physical erasing unit stores valid data; if the current physical erasing unit stores valid data, a first wear leveling operation is performed on the current physical erasing unit; if the current physical erasing unit does not store valid data, the current physical erasing unit is associated with an idle pool.

[0016] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine whether the difference between the number of erasures of each of the plurality of physical erasure units and the average number of erasures is greater than a preset threshold. If there is at least one physical erasure unit among the plurality of physical erasure units whose difference is greater than the preset threshold, the memory control circuit unit is further used to determine whether the written time of each of the at least one physical erasure unit is greater than a preset time threshold. If there is the current physical erasure unit among the at least one physical erasure unit whose written time is greater than the preset time threshold, the memory control circuit unit is further used to determine whether the current physical erasure unit meets the preset condition.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select a physical erase unit with the highest erase count from the idle pool as a first target physical erase unit, and move all data of the current physical erase unit to the first target physical erase unit.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine whether there is an unfilled first target physical erase unit. If there is no unfilled first target physical erase unit, the memory control circuit unit is further used to select a physical erase unit with the highest number of erase times from the idle pool as the first target physical erase unit, and move all data in the current physical erase unit to the first target physical erase unit.

[0019] In an exemplary embodiment of the present invention, if there is an unfilled first target physical erase unit, the memory control circuit unit is further used to determine whether the remaining capacity of the unfilled first target physical erase unit is sufficient to store all the data in the current physical erase unit. If so, the memory control circuit unit is further used to move all the data in the current physical erase unit to the unfilled first target physical erase unit. If not, the memory control circuit unit is further used to select the physical erase unit with the highest number of erase times from the idle pool as the first target physical erase unit, and move all the data in the current physical erase unit to the first target physical erase unit.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine whether there is an unfilled second target physical erase unit. If there is no unfilled second target physical erase unit, the memory control circuit unit is further used to select a physical erase unit with the highest number of erase times from the idle pool as the second target physical erase unit, and move the valid data in the current physical erase unit to the second target physical erase unit.

[0021] In an exemplary embodiment of the present invention, if there is a second target physical erase unit that is not full, the memory control circuit unit is further used to determine whether the remaining capacity of the second target physical erase unit that is not full is sufficient to store the valid data in the current physical erase unit. If so, the memory control circuit unit is further used to move the valid data in the current physical erase unit to the second target physical erase unit that is not full. If not, the memory control circuit unit is further used to select the physical erase unit with the highest number of erase times from the idle pool as the second target physical erase unit, and move the valid data in the current physical erase unit to the second target physical erase unit that is not full and the second target physical erase unit in sequence.

[0022] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to obtain a plurality of erasure times of the plurality of physical erasure units, and calculate the average erasure time according to the plurality of erasure times.

[0023] Based on the above, the present invention provides a wear leveling method and a memory storage device, which can perform wear leveling operations on closed physical erase units and open physical erase units to meet user usage habits. In addition, in the wear leveling operation on the open physical erase unit, by moving all the data of the open physical erase unit to the target physical erase unit, the service life of the memory storage device can be improved while the data stability of the memory storage device is improved. In addition, by using the target physical erase unit that is not fully written, the waste of storage space can be effectively avoided.

[0024] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a system and a storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0032] Figure 8 is a flow chart of a wear leveling method according to an exemplary embodiment of the present invention;

[0033] Fig. 9 is a flowchart of performing a first wear leveling operation according to an exemplary embodiment of the present invention;

[0034] Fig.10 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0035] Fig.11 is a flowchart of performing a first wear leveling operation according to an exemplary embodiment of the present invention;

[0036] Fig.12 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0037] Fig.13 is a flowchart of performing a second wear leveling operation according to an exemplary embodiment of the present invention;

[0038] Fig.14 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0039] Fig.15 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0040] Fig.16 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention;

[0041] Fig.17 is a flow chart of a wear leveling method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0043] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0045] The host system 11 may be connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0046] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 in a wired or wireless manner.

[0047] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0048] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 The storage device 30 and the system 31.

[0049] Figure 3 is a schematic diagram of a system and a storage device according to an exemplary embodiment of the present invention. Figure 3 , the storage device 30 can be used in conjunction with the system 31 to store data. For example, the system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0050] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0051] The connection interface unit 41 is used to connect to the host system 11 . The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41 . For example, the connection interface unit 41 may be compatible with the Peripheral Component Interconnect Express (PCI Express) standard, the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards.

[0052] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to control the rewritable non-volatile memory module 43. For example, the memory control circuit unit 42 can instruct the rewritable non-volatile memory module 43 to perform operations such as writing, reading, and erasing data according to the instructions of the host system 11. For example, the memory control circuit unit 42 may include a flash memory controller.

[0053] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0054] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0055] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0056] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0057] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. For example, the memory management circuit 51 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices.

[0058] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. For example, the host interface 52 can be compatible with the PCI Express standard, the SATA standard, the PATA standard, the IEEE1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0059] The memory interface 53 is connected to the memory management circuit 51. The memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. For example, the memory management circuit 51 can issue an operation instruction to the rewritable non-volatile memory module 43 through the memory interface 53 to instruct the rewritable non-volatile memory module 43 to perform various operations such as reading, writing or erasing data.

[0060] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0061] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. For example, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0062] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0063] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 601 ( 0 ) to 601 (C) in the rewritable non-volatile memory module 43 into a storage pool 61 and a spare pool 62 .

[0064] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. A physical programming unit is a basic unit for performing a programming operation to write data. For example, a physical programming unit may include one or more physical pages or physical sectors. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a virtual block may include one or more physical erase units. A physical erase unit is a basic unit for performing an erase operation to erase data. For example, a physical erase unit may include one or more physical blocks (blcok).

[0065] In an exemplary embodiment, the physical units 601(0)-601(B) in the storage pool 61 are used to store user data (e.g., from Figure 1 user data of the host system 11). For example, the physical units 601(0)-601(B) in the storage pool 61 can store valid data and invalid data. In addition, the memory management circuit 51 can logically group the physical units 601(0)-601(A) in the storage pool 61 into an open pool 611, and logically group the physical units 601(A+1)-601(B) in the storage pool 61 into a closed pool 612. For example, if a physical unit has stored data and is not full, the physical unit can be associated (or added) to the open pool 611. For example, if a physical unit has stored data and is full, the physical unit can be associated (or added) to the closed pool 612. In an exemplary embodiment, the physical units 601(0)-601(A) in the open pool 611 are also called open physical units. The physical units 601(A+1)-601(B) in the closed pool 612 are also referred to as closed physical units. For example, the open pool 611 may include a plurality of open physical erase units, each of which may include one or more open physical blocks. For example, the closed pool 612 may include a plurality of closed physical erase units, each of which may include one or more closed physical blocks.

[0066] In an exemplary embodiment, the physical units 601(B+1)-601(C) in the idle pool 62 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 62. In addition, the physical units in the idle pool 62 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle pool 62 to store the new data.

[0067] In an exemplary embodiment, the memory management circuit 51 may configure the logical units 602(0)-602(D) to map the physical units 601(0)-601(B) in the storage area 61. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0068] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0069] Figure 7 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention. Figure 7 In an exemplary embodiment, the memory management circuit 51 may logically group the physical erasing units in the rewritable non-volatile memory module 43 into an idle pool 72 and an open pool 711 and a closed pool 712 of the storage pool 71 .

[0070] First, in the first stage, the idle pool 72 includes but is not limited to physical erase units B7-B9, the open pool 711 includes but is not limited to physical erase units B1-B3, and the closed pool 712 includes but is not limited to physical erase units B4-B6. Next, in the second stage, the physical erase units B2 and B3 that originally belonged to the open pool 711 in the first stage can be filled and associated with the closed pool 722, while the physical erase unit B1 is not accessed by the host system 11 and is still associated with the open pool 711 in the second stage. In addition, the physical erase units B7 and B8 that originally belonged to the idle pool 72 in the first stage can be associated with the open pool 711 in the second stage. Finally, after a long period of time, the third stage is entered.

[0071] like Figure 7 As shown, since the user no longer uses the physical erase unit B1 and the physical erase unit B1 associated with the open pool 711 does not participate in the wear leveling operation, during the process from the second stage to the third stage, the physical erase unit B1 is not filled and continues to belong to the open pool 711, while the erasure times of other physical erase units are continuously increased. Finally, in the third stage, the erasure times of the physical erase unit B1 will be much lower than the erasure times of other physical erase units, thereby causing adverse effects on the service life of the memory storage device 10.

[0072] The present invention provides a wear leveling method, which can perform wear leveling operations on a closed physical erase unit and an open physical erase unit to respond to user usage habits, thereby effectively extending the service life of a memory storage device and improving data stability.

[0073] Figure 8 is a flow chart of a wear leveling method according to an exemplary embodiment of the present invention. Figure 8 In an exemplary embodiment, the memory management circuit 51 may determine whether each physical erasable unit of the rewritable non-volatile memory module 43 satisfies a preset condition for triggering a wear leveling operation based on the erasing times and writing times of the physical erasable units.

[0074] In step S801, the memory management circuit 51 may obtain a plurality of erasure times of a plurality of physical erasure units, and calculate an average erasure time according to the plurality of erasure times. In an exemplary embodiment, the memory management circuit 51 may periodically obtain a plurality of erasure times of a plurality of physical erasure units of the rewritable non-volatile memory module 43, and calculate an average erasure time according to the plurality of erasure times. In an exemplary embodiment, the memory management circuit 51 may, for example, obtain a plurality of erasure times of a plurality of physical erasure units of the rewritable non-volatile memory module 43 according to an instruction from the host system 11, and calculate an average erasure time according to the plurality of erasure times.

[0075] In step S802, the memory management circuit 51 can determine whether the difference between the number of erase times and the average number of erase times of each physical erase unit in the rewritable non-volatile memory module 43 is greater than a preset threshold. Specifically, if the difference between the number of erase times and the average number of erase times of a physical erase unit is larger, it means that the number of erase times of this physical erase unit is much higher (or much lower) than other physical erase units, and this physical erase unit needs to be put into wear leveling operation to avoid affecting the service life of the memory storage device 10. The value of the preset threshold can be designed according to actual needs, and the present invention does not limit it. If there is at least one physical erase unit whose difference between the number of erase times and the average number of erase times is greater than the preset threshold, then enter step S803; otherwise, end Figure 8 Wear leveling method.

[0076] In step S803, the memory management circuit 51 may further determine whether the writing time of at least one of the above-mentioned physical erasing units is greater than a preset time threshold. Specifically, when data is written to a physical erasing unit, the memory management circuit 51 may record a timestamp in the physical erasing unit, wherein the timestamp is used to represent the time point when the data is written to the physical erasing unit. The memory management circuit 51 may, for example, calculate the writing time of the physical erasing unit through the timestamp. For example, the memory management circuit 51 may calculate the time length between the time point when the data is written to the physical erasing unit and the current time point through the timestamp (that is, the writing time). Accordingly, the memory management circuit 51 may determine whether the physical erasing unit meets the preset condition by determining whether the writing time of a physical erasing unit is greater than a preset time threshold. The value of the preset time threshold may be designed according to actual needs, and the present invention does not limit it.

[0077] In an exemplary embodiment, the memory management circuit 51 may, for example, randomly determine whether the written time of the at least one physical erasing unit is greater than a preset time threshold. In an exemplary embodiment, the memory management circuit 51 may, for example, determine whether the written time of the at least one physical erasing unit is greater than a preset time threshold in descending order according to the difference between the number of erase times of the at least one physical erasing unit and the average number of erase times.

[0078] In an exemplary embodiment, the memory management circuit 51 may, for example, determine whether the written time of at least one physical erase unit (for example, 5 physical erase units) is greater than a preset time threshold according to the number of erases of the at least one physical erase unit (for example, 5 physical erase units) in descending order. Specifically, the memory management circuit 51 may obtain the timestamps in the above 5 physical erase units in descending order according to the number of erases, and determine whether the written time represented by the timestamps is greater than the preset time threshold. In detail, first, the memory management circuit 51 may obtain the timestamp of the physical erase unit with the highest number of erases among the above 5 physical erase units, and calculate the written time of the physical erase unit with the highest number of erases based on the timestamps, and determine whether the written time is greater than the preset time threshold. Assuming that the written time of the physical erase unit with the highest number of erases is not greater than the preset time threshold, the physical erase unit with the highest number of erases does not meet the preset condition and does not need to be put into the wear leveling operation temporarily, and enters step S804.

[0079] In step S804, the memory management circuit 51 may determine whether the physical erasing unit with the highest number of erasing times is the last one of the above five physical erasing units. Since the physical erasing unit with the highest number of erasing times is not the last one of the above five physical erasing units (that is, there are still four physical erasing units among the above five physical erasing units that have not been executed in step S803), the process may return to step S803, and the memory management circuit 51 may continue to determine whether the written time of the physical erasing unit with the highest number of erasing times among the above four physical erasing units is greater than the preset time threshold. If the written time of the physical erasing unit with the highest number of erasing times among the above four physical erasing units is not greater than the preset time threshold, the process proceeds to step S804, and the above implementation details are repeated until the above four physical erasing units have all been executed in step S803, or the written time of one of the above four physical erasing units is greater than the preset time threshold, and the process proceeds to step S805.

[0080] On the other hand, if the written time of the physical erasing unit with the highest number of erasing times among the above four physical erasing units is greater than the preset time threshold, the physical erasing unit with the highest number of erasing times among the above four physical erasing units meets the preset condition, and the process proceeds to step S805. In step S805, the memory management circuit 51 can determine whether the physical erasing unit with the highest number of erasing times among the above four physical erasing units (that is, the current physical erasing unit that meets the preset condition) is fully written. In other words, the memory management circuit 51 can determine whether the current physical erasing unit is an open physical erasing unit or a closed physical erasing unit.

[0081] If the current physical erase unit is not fully written (that is, the current physical erase unit is an open physical erase unit), the process proceeds to step S806. In step S806, the memory management circuit 51 may determine whether the current physical erase unit stores valid data. If the current physical erase unit does not store valid data, the process proceeds to step S807. In step S807, the memory management circuit 51 may associate the current physical erase unit with the idle pool 72 so that the current physical erase unit can be put into use in subsequent write operations to store user data written by the host system 11. On the contrary, if the current physical erase unit stores valid data, the process proceeds to step S808. In step S808, the memory management circuit 51 may perform a first wear leveling operation on the current physical erase unit.

[0082] In an exemplary embodiment, the implementation details of the memory management circuit 51 performing the first wear leveling operation may be as follows. Fig. 9 and Fig.10 As shown, Fig. 9 is a flowchart of performing a first wear leveling operation according to an exemplary embodiment of the present invention;

[0083] Fig.10 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention. Fig. 9 and Fig.10 In step S901, the memory management circuit 51 may select the physical erase unit with the highest number of erase times from the idle pool 72 as the first target physical erase unit. That is, the memory management circuit 51 may select the physical erase unit B3 with the highest number of erase times (i.e., 515 times) from the idle pool 72 as the first target physical erase unit. Next, in step S902, the memory management circuit 51 may select the current physical erase unit (i.e., Fig.10 All data in the physical erase unit B1) in the first target physical erase unit B3 are moved to complete the first wear leveling operation.

[0084] Further explanation, the current physical erase unit B1 satisfies the preset condition, that is, the difference between the number of erase times of the current physical erase unit B1 and the average number of erase times is greater than the preset threshold, and the writing time thereof is also greater than the preset time threshold. In other words, the number of erase times of the current physical erase unit B1 is significantly different from the number of erase times of other physical erase units in the rewritable non-volatile memory module 43, and therefore, the current physical erase unit B1 needs to be put into the wear leveling operation to maintain the service life of the memory storage device 10. In addition, since the current physical erase unit B1 is an open physical erase unit that is not fully written, in order to cope with the characteristic of poor data stability in the open physical unit, the first wear leveling operation provided by the present invention is to move all data stored in the current physical erase unit B1 to the first target physical erase unit B3. In this way, the first wear leveling operation provided by the present invention can not only improve the service life of the memory storage device 10, but also further improve the data stability of the memory storage device 10.

[0085] In an exemplary embodiment, the implementation details of the memory management circuit 51 performing the first wear leveling operation may be as follows. Figures 10 to 12 As shown, Fig.11 is a flowchart of performing a first wear leveling operation according to an exemplary embodiment of the present invention;

[0086] Fig.12 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention. Figures 10 to 12 In step S1101, the memory management circuit 51 may determine whether there is a first target physical erase unit that is not fully written. Specifically, the first target physical erase unit is a physical erase unit used to store all data of the current physical erase unit in the first wear leveling operation. In an exemplary embodiment, the memory management circuit 51 may, for example, determine whether the first target physical erase unit in the previous first wear leveling operation is fully written to determine whether to continue to use the first target physical erase unit in the previous first wear leveling operation.

[0087] If there is no unfilled first target physical erase unit, then the process proceeds to step S1102. Fig.10 In step S1102, the memory management circuit 51 may select the physical erase unit B3 with the highest number of erase times from the idle pool 72 as the first target physical erase unit. Next, in step S1103, the memory management circuit 51 may move all data in the current physical erase unit B1 to the first target physical erase unit B3 to complete the first wear leveling operation.

[0088] It is worth mentioning that since the current physical erase unit B1 is an open physical erase unit that has not been fully written, in order to cope with the poor data stability of the open physical unit, the first wear leveling operation moves all data stored in the current physical erase unit B1 to the first target physical erase unit B3. This can improve the service life of the memory storage device 10 while also improving the data stability of the memory storage device 10.

[0089] On the contrary, if there is an unfilled first target physical erase unit, the process proceeds to step S1104. Fig.12 In step S1104 , the memory management circuit 51 may determine whether the remaining capacity of the unfilled first target physical erasure unit (eg, the physical erasure unit B6 ) is sufficient to store all the data in the current physical erasure unit B1 .

[0090] If the remaining capacity of the unfilled first target physical erase unit B6 is insufficient to store all the data in the current physical erase unit B1, the process returns to step S1102, and steps S1102 and S1103 are sequentially executed to complete the first wear leveling operation.

[0091] In contrast, if the remaining capacity of the unfilled first target physical erase unit B6 is sufficient to store all the data in the current physical erase unit B1, the process proceeds to step S1105. In step S1105, the memory management circuit 51 may move all the data in the current physical erase unit B1 to the unfilled first target physical erase unit B6 to complete the first wear leveling operation.

[0092] It is worth mentioning that the first wear leveling operation moves all data stored in the current physical erase unit B1 to the first target physical erase unit B6, which can improve the service life of the memory storage device 10 while improving the data stability of the memory storage device 10. In addition, the first target physical erase unit B6 is used to perform the first wear leveling operation, which can effectively avoid the waste of storage space of the memory storage device 10.

[0093] On the other hand, if the current physical erasing unit is full (ie, the current physical erasing unit is a closed physical erasing unit), the process proceeds to step S809. In step S809, the memory management circuit 51 may perform a second wear leveling operation on the current physical erasing unit.

[0094] In an exemplary embodiment, the implementation details of the memory management circuit 51 performing the second wear leveling operation may be as follows. Figures 13 to 16 As shown, Fig.13 is a flowchart of performing a second wear leveling operation according to an exemplary embodiment of the present invention;

[0095] Figures 14 to 16 is a schematic diagram of a storage pool and an idle pool according to an exemplary embodiment of the present invention. Figures 13 to 16 In step S1301, the memory management circuit 51 may determine whether there is a second target physical erase unit that is not fully written. Specifically, the second target physical erase unit is a physical erase unit used to store valid data of the current physical erase unit in the second wear leveling operation. In an exemplary embodiment, the memory management circuit 51 may determine whether the second target physical erase unit in the previous second wear leveling operation is fully written to determine whether to continue to use the second target physical erase unit in the previous second wear leveling operation.

[0096] If there is no unfilled second target physical erase unit, then the process proceeds to step S1302. Fig.14 In step S1302, the memory management circuit 51 may select the physical erase unit B3 with the highest number of erase times (ie, 515 times) from the idle pool 72 as the second target physical erase unit. Next, in step S1303, the memory management circuit 51 may select the current physical erase unit (ie, Fig.14 The valid data in the physical erase unit B2 in the first target physical erase unit is moved to the second target physical erase unit B3 to complete the second wear leveling operation.

[0097] On the contrary, if there is an unfilled second target physical erase unit, the process proceeds to step S1304. In step S1304, the memory management circuit 51 can further determine whether the remaining capacity of the unfilled second target physical erase unit is sufficient to store the valid data in the current physical erase unit.

[0098] If the remaining capacity of the second target physical erase unit is sufficient to store the valid data in the current physical erase unit, then the process proceeds to step S1305. Fig.15 In step S1305, the memory management circuit 51 may erase the current physical erase unit (ie, Fig.15 The valid data in the physical erase unit B2) is moved to the unfilled second target physical erase unit (for example, Fig.15 In this exemplary embodiment, the physical erase unit B1 in the embodiment is erased to complete the second wear leveling operation. Fig.15 As shown, after the second wear leveling operation is completed, the physical erase unit B1 is still not full, so the physical erase unit B1 is still associated with the open pool 711. In another exemplary embodiment, after the second wear leveling operation is completed, the physical erase unit B1 may be full and thus associated with the closed pool 712.

[0099] In contrast, if the remaining capacity of the second target physical erase unit is insufficient to store the valid data in the current physical erase unit, the process proceeds to step S1306. Fig.16 In step S1306, the memory management circuit 51 may select the physical erase unit B3 with the highest number of erase times (ie, 515 times) from the idle pool 72 as the second target physical erase unit. Next, in step S1307, the memory management circuit 51 may select the current physical erase unit (ie, Fig.16 The valid data in the physical erase unit B2) is sequentially moved to the unfilled second target physical erase unit (for example, Fig.16 The physical erase unit B1 in the second target physical erase unit B3 is erased to complete the second wear leveling operation. After the second wear leveling operation is completed, Fig.16 As shown, the physical erase unit B1 may be fully written and thus associated with the closed pool 712 , and the physical erase unit B3 is not fully written and thus associated with the open pool 711 .

[0100] According to the above, the second wear leveling operation of the present invention can effectively avoid wasting the storage space of the memory storage device 10 by continuing to use the second target physical erase unit that is not fully written.

[0101] Fig.17 is a flow chart of a wear leveling method according to an exemplary embodiment of the present invention. Fig.17 . In step S1701, based on the number of erase times and write time of each physical erase unit, determine whether each physical erase unit meets the preset conditions. In step S1702, if there is a current physical erase unit that meets the preset conditions, determine whether the current physical erase unit is full. In step S1703, if the current physical erase unit is not full, determine whether the current physical erase unit stores valid data. In step S1704, if the current physical erase unit stores valid data, perform a first wear leveling operation on the current physical erase unit.

[0102] However, Fig.17 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.17 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.17 The method can be used in combination with the above embodiments or can be used alone, and the present invention is not limited thereto.

[0103] In summary, the wear leveling method and memory storage device proposed in the exemplary embodiment of the present invention can further perform wear leveling operations on open physical erase units on the basis of the conventional wear leveling method for closed physical erase units to meet the user's usage habits. In addition, in the wear leveling operation on the open physical erase unit, by moving all the data of the open physical erase unit to the target physical erase unit, the service life of the memory storage device can be improved while the data stability of the memory storage device is improved. In addition, by continuing to use the target physical erase unit that is not fully written, the waste of storage space can be effectively avoided.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wear leveling method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, and the wear leveling method includes: Based on whether the number of erasure times and the writing time of each of the plurality of physical erasure units reaches a preset threshold, determining whether each of the plurality of physical erasure units meets a preset condition; If there is a current physical erasing unit that meets the preset condition among the multiple physical erasing units, determining whether the current physical erasing unit is full; If the current physical erasing unit is not fully written, performing a first wear leveling operation on the current physical erasing unit; If the current physical erasing unit is full, a second wear leveling operation is performed on the current physical erasing unit.

2. The wear leveling method according to claim 1, if the current physical erase unit is not full, further comprising: Determining whether the current physical erasing unit stores valid data; If the current physical erasing unit has valid data stored in it, performing a first wear leveling operation on the current physical erasing unit; If the current physical erase unit does not store valid data, the current physical erase unit is associated with an idle pool.

3. The wear leveling method according to claim 1 , wherein the step of determining whether each of the plurality of physical erasing units meets the preset condition based on the erasing times and the written time of each of the plurality of physical erasing units comprises: Determine whether the difference between the number of erasure times of each of the plurality of physical erasure units and the average number of erasure times is greater than a preset threshold; If there is at least one physical erasing unit among the plurality of physical erasing units whose difference is greater than the preset threshold, determining whether the written time of each of the at least one physical erasing unit is greater than the preset time threshold; as well as If there is a current physical erasing unit whose written time is greater than the preset time threshold in the at least one physical erasing unit, it is determined that the current physical erasing unit meets the preset condition.

4. The wear leveling method according to claim 1, wherein the step of performing the first wear leveling operation comprises: Selecting a physical erase unit with the highest erase count from the idle pool as a first target physical erase unit; as well as All data of the current physical erasing unit are moved to the first target physical erasing unit.

5. The wear leveling method according to claim 1 , wherein the step of performing the first wear leveling operation comprises: Determine whether there is a first target physical erase unit that is not fully written; as well as If the unfull first target physical erase unit does not exist, a physical erase unit with the highest erase count is selected from the idle pool as the first target physical erase unit, and all data in the current physical erase unit is moved to the first target physical erase unit.

6. The wear leveling method according to claim 5, wherein the step of performing the first wear leveling operation comprises: If the unfilled first target physical erase unit exists, determining whether the remaining capacity of the unfilled first target physical erase unit is sufficient to store all the data in the current physical erase unit; If yes, then all the data in the current physical erase unit are moved to the first target physical erase unit that is not fully written; as well as If not, the physical erase unit with the highest erase count is selected from the idle pool as the first target physical erase unit, and all the data in the current physical erase unit is moved to the first target physical erase unit.

7. The wear leveling method according to claim 1, wherein the step of performing the second wear leveling operation comprises: Determining whether there is a second target physical erase unit that is not fully written; as well as If the unfull second target physical erase unit does not exist, a physical erase unit with the highest erase count is selected from the idle pool as the second target physical erase unit, and valid data in the current physical erase unit is moved to the second target physical erase unit.

8. The wear leveling method according to claim 7, wherein the step of performing the second wear leveling operation comprises: If the unfilled second target physical erase unit exists, determining whether the remaining capacity of the unfilled second target physical erase unit is sufficient to store the valid data in the current physical erase unit; If yes, then moving the valid data in the current physical erase unit to the unfilled second target physical erase unit; as well as If not, the physical erase unit with the highest erase count is selected from the idle pool as the second target physical erase unit, and the valid data in the current physical erase unit is moved to the unfull second target physical erase unit and the second target physical erase unit in sequence.

9. The wear leveling method according to claim 1 , further comprising: Obtaining a plurality of erasure times of the plurality of physical erasure units; as well as An average erasure number is calculated according to the plurality of erasure numbers.

10. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Based on the erasure times and writing time of each of the plurality of physical erasing units, determining whether each of the plurality of physical erasing units meets a preset condition; If there is a current physical erasing unit that meets the preset condition among the multiple physical erasing units, determining whether the current physical erasing unit is full; If the current physical erasing unit is not fully written, performing a first wear leveling operation on the current physical erasing unit; If the current physical erasing unit is full, a second wear leveling operation is performed on the current physical erasing unit.

11. The memory storage device according to claim 10, wherein if the current physical erase unit is not fully written, the memory control circuit unit is further configured to Determining whether the current physical erasing unit stores valid data; If the current physical erasing unit has valid data stored in it, performing a first wear leveling operation on the current physical erasing unit; If the current physical erase unit does not store valid data, the current physical erase unit is associated with an idle pool.

12. The memory storage device according to claim 10, wherein the memory control circuit unit is further used to determine whether the difference between the number of erasure times of each of the plurality of physical erasure units and the average number of erasure times is greater than a preset threshold, If there is at least one physical erasing unit among the plurality of physical erasing units whose difference is greater than the preset threshold, the memory control circuit unit is further used to determine whether the written time of each of the at least one physical erasing unit is greater than the preset time threshold, and If there is a current physical erasing unit whose written time is greater than the preset time threshold in the at least one physical erasing unit, the memory control circuit unit is further configured to determine that the current physical erasing unit satisfies the preset condition.

13. The memory storage device according to claim 10, wherein the memory control circuit unit is further configured to select a physical erase unit with the highest erase count from the idle pool as the first target physical erase unit, and The memory control circuit unit is further used for moving all data of the current physical erasing unit to the first target physical erasing unit.

14. The memory storage device according to claim 10, wherein the memory control circuit unit is further configured to determine whether there is a first target physical erase unit that is not fully written, and If the unfilled first target physical erase unit does not exist, the memory control circuit unit is further configured to select a physical erase unit with the highest erase count from the idle pool as the first target physical erase unit, and move all data in the current physical erase unit to the first target physical erase unit.

15. The memory storage device according to claim 14, wherein if the unfilled first target physical erase unit exists, the memory control circuit unit is further configured to determine whether the remaining capacity of the unfilled first target physical erase unit is sufficient to store all the data in the current physical erase unit, If yes, the memory control circuit unit is further used to move all the data in the current physical erase unit to the first target physical erase unit that is not fully written, and If not, the memory control circuit unit is further configured to select the physical erase unit with the highest erase count from the idle pool as the first target physical erase unit, and move all the data in the current physical erase unit to the first target physical erase unit.

16. The memory storage device according to claim 10, wherein the memory control circuit unit is further configured to determine whether there is a second target physical erase unit that is not fully written, and If the unfilled second target physical erase unit does not exist, the memory control circuit unit is further configured to select a physical erase unit with the highest erase count from the idle pool as the second target physical erase unit, and move valid data in the current physical erase unit to the second target physical erase unit.

17. The memory storage device according to claim 16, wherein if the unfilled second target physical erase unit exists, the memory control circuit unit is further configured to determine whether the remaining capacity of the unfilled second target physical erase unit is sufficient to store the valid data in the current physical erase unit, If yes, the memory control circuit unit is further used to move the valid data in the current physical erase unit to the second target physical erase unit that is not fully written, and If not, the memory control circuit unit is further used to select the physical erase unit with the highest erase count from the idle pool as the second target physical erase unit, and sequentially move the valid data in the current physical erase unit to the unfull second target physical erase unit and the second target physical erase unit. 18 . The memory storage device according to claim 10 , wherein the memory control circuit unit is further configured to obtain a plurality of erasure times of the plurality of physical erasure units, and calculate an average erasure time according to the plurality of erasure times.

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