FIFO (First In First Out) data signal exchange method
Through the design of FIFO top-level circuit and control module, the increase in data selector caused by address pointers is avoided, and the problem of circuit area overhead in traditional FIFO circuits in new memory is solved, and the circuit area is achieved is lower, which is adapted to the high level of new memory. Speed and high density requirements.
Patent Information
- Application Number
- CN202411181472.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2024-12-17
AI Technical Summary
The existing FIFO control circuits use read and write address pointers, resulting in an increase in the number of data selectors, resulting in circuit area overhead, making it difficult to adapt to the low-area requirements of new memory, especially in the application of memory chips in wearable devices.
Using the FIFO data signal exchange method, the FIFO top-level circuit includes a FIFO register group and a FIFO control module, and receives signals from the SPI interface circuit, converts them into data update signals, FIFO data and shift signals, and controls the FIFO register group to realize data input, Shift, single shift and output functions avoid the increase in data selector caused by the use of address pointers and reduce the circuit area.
It effectively reduces the circuit area, making new memory more advantageous in low-area applications, and adapts to the speed and density requirements of new memory.
Smart Images
Figure CN119148969A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of memory, and in particular to a FIFO data signal exchange method with low area and no address pointer. Background Art
[0002] With the continuous advancement of semiconductor technology, the demand for memory speed and density is also increasing. Traditional memory technology based on silicon-based materials is currently facing theoretical and technical limits, namely the von Neumann bottleneck problem. In order to overcome these difficulties, prototype devices of a new generation of non-volatile memory have been proposed and widely studied. They include phase change memory, ferroelectric memory, magnetoresistive memory and resistive memory. Among them, resistive memory relies on the change of device resistance to store information. It has the advantages of simple structure, small area, fast speed and compatibility with CMOS process. As the next generation of mainstream non-volatile memory, it has great potential. However, with the increasing demand for speed and density of new memories, especially for memory chips in wearable devices, the size of the memory peripheral circuit area has become particularly important.
[0003] At present, the FIFO control circuit realizes the movement of the read and write space position based on dual pointers, including a read pointer and a write pointer. The key design lies in how to avoid the occurrence of empty reading and overflow, that is, it must be ensured that the FIFO cannot be written when it is full, and cannot be read when it is empty. Especially for asynchronous FIFOs, it is generally necessary to implement the logical mapping from the address of the read and write pointer to the full / empty status flag according to different algorithms, so as to further control the start and stop of reading and writing. The existing FIFO control circuit uses a read and write address pointer, which will lead to the integration of a large number of data selectors, resulting in a large amount of circuit area overhead, and ultimately making it increasingly difficult for traditional FIFOs to be applied to new embedded storage chips. Summary of the invention
[0004] The purpose of the present invention is to solve the problem that the existing FIFO circuit cannot adapt to the low-area characteristics of the new memory, and proposes a FIFO data signal exchange method, which avoids the situation where a large number of data selectors are integrated when using address pointers, thereby reducing the circuit area to the greatest extent.
[0005] In order to achieve the above-mentioned object of the invention, the technical solution of the present invention is as follows:
[0006] A FIFO data signal exchange method, characterized in that the FIFO top-level circuit includes a FIFO register group and a FIFO control module, the FIFO control module receives signals from an SPI interface circuit, and converts these signals into data update signals, FIFO data and shift signals respectively, and is used to control the FIFO register group to realize data input, data shift, data single shift, port cycle data selection and data output functions; thereby realizing that the FIFO top-level circuit transmits back signals related to the SPI interface, specifically comprising the following steps:
[0007] 1) The FIFO control module receives different FIFO signal flags and enters three different initial states respectively: when receiving the load signal flag, it enters the data loading state LOAD state; when receiving the shift flag, it enters the data shift SHIFT state; when receiving the single shift flag, it enters the data single shift state SSHIF state;
[0008] 2) In the LOAD state, the FIFO control module sets the data update signal high to control the data input of the FIFO register group, and then returns to the initial state;
[0009] 3) In the SHIFT state, the FIFO control module assigns the number of data shift bits to the internal counter and then enters the NEXT state;
[0010] 4) In the NEXT state, the FIFO control module sets the shift signal to a high level for a specified period according to the number of data shift bits to control the data shift of the FIFO register group, and then returns to the initial state;
[0011] 5) In the SSHIF state, the FIFO control module sets the shift signal to a high level for one cycle to control the single shift of data in the FIFO register group, and then returns to the initial state.
[0012] Furthermore, the signal transmitted from the SPI interface circuit in the memory chip to the FIFO top-level circuit specifically includes:
[0013] 1) Load signal flag, high level indicates data input operation, pulse signal lasts for 1 PCLK cycle width;
[0014] 2) Input data, input in parallel to the lowest register column of the FIFO register group;
[0015] 3) Shift flag, a high level indicates a data shift operation, and the pulse signal lasts for 1 PCLK cycle width;
[0016] 4) The number of data shift bits controls the depth of the FIFO register group shift;
[0017] 5) Single shift flag, a high level indicates a single data shift operation, and the pulse signal lasts for 1 PCLK cycle width;
[0018] 6) Output data, directly receive the highest bit FIFO register column data, and connect to the write drive circuit;
[0019] 7) Data busy signal, a high level indicates that the FIFO top-level circuit is performing FIFO related operations.
[0020] Furthermore, when data is input, the lowest register column accepts external data input: when the load signal flag is high, the FIFO control module generates a periodic high-level signal at the enable end of the lowest register column, controlling the lowest register column to accept external data as input. When data is output, the data in the highest register column is output, and the highest register column and the write drive circuit data are always accessible.
[0021] Furthermore, when the FIFO register group performs multiple shifts, the FIFO register group performs data shifting according to the required moving distance: when the shift flag position is high, the FIFO control module generates a high level signal corresponding to the number of cycles X at the register group shift enable end according to the shift distance.
[0022] Furthermore, the data shift of the FIFO register group follows the following principle: except for the lowest register column, each register column accepts the data of the lower register column as input, and the shift of each column input is one-to-one corresponding to the width position, and the lowest register column takes the data of the highest register column as input, so as to realize X times of adjacent data cyclic shift within X cycles.
[0023] Furthermore, the FIFO register group performs a single-cycle data shift. When the single shift flag is high, the FIFO control module generates a single-cycle high-level signal at the register group shift enable end to control all FIFO register columns to perform a single data shift from low to high.
[0024] Furthermore, when switching between data shifting and data input, the FIFO control module controls the selection of different input signals of the lowest register column according to the required operation: when the single shift flag or the shift flag position is high, the highest register column is selected as input; when the load signal flag position is high, the external data is selected as input.
[0025] Furthermore, all data in the register group are reset: the FIFO control module sets the reset flag high, generates a single-cycle high-level signal at the register group reset enable end, and controls all FIFO registers to reset.
[0026] The beneficial effects of the present invention are as follows:
[0027] Compared with the traditional FIFO with read-write address pointer, the FIFO top-level circuit of the present invention adopts a FIFO register group and a FIFO control module. The FIFO control module receives signals from the SPI interface circuit and converts these signals into data update signals, FIFO data and shift signals respectively, and is used to control the FIFO register group to realize data input, data shift, data single shift, port cycle data selection and data output functions, so as to realize the FIFO top-level circuit to transmit back signals related to the SPI interface, avoid the situation that the use of address pointers will synthesize a large number of data selectors, and minimize the circuit area, so that the new memory has more advantages in the field of low-area applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 Schematic diagram of signal transmission between FIFO top-level module and SPI interface circuit;
[0029] Figure 2 The top-level overall block diagram of FIFO of a specific embodiment of the present invention;
[0030] Figure 3 A schematic diagram of a FIFO register group according to a specific embodiment of the present invention;
[0031] Figure 4 A schematic diagram of state transition of a FIFO control module according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0032] The following specifically describes the implementation of the present invention based on an example of a FIFO register group with a depth of 64 and a width of 44.
[0033] Figure 1 The figure shows the overall block diagram of the most common SPI interface circuit in the industry and the FIFO top-level circuit to realize data signal exchange. The SPI interface circuit in the memory chip transmits the signal to the FIFO top-level circuit, and the FIFO top-level circuit transmits the signal related to the SPI interface back.
[0034] Figure 2 The figure shows the overall block diagram of the FIFO top-level circuit proposed by the present invention, which specifically includes a FIFO control module (FIFO_Controller) and a FIFO register group module (FIFO). The specific meanings of the various signals received by the SPI interface circuit by the FIFO control module are as follows:
[0035] SPI_FIFO_DATA_EN: Load signal flag, that is, data input valid signal. A high level indicates data input operation, and the pulse signal lasts for 1 PCLK cycle width.
[0036] SPI_FIFO_DATA[43:0]: 44-bit input data, parallel input to the lowest register column of the FIFO register group;
[0037] SPI_FIFO_SHIFT_EN: shift flag, that is, data shift valid signal, its high level indicates data shift operation, the pulse signal lasts for 1 PCLK cycle width;
[0038] SPI_FIFO_SHIFT_BIT[5:0]: The number of data shift bits, which controls the shift depth of the FIFO register group;
[0039] SPI_FIFO_SSHIF_EN: single shift flag, that is, data single shift valid signal, its high level indicates data single shift operation, the pulse signal lasts for 1 PCLK cycle width;
[0040] FIFO_SPI_TOP[43:0]: 44-bit output data, directly receives the highest-order FIFO register column data, and is connected to the write drive circuit (Write Drive[43:0]).
[0041] FIFO_SPI_BUSY: FIFO data busy signal, a high level indicates that the FIFO top-level circuit is performing FIFO related operations.
[0042] The FIFO control module receives SPI_FIFO_DATA_EN, SPI_FIFO_SHIFT_EN, and SPI_FIFO_SSHIF_EN from the SPI interface circuit, and converts these signals into data update signals (DATA_UPDATE), FIFO data (FIFO_DATA), and shift signals (F_SHIFT), respectively, to control the FIFO register group to realize data input, data shift, data single shift, port cycle data selection, and data output functions; the FIFO register group outputs 44-bit FIFO data by receiving the data update signals and shift signals generated by the FIFO control module.
[0043] Figure 3The figure shows a schematic diagram of the FIFO register group proposed by the present invention. Its depth is 64, corresponding to the number of bits of the sector address; the width is 44, corresponding to the number of sectors. When the data update signal (DADA_UPDATE) is valid, the 44-bit FIFO data (FIFO_DATA) is written into the lowest FIFO register column; when the shift signal (F_SHIFT) is valid, the FIFO register group controls the cyclic shift of the valid data according to the high level continuous period of the shift signal; when the data is written into the FIFO register group, the lowest FIFO register column receives the input data, and when the shift operation is performed, the lowest FIFO register column receives the cyclic shift data of the highest FIFO register column, thereby completing the selection of the FIFO register group port cyclic data; SPI_FIFO_TOP directly receives the highest FIFO register column data, and is connected to the write drive circuit (Write Drive) when needed to complete the output of the 44-bit FIFO data.
[0044] The FIFO data exchange method proposed by the present invention specifically includes:
[0045] IDLE: The initial state of the state machine. It enters three different states according to the different FIFO signal flags received: when the load signal flag (SPI_FIFO_DATA_EN) is received, it enters the LOAD state; when the shift flag (SPI_FIFO_SHIFT_EN) is received, it enters the SHIFT state; when the single shift flag (SPI_FIFO_SSHIF_EN) is received, it enters the SSHIF state.
[0046] LOAD: Data loading state. In this state, the data update signal (DATA_UPDATE) is set high to control the data input of the FIFO register group, and then returns to the initial state.
[0047] SHIFT: Data shift state. In this state, the data shift bit number (SPI_FIFO_SHIFT_BIT) is assigned to the internal counter, and then enters the NEXT state.
[0048] NEXT: In this state, the shift signal (F_SHIFT) is set to a high level for a specified period according to the number of data shift bits (SPI_FIFO_SHIFT_BIT) to control the data shift of the FIFO register group, and then returns to the initial state.
[0049] SSHIF: Data single shift state. In this state, the shift signal (F_SHIFT) is set to a high level for one cycle to control the data single shift of the FIFO register group, and then returns to the initial state.
[0050] Figure 4The figure shows a state transition diagram of the FIFO control module of the present invention, specifically:
[0051] 1) When data is input into the top circuit of FIFO, the lowest register column FIFO[0] accepts external data input: when the load signal flag FIFO_DATA_EN is set high, the FIFO control module generates a periodic high-level signal at the enable terminal DATA_UPDATE of the lowest register column FIFO[0] to control the lowest register column of FIFO to accept external data FIFO_DATA[W-1:0] as input;
[0052] 2) When FIFO data needs to be shifted multiple times, the FIFO register group shifts data according to the required moving distance FIFO_SHIFT_BIT[N-1:0]=X: When the shift flag FIFO_SHIFT_EN is set high, the FIFO control module generates a high-level signal corresponding to the number of cycles X at the register group shift enable terminal F_SHIFT according to the shift distance FIFO_SHIFT_BIT[N-1:0], and controls all FIFO register columns to shift data from low to high. The shift follows the following principles:
[0053] Except for the lowest register column FIFO[0], each register column FIFO[i] accepts the data of the lower register column FIFO[i-1] as input, and the shift of each column input is one-to-one corresponding to the width position. The lowest register column FIFO[0] takes the data of the highest register column FIFO[2^N-1] as input, so as to realize X times of adjacent data cyclic shift in X cycles.
[0054] 3) When the FIFO data only needs a single shift, the FIFO register group performs a single-cycle data shift: When the single shift flag FIFO_SSHIF_EN is set high, the FIFO control module generates a single-cycle high-level signal at the register group shift enable terminal F_SHIFT, and controls all FIFO register columns to perform a single data shift from the low-order FIFO[i-1] to the high-order FIFO[i]. The shift follows the same principle as step 2)
[0055] 4) When the FIFO data switches between data shifting and data input, the FIFO control module controls the selection of different input signals of the lowest register column FIFO[0] according to the required operation: when the single shift flag FIFO_SSHIF_EN or the shift flag FIFO_SHIFT_EN is set high, the highest register column FIFO[2^N-1] is selected as input; when the load signal flag FIFO_DATA_EN is set high, the external data FIFO_DATA[W-1:0] is selected as input;
[0056] 5) When FIFO data needs to be output, the data in the highest register column FIFO[2^N-1] is output: the highest register column FIFO[2^N-1] and the write drive circuit Write_Drive[W-1:0], and its data is always accessible.
[0057] 6) When the FIFO data needs to be reset, all the data in the register group are reset: when the reset flag RST_N is set high, a single cycle high-level signal is generated at the register group reset enable terminal RST_N to control all FIFO registers to reset
[0058] 7) When the FIFO register group is operating, the data busy signal output to the outside is set high: when the enable signal DATA_UPDATE of the lowest register column FIFO[0], the register group shift enable signal F_SHIFT or the reset flag RST_N is set high, the busy flag signal FIFO_BUSY is set high.
[0059] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.
Claims
1. A FIFO data signal exchange method, characterized in that: The FIFO top-level circuit includes a FIFO register group and a FIFO control module. The FIFO control module receives signals from the SPI interface circuit and converts these signals into data update signals, FIFO data and shift signals respectively, which are used to control the FIFO register group to realize data input, data shift, data single shift, port cycle data selection and data output functions; thereby realizing that the FIFO top-level circuit transmits back signals related to the SPI interface, which specifically includes the following steps: 1) The FIFO control module receives different FIFO signal flags and enters three different initial states respectively: when receiving the load signal flag, it enters the data loading state LOAD state; when receiving the shift flag, it enters the data shift SHIFT state; when receiving the single shift flag, it enters the data single shift state SSHIF state; 2) In the LOAD state, the FIFO control module sets the data update signal high to control the data input of the FIFO register group, and then returns to the initial state; 3) In the SHIFT state, the FIFO control module assigns the number of data shift bits to the internal counter and then enters the NEXT state; 4) In the NEXT state, the FIFO control module sets the shift signal to a high level for a specified period according to the number of data shift bits to control the data shift of the FIFO register group, and then returns to the initial state; 5) In the SSHIF state, the FIFO control module sets the shift signal to a high level for one cycle to control the single shift of data in the FIFO register group, and then returns to the initial state.
2. The FIFO data signal exchange method according to claim 1, characterized in that: The signals transmitted from the SPI interface circuit in the memory chip to the FIFO top-level circuit specifically include: 1) Load signal flag, high level indicates data input operation, pulse signal lasts for 1 PCLK cycle width; 2) Input data, input in parallel to the lowest register column of the FIFO register group; 3) Shift flag, a high level indicates a data shift operation, and the pulse signal lasts for 1 PCLK cycle width; 4) The number of data shift bits controls the depth of the FIFO register group shift; 5) Single shift flag, a high level indicates a single data shift operation, and the pulse signal lasts for 1 PCLK cycle width; 6) Output data, directly receive the highest bit FIFO register column data, and connect to the write drive circuit; 7) Data busy signal, a high level indicates that the FIFO top-level circuit is performing FIFO related operations.
3. The FIFO data signal exchange method according to claim 2, characterized in that: When data is input, the lowest register column accepts external data input: when the load signal flag is high, the FIFO control module generates a periodic high-level signal at the enable end of the lowest register column, controlling the lowest register column to accept external data as input. When data is output, the data in the highest register column is output, and the highest register column and the write drive circuit data are always accessible.
4. The FIFO data signal exchange method according to claim 3, characterized in that: When the FIFO register group performs multiple shifts, the FIFO register group performs data shifting according to the required moving distance: when the shift flag position is high, the FIFO control module generates a high level signal corresponding to the number of cycles X at the register group shift enable end according to the shift distance.
5. The FIFO data signal exchange method according to claim 4, characterized in that: The data shift of the FIFO register group follows the following principle: except for the lowest register column, each register column accepts the data of the lower register column as input, and the shift of each column input is one-to-one corresponding to the width position, and the lowest register column takes the data of the highest register column as input, so as to realize X times of adjacent data cyclic shift within X cycles.
6. The FIFO data signal exchange method according to claim 3, characterized in that: The FIFO register group performs a single-cycle data shift. When the single shift flag is high, the FIFO control module generates a single-cycle high-level signal at the register group shift enable end to control all FIFO register columns to perform a single data shift from low to high.
7. The FIFO data signal exchange method according to claim 3, characterized in that: When switching between data shifting and data input, the FIFO control module controls the selection of different input signals of the lowest register column according to the required operation: when the single shift flag or the shift flag is high, the highest register column is selected as input; when the load signal flag is high, the external data is selected as input.
8. The FIFO data signal exchange method according to claim 3, characterized in that: Reset all data in the register group: The FIFO control module sets the reset flag high, generates a single-cycle high-level signal at the register group reset enable end, and controls all FIFO registers to reset.