High-power chip microelectronic packaging defect detection method

Abstract

The invention belongs to the technical field of microelectronic packaging defects, and particularly relates to a high-power chip microelectronic packaging defect detection method. According to the method, when noise in a high-power chip microelectronic packaging image is eliminated, a structural element is used in the corrosion operation stage, and the method is generally called as pixel-by-pixel comparison between a core and the image. When the structural element completely covers the corresponding image area, setting the pixel corresponding to the output image as the foreground of the chip microelectronic packaging surface image, or else, setting the pixel corresponding to the output image as the background of the chip microelectronic packaging surface image; in the expansion operation stage, the execution mode is opposite to that of the corrosion operation. And detecting a reference straight line and a feature point in the chip microelectronic packaging surface image by means of Hough transformation, determining a rotation angle of the chip microelectronic packaging surface image, and performing adaptive correction. And carrying out threshold segmentation processing on the packaging defect by adopting a maximum between-class variance method, namely an Otsu method, and determining a specific state of the packaging defect according to a threshold distribution condition.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronic packaging defects, and in particular relates to a method for detecting defects in high-power chip microelectronic packaging. Background Art

[0002] In the chip microelectronic packaging processing stage, it is first necessary to ensure that the packaging process can completely fix the chip on the packaging base and use packaging resin or other packaging materials for packaging to protect the chip from damage by the external environment. Secondly, the packaging must also ensure that the connection between the chip and the circuit board is stable and reliable, facilitating communication and data transmission between the chip and external devices. In addition, the accuracy and consistency of the packaging process are crucial, which will directly affect the performance and reliability of the chip. When conducting chip packaging defect detection, with the rapid development of the integrated circuit industry, the IC size is getting smaller and smaller, and the packaging process is becoming more and more complex, which increases the difficulty of defect detection. In addition, there are various types of defects that may occur in the packaging process, including scratches, stains, bubbles, etc., and each defect requires specific detection methods and strategies. At the same time, in order to meet the needs of actual applications, it is necessary to increase the detection speed while ensuring the detection accuracy to meet the needs of large-scale production.

[0003] In the literature: Lightweight chip packaging defect detection method based on improved YOLOv5, a lightweight chip packaging defect detection method based on improved YOLOv5 is proposed. By adding a channel attention mechanism after the feature extraction module, the attention of the defect channel is improved, thereby improving the detection accuracy of the target. At the same time, the fast feature pyramid structure and MobileNetV3 are used to effectively reduce the model size and computational complexity, and it has higher adaptability when deployed on resource-limited industrial embedded devices. However, this method is only trained and tested for a specific chip packaging data set, and its generalization ability needs to be further verified. Literature: Multi-scale IC metal packaging surface defect detection based on MST-GAN, a multi-scale IC metal packaging defect detection method based on MST-GAN is proposed. MST-GAN can capture the multi-scale features of the IC metal packaging surface, and can have good detection effects for defects of different sizes and types. And for various complex environments and conditions in the IC packaging manufacturing process, this method may have good robustness. However, compared with lightweight models, MST-GAN has a higher model complexity and may have higher requirements for hardware resources. In addition, on high-speed production lines, real-time performance may be an issue that needs further optimization.

[0004] Since chip microelectronic packaging defects are usually subtle, it is difficult to ensure effective detection when testing them. Summary of the invention

[0005] The purpose of the present invention is to solve the above technical problems and propose a method for detecting defects in high-power chip microelectronic packaging.

[0006] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0007] A high-power chip microelectronic packaging defect detection method comprises the following steps:

[0008] S1. Preprocessing of chip microelectronic package surface image: To eliminate noise in high-power chip microelectronic package image, when removing noise from the original chip microelectronic package surface image, first use the corrosion operation to eliminate small noise and isolated pixels in the image; then use the dilation operation to restore the foreground area that has been reduced due to the corrosion operation;

[0009] S2. Rotation correction of chip microelectronic package surface image: Hough transform is used to perform rotation correction processing on the denoised chip microelectronic package surface image, and the straight lines or other regular shapes in the image are identified and corrected. Hough transform is applied to detect the reference straight lines and feature points in the chip microelectronic package surface image, so as to determine the rotation angle of the chip microelectronic package surface image and perform adaptive correction;

[0010] S3. Packaging defect recognition and detection: For the corrected surface image of the microelectronic package of the chip to be inspected, the maximum between-class variance method, namely the Otsu method, is used to perform threshold segmentation processing, and the specific state of the packaging defect is determined according to the threshold distribution; through the classification judgment standard, combined with the output result of the Otsu function of the surface image of the microelectronic package of the chip to be inspected, the defect state is detected.

[0011] Further, as a preferred technical solution of the present invention, the S1 comprises the following steps: based on morphological operations, combined with specific functions of the OpenCV image processing library;

[0012] In the corrosion operation stage, a structural element, called a kernel, is used to compare the image pixel by pixel. When the structural element completely covers the corresponding image area, the corresponding pixel of the output image is set as the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image. The specific processing method is expressed as follows:

[0013]

[0014] Among them, E represents the input chip microelectronic package surface image, that is, the original image to be processed, and B represents the structural element, which is used to define the range and shape of the corrosion operation, which is a 3x3 rectangular kernel. represents the corrosion operation, and x represents the sign for selecting the foreground of the chip microelectronic package surface image corresponding to the pixel of the image by using the pixel extrapolation method; the corrosion operation is used to reduce the foreground area of ​​the chip microelectronic package surface image, and eliminate the small noise and isolated pixels existing in the original chip microelectronic package surface image;

[0015] In the dilation operation stage, the execution mode is opposite to the erosion operation, that is, by comparing the structure element with the image pixel by pixel, retaining any pixel where the structure element intersects with the image, that is, setting the output image pixel as the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image;

[0016]

[0017] in, Represents the dilation operation, y represents the flag for selecting the image background of the surface of the microelectronic package of the pixel chip corresponding to the image; the dilation operation is used to expand the foreground area to fill the holes and the broken connection areas.

[0018] Further, as a preferred technical solution of the present invention, S2 includes the following steps: using Hough transform to map points in the chip microelectronic package surface image space to parameter space; for straight line detection, using polar coordinates to represent the mapping results of points in the image in the parameter space, specifically:

[0019] ρ=xcosα+ysinα(3)

[0020] Among them, ρ represents the distance parameter from the point in the chip microelectronic package surface image space to the target detection line in the parameter space, and α represents the angle between the target detection line and the horizontal direction;

[0021] When using Hough transform to detect straight lines or other regular shapes in an image, these shapes are used as a reference for rotation correction of the overall chip microelectronic package surface image, and the method of identifying feature points based on this is expressed as:

[0022] I=(lmax-x) 2 +y 2 (4)

[0023] Where I represents the feature point extraction result of the chip microelectronic packaging surface image, l represents the target detection line;

[0024] At this time, the rotation angle of the chip microelectronic package surface image is calculated by combining formula (4), which is specifically expressed as:

[0025]

[0026] Wherein, θ represents the rotation angle of the chip microelectronic package surface image; according to the rotation angle calculated by formula (5), the chip microelectronic package surface image is rotationally corrected so that the feature points are aligned with the horizontal line; thus, the rotation correction processing of the chip microelectronic package surface image is realized.

[0027] Further, as a preferred technical solution of the present invention, S3 includes the following steps: Considering that the Otsu method is an operation performed on a grayscale image, the surface image of the chip microelectronic package to be detected is in the form of a grayscale image, and the specific processing method is expressed as follows:

[0028]

[0029] Among them, R(i,j), G(i,j) and B(i,j) together constitute the grayscale information of the pixel point of the image on the surface of the microelectronic package of the chip to be inspected corresponding to the (x,y) coordinate;

[0030] The Otsu function is applied to perform threshold segmentation on the grayscale image, and the global threshold is used to maximize the inter-class variance between the foreground, i.e., the defect, and the background. The specific implementation method is as follows:

[0031]

[0032] Among them, g(i,j) represents the grayscale parameter of the pixel point on the surface of the microelectronic package of the chip to be inspected corresponding to the (x,y) coordinate output by the Otsu function; when R(i,j), G(i,j) and B(i,j) are greater than or equal to the global threshold, the value of g(i,j) is 1; when R(i,j), G(i,j) and B(i,j) are less than the global threshold, the value of g(i,j) is 0; the image is segmented into two parts, i.e., the foreground, i.e., the defect, and the background, using the Otsu method;

[0033] When determining the defect state of the package according to the threshold distribution, the binary image after the threshold segmentation is observed; the foreground, i.e. the defective part, will be displayed as white or highlighted, and the background part will be displayed as black or dimmed;

[0034] When the classification criteria are: appearing as a thin and long white or bright area extending in a certain direction; the defect type is a scratch;

[0035] When the classification criteria are: similar to a scratch, but may be longer, deeper or more irregular; then the defect type is a scratch;

[0036] When the classification criteria are: white or bright isolated areas in a black background, usually with a small area; the defect type is a hole;

[0037] When the classification criteria are: a larger white or highlighted area, which indicates that part of the area is missing or damaged; the defect type is defect;

[0038] When the classification criteria are: a white or highlighted area that is clearly different from the surrounding environment, with a specific shape, size or color; the defect type is foreign matter.

[0039] The high-power chip microelectronic packaging defect detection method described in the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0040] (1) The high-power chip microelectronic packaging defect detection method of the present invention effectively realizes the effective detection of different types of packaging defects and has good practical application value in the chip production quality control link. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the method steps of an embodiment of the present invention;

[0042] Figure 2 Schematic diagram of chip microelectronic packaging defect types in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention is further explained below in detail with reference to the accompanying drawings so that those skilled in the art can more deeply understand the present invention and be able to implement it. However, the following reference examples are only used to explain the present invention and are not intended to limit the present invention.

[0044] like Figure 1 As shown, the present invention proposes a high-power chip microelectronic package defect detection method, including the following steps: S1, chip microelectronic package surface image preprocessing; for the original chip microelectronic package surface image, due to the influence of objective environmental light conditions and image acquisition equipment performance, there may be certain noise, which will interfere with the defect detection results. In view of this, the present invention uses corrosion operations and expansion operations to eliminate noise in high-power chip microelectronic package images. In the specific execution process, the basic principles of morphological operations are followed, and the specific functions of the OpenCV image processing library are combined to achieve it.

[0045] In the corrosion operation stage, the present invention mainly compares the image pixel by pixel through a structural element (usually called a kernel). When the structural element completely covers the corresponding image area, the corresponding pixel of the output image is set as the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image. The specific processing method can be expressed as:

[0046]

[0047] Among them, E represents the input chip microelectronic package surface image, that is, the original image to be processed, and B represents the structural element. This article uses this element to define the range and shape of the corrosion operation, specifically a 3x3 rectangular kernel. Represents the corrosion operation, and x represents the sign for selecting the foreground of the image corresponding to the pixel chip microelectronic package surface image by using the pixel extrapolation method.

[0048] By using this operation mode, the foreground area of ​​the chip microelectronic package surface image is reduced, and the small noise and isolated pixels existing in the original chip microelectronic package surface image are eliminated. [8] .

[0049] In the dilation operation stage, the execution method is opposite to the erosion operation, that is, by comparing the structural element with the image pixel by pixel, retaining any pixel where the structural element intersects with the image, that is, setting the output image pixel to the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image.

[0050]

[0051] in, Represents the dilation operation, and y represents the flag for selecting the image background of the surface of the microelectronic package chip corresponding to the pixel of the image.

[0052] Using this operation, the foreground region is expanded to fill holes and disconnected areas.

[0053] According to the above processing method, when removing noise from the original chip microelectronic package surface image, the corrosion operation is first used to remove small noise and isolated pixels in the image; and the expansion operation is then used to restore the foreground area that has been reduced by the corrosion operation. In this way, the preprocessing of the chip microelectronic package surface image is achieved.

[0054] S2. Rotation correction of the chip microelectronic package surface image: For the denoised chip microelectronic package surface image, the present invention uses Hough transform to perform rotation correction processing on it, wherein the main purpose of performing the operation is to identify and correct the straight lines or other regular shapes in the image, so as to ensure that the corresponding basic data is more complete and reliable in the subsequent defect detection stage. In the actual implementation process, although Hough transform is usually used for the detection of straight lines or curves, in the application of the present invention, it is applied to detect reference straight lines and feature points in the chip microelectronic package surface image, so as to determine the rotation angle of the chip microelectronic package surface image and perform adaptive correction.

[0055] The present invention uses Hough transform to map points in the chip microelectronic package surface image space to parameter space. In this way, the problem of line detection in the chip microelectronic package surface image is transformed into the problem of finding peaks in parameter space. For line detection, the present invention uses polar coordinates to represent the mapping results of points in the image in parameter space, specifically:

[0056] ρ=x cosα+y sinα (3)

[0057] Among them, ρ represents the distance parameter from the point in the chip microelectronic package surface image space to the target detection line in the parameter space, and α represents the angle between the target detection line and the horizontal direction.

[0058] Based on the above mapping method, when using Hough transform to detect straight lines or other regular shapes in the image, these shapes are used as references for rotation correction of the surface image of the entire chip microelectronic package. The method of identifying feature points based on this can be expressed as

[0059] I=(lmax-x) 2 +y 2 (4)

[0060] Where I represents the feature point extraction result of the chip microelectronic packaging surface image, and l represents the target detection line.

[0061] At this time, combined with formula (4), the rotation angle of the chip microelectronic package surface image is calculated, which can be specifically expressed as

[0062]

[0063] Wherein, θ represents the rotation angle of the chip microelectronic package surface image. According to the rotation angle calculated by formula (5), the chip microelectronic package surface image is rotated and corrected so that the feature points are aligned with the horizontal line.

[0064] According to the above-mentioned method, the rotation correction processing of the chip microelectronic packaging surface image is realized, which provides a reliable execution basis for the subsequent packaging defect detection.

[0065] S3. Packaging defect recognition and detection: For the corrected surface image of the chip microelectronic package to be detected, the present invention uses the maximum between-class variance method (Otsu method) to perform threshold segmentation processing on it, and determines the specific state of the packaging defect according to the threshold distribution. It is a complex process involving image processing and analysis.

[0066] First, considering that the Otsu method is an operation performed on a grayscale image, it is necessary to convert the surface image of the chip microelectronic package to be detected into a grayscale image. The specific processing method can be expressed as

[0067]

[0068] Among them, R(i,j), G(i,j) and B(i,j) together constitute the grayscale information of the pixel point of the image on the surface of the microelectronic package of the chip to be inspected, corresponding to the (x,y) coordinate.

[0069] On this basis, the Otsu function is applied to perform threshold segmentation on the grayscale image, and the global threshold is used to maximize the inter-class variance between the foreground (defect) and the background. The specific implementation method can be expressed as

[0070]

[0071] Among them, g(i,j) represents the grayscale parameter of the pixel point on the surface of the microelectronic package of the chip to be detected corresponding to the (x,y) coordinate output by the Otsu function. When R(i,j), G(i,j) and B(i,j) are greater than or equal to the global threshold, the value of g(i,j) is 1; when R(i,j), G(i,j) and B(i,j) are less than the global threshold, the value of g(i,j) is 0.

[0072] In the manner shown above, the image is segmented into foreground (defect) and background using the Otsu method.

[0073] According to the threshold distribution, the package defect status can be determined by observing the binary image after threshold segmentation. Among them, the foreground (defect) part will be displayed as white or high light, and the background part will be displayed as black or low light. The specific defect detection and classification judgment criteria are shown in Table 1.

[0074] Table 1 Package defect identification, detection and classification criteria

[0075]

[0076] like Figure 2 As shown, according to the above judgment criteria, combined with the Otsu function output result of the surface image of the microelectronic package of the chip to be detected, the defect state is detected to ensure the accuracy of recognition and classification.

[0077] When analyzing the performance of the chip microelectronic packaging defect detection method of the present invention, comparative tests were carried out. Among them, the specific control groups were respectively Literature 1: Lightweight chip packaging defect detection method based on improved YOLOv5, a lightweight chip packaging defect detection method based on improved YOLOv5, and Literature 2: Multi-scale IC metal packaging surface defect detection based on MST-GAN, a multi-scale IC metal packaging defect detection method based on MST-GAN.

[0078] For specific test data, the high-power chip microelectronic packaging defect image dataset from the actual production process of multiple microelectronic packaging manufacturing companies is used as the basis. The basic composition of the dataset is analyzed. Among them, the chip specification classification is mainly the QFP (quad flat package) series, including plastic QFP and MQFP (metricquad flat package) types.

[0079] (1) Plastic QFP: As a common package type, it has the characteristics of various pin center distances and a large number of pins. The dataset contains plastic QFP chips of various specifications, such as QFP with a center distance of 0.65 mm, whose maximum number of pins can reach 304.

[0080] (2) MQFP (metric quad flat package): It differs from plastic QFP in structure and performance, but is also widely used in the microelectronics industry.

[0081] (3) Other package types: In addition to the QFP series, this data set also includes other types of packaged chips, such as BGA (ball grid array package), SOIC (small outline integrated circuit package), etc. These package types differ in terms of pin arrangement, packaging materials, etc.

[0082] In addition to the above preparations, the parameters of the method of the present invention are set as shown in Table 2.

[0083] Table 2 Parameters of the method of the present invention

[0084]

[0085] On the basis of the above, the present invention combines the common defect types of actual high-power chip microelectronic packaging and selects Figure 2 Shown are five common types of chip packaging defects.

[0086] according to Figure 2 The classification of chip microelectronic packaging defects shown in the figure shows that the scratch defect is manifested as a large area of ​​polished area, and the test data set includes center substrate scratches and pin scratches. The scratch defect is manifested as a long and thin strip. Compared with the scratch, the scratch area on the pin is smaller. The test data set is divided into center substrate scratches and pin scratches. Hole defects mainly occur on the surface or inside of the solder joint. The defect defect is mainly the missing of the pin or substrate. Foreign matter defects refer to the mixing of unexpected substances such as dust and fibers into the chip package during the packaging process.

[0087] By recording and classifying the above five defect types in detail, the present invention sets the test data scale of each defect type to 100 (not limiting the specific chip type), and analyzes the performance of the three methods by analyzing the detection of defects.

[0088] On the basis of the above, the effective detection of different types of packaging defects by the three methods is statistically analyzed, and the obtained data results are shown in Table 3.

[0089] Table 3 Comparison of test results of different methods

[0090]

[0091] Combined with the test results shown in Table 2, the detection performance of three different methods is compared and analyzed. Among them, under the lightweight chip packaging defect detection method based on improved YOLOv5 proposed in document 1, the number of effective detections of different types of defects is relatively stable, basically stable in the range of 90.00%-93.00%, and there is room for further improvement in the overall level; under the multi-scale IC metal packaging defect detection method based on MST-GAN proposed in document 2, the detection performance of scratch defects is obviously skewed, and the specific effective detection rate is only 86.00%; in contrast, in the test results of the method of the present invention, the number of effective detections of different types of defects is higher than 95, and the overall comprehensive effective detection rate reaches 96.40%, which is 3.80% higher than the detection method in document 1 and 3.40% higher than the detection method in document 2. Based on the above comparative analysis of the test results, it can be concluded that the high-power chip microelectronic packaging defect detection method proposed in the present invention can achieve effective detection of different types of defects and has good practical application value.

[0092] The invention provides a high-power chip microelectronic package defect detection method, which effectively realizes the effective detection of different types of package defects and has good practical application value in the chip production quality control link.

[0093] The specific implementation scheme described above further describes in detail the purpose, technical scheme and beneficial effects of the present invention. It should be understood that the above is only a specific implementation scheme of the present invention and is not intended to limit the scope of the present invention. Any equivalent changes and modifications made by any technician in the field without departing from the concept and principle of the present invention should fall within the scope of protection of the present invention.

Claims

1. A high-power chip microelectronic packaging defect detection method, characterized in that: The following steps are involved: S1. Preprocessing of chip microelectronic package surface image: To eliminate noise in high-power chip microelectronic package image, when removing noise from the original chip microelectronic package surface image, first use the corrosion operation to eliminate small noise and isolated pixels in the image; then use the dilation operation to restore the foreground area that has been reduced due to the corrosion operation; S2. Rotation correction of chip microelectronic package surface image: Hough transform is used to perform rotation correction processing on the denoised chip microelectronic package surface image, and the straight lines or other regular shapes in the image are identified and corrected. Hough transform is applied to detect the reference straight lines and feature points in the chip microelectronic package surface image, so as to determine the rotation angle of the chip microelectronic package surface image and perform adaptive correction; S3. Packaging defect recognition and detection: For the corrected surface image of the microelectronic package of the chip to be inspected, the maximum between-class variance method, namely the Otsu method, is used to perform threshold segmentation processing, and the specific state of the packaging defect is determined according to the threshold distribution; through the classification judgment standard, combined with the output result of the Otsu function of the surface image of the microelectronic package of the chip to be inspected, the defect state is detected.

2. A high-power chip microelectronic packaging defect detection method according to claim 1, characterized in that: The S1 comprises the following steps: based on morphological operations, combined with specific functions of the OpenCV image processing library; In the corrosion operation stage, a structural element, called a kernel, is used to compare the image pixel by pixel. When the structural element completely covers the corresponding image area, the corresponding pixel of the output image is set as the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image. The specific processing method is expressed as follows: Among them, E represents the input chip microelectronic package surface image, that is, the original image to be processed, and B represents the structural element, which is used to define the range and shape of the corrosion operation, which is a 3x3 rectangular kernel. represents the corrosion operation, and x represents the sign for selecting the foreground of the chip microelectronic package surface image corresponding to the pixel of the image by using the pixel extrapolation method; the corrosion operation is used to reduce the foreground area of ​​the chip microelectronic package surface image, and eliminate the small noise and isolated pixels existing in the original chip microelectronic package surface image; In the dilation operation stage, the execution mode is opposite to the erosion operation, that is, by comparing the structure element with the image pixel by pixel, retaining any pixel where the structure element intersects with the image, that is, setting the output image pixel as the foreground of the chip microelectronic package surface image, otherwise, it is the background of the chip microelectronic package surface image; in, Represents the dilation operation, y represents the flag for selecting the image background of the surface of the microelectronic package of the pixel chip corresponding to the image; the dilation operation is used to expand the foreground area to fill the holes and the broken connection areas.

3. A high-power chip microelectronic packaging defect detection method according to claim 2, characterized in that: The step S2 includes the following steps: using Hough transform to map points in the chip microelectronic package surface image space to parameter space; for straight line detection, using polar coordinates to represent the mapping results of points in the image in the parameter space, specifically: ρ=xcosα+ysinα(3) Among them, ρ represents the distance parameter from the point in the chip microelectronic package surface image space to the target detection line in the parameter space, and α represents the angle between the target detection line and the horizontal direction; When using Hough transform to detect straight lines or other regular shapes in an image, these shapes are used as a reference for rotation correction of the overall chip microelectronic package surface image, and the method of identifying feature points based on this is expressed as: I=(lmax-x) 2 +y 2 (4) Where I represents the feature point extraction result of the chip microelectronic packaging surface image, l represents the target detection line; At this time, the rotation angle of the chip microelectronic package surface image is calculated by combining formula (4), which is specifically expressed as: Wherein, θ represents the rotation angle of the chip microelectronic package surface image; according to the rotation angle calculated by formula (5), the chip microelectronic package surface image is rotationally corrected so that the feature points are aligned with the horizontal line; thus, the rotation correction processing of the chip microelectronic package surface image is realized.

4. A high-power chip microelectronic packaging defect detection method according to claim 3, characterized in that: S3 includes the following steps: Considering that the Otsu method is an operation performed on a grayscale image, the surface image of the chip microelectronic package to be detected is in the form of a grayscale image. The specific processing method is expressed as follows: Among them, R(i,j), G(i,j) and B(i,j) together constitute the grayscale information of the pixel point of the surface image of the microelectronic package of the chip to be inspected corresponding to the (x,y) coordinate; The Otsu function is applied to perform threshold segmentation on the grayscale image, and the global threshold is used to maximize the inter-class variance between the foreground, i.e., the defect, and the background. The specific implementation method is as follows: Among them, g(i,j) represents the grayscale parameter of the pixel point on the surface of the microelectronic package of the chip to be inspected corresponding to the (x,y) coordinate output by the Otsu function; when R(i,j), G(i,j) and B(i,j) are greater than or equal to the global threshold, the value of g(i,j) is 1; when R(i,j), G(i,j) and B(i,j) are less than the global threshold, the value of g(i,j) is 0; the image is segmented into two parts, i.e., the foreground, i.e., the defect, and the background, using the Otsu method; When determining the defect state of the package according to the threshold distribution, the binary image after the threshold segmentation is observed; the foreground, i.e. the defective part, will be displayed as white or highlighted, and the background part will be displayed as black or dimmed; When the classification criteria are: appearing as a thin and long white or bright area extending in a certain direction; the defect type is a scratch; When the classification criteria are: similar to a scratch, but may be longer, deeper or more irregular; then the defect type is a scratch; When the classification criteria are: white or bright isolated areas in a black background, usually with a small area; the defect type is a hole; When the classification criteria are: a larger white or highlighted area, which indicates that part of the area is missing or damaged; the defect type is defect; When the classification criteria are: a white or highlighted area that is clearly different from the surrounding environment, with a specific shape, size or color; the defect type is foreign matter.

Images