Epitaxial wafer and manufacturing method and device thereof

Abstract

The invention provides an epitaxial wafer and a manufacturing method and device thereof, and the method comprises the steps: judging whether the SFQRmax of the epitaxial wafer has a set correlation with the ESFQD value in the angle direction with the SFQRmax when the absolute value of the difference between the ESFQD values of the epitaxial wafer in two symmetrical angle directions is smaller than a set difference threshold value; if the ESFQD values have the correlation, when the average value of the ESFQD values of the epitaxial wafer is positive and is greater than a set first average threshold value, determining an improvement means for reducing the thickness of the edge epitaxial layer; if the ESFQD values have the correlation, when the average value of the ESFQD values of the epitaxial wafer is negative and smaller than a set second average value threshold value, determining an improvement means for increasing the thickness of the edge epitaxial layer; and after improving the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, carrying out epitaxial growth on the polished wafer to be subjected to epitaxial growth according to the improved epitaxial process parameters.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a manufacturing method and device thereof. Background Art

[0002] As substrates used in the manufacturing process of semiconductor devices, wafers made of semiconductors such as silicon wafers are widely used. It is known that there are polished wafers (PW) made by slicing single crystal ingots and performing grinding, polishing, cleaning and other processing processes, and epitaxial wafers with single crystal silicon epitaxial layers formed on the surface of polished wafers by chemical vapor deposition and other methods. The epitaxial wafers obtained by chemical vapor deposition have the characteristics of few surface defects, excellent crystallization performance and controllable resistivity.

[0003] The flatness of the epitaxial wafer surface is an important parameter affecting the performance of semiconductor devices. The better the flatness, the higher the device yield and performance. Therefore, improving flatness is an important part of epitaxial wafer research. Summary of the invention

[0004] The present disclosure provides an epitaxial wafer and a method and device for manufacturing the same; the flatness of the epitaxial wafer can be improved.

[0005] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for manufacturing an epitaxial wafer, the method comprising: When the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than the set difference threshold, the maximum local flatness SFQR of the epitaxial wafer is determined. max With the SFQR max Whether the ESFQD value in the angular direction has the set correlation; If the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, determining an improvement measure for reducing the thickness of the edge epitaxial layer; If the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than the set second mean value threshold, determining an improvement measure for increasing the thickness of the edge epitaxial layer; After improving the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, epitaxial growth is performed on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

[0006] In a second aspect, the present disclosure provides an epitaxial wafer manufacturing device, the epitaxial wafer manufacturing device comprising: a first determination unit, a second determination unit, a determination unit, and an epitaxial execution unit; wherein, The first determination unit is configured to determine the maximum local flatness SFQR of the epitaxial wafer when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than a set difference threshold. max With the SFQR max Whether the ESFQD value in the angular direction has the set correlation; The second determination unit is configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold; The determining unit is configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, determine an improvement measure for reducing the thickness of the edge epitaxial layer; The second determination unit is further configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is negative and is less than a set second mean value threshold; The determining unit is further configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than a set second mean value threshold, determine an improvement means for increasing the thickness of the edge epitaxial layer; The epitaxial execution unit is configured to improve the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, and then perform epitaxial growth on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

[0007] In a third aspect, the present disclosure provides an epitaxial wafer manufacturing device, the epitaxial wafer manufacturing device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the epitaxial wafer manufacturing method as described in the first aspect.

[0008] In a fourth aspect, the present disclosure provides an epitaxial wafer, which is manufactured by the method for manufacturing an epitaxial wafer described in the first aspect, and the ESFQD value of the epitaxial wafer is in [-11, -3], and the SFQRmax of the epitaxial wafer is less than or equal to 14.92.

[0009] The present invention discloses an epitaxial wafer and a method and device for manufacturing the same; the ESFQD values ​​of the epitaxial wafer after epitaxial growth are detected to be substantially the same in the symmetrical angle direction and the SFQR of the epitaxial wafer is max With SFQR maxWhen the ESFQD values ​​in the angular direction are correlated, the improvement measures for the subsequent polished wafers to be epitaxially grown are determined according to the mean value of the ESFQD values, so that the ESFQD values ​​of the epitaxial wafers produced by the subsequent polished wafers can be close to or reach the interval corresponding to the lower SFQR value, thereby improving the flatness of the epitaxial wafers produced by the subsequent polished wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the structure of the epitaxial growth equipment provided in the present invention.

[0011] Figure 2 A schematic flow chart of a method for manufacturing an epitaxial wafer provided in the present invention.

[0012] Figure 3 A schematic diagram of obtaining an epitaxial wafer when the wafer provided in the present disclosure is centered on an epitaxial susceptor.

[0013] Figure 4 The disclosure provided in Figure 3 A graph showing the variation of the ESFQD value of the epitaxial wafer obtained under the shown conditions with the angular direction.

[0014] Figure 5 Schematic diagram of the center of the polished wafer provided for the present disclosure being offset from the center of the epitaxial susceptor.

[0015] Figure 6 The disclosure provided in Figure 5 A graph showing the variation of the ESFQD value of the epitaxial wafer obtained under the shown conditions with the angular direction.

[0016] Figure 7 The disclosure provided in Figure 5 Map of SFQR values ​​of epitaxial wafers obtained under the conditions shown.

[0017] Figure 8 A schematic diagram of the correlation between the ESFQD value and the SFQR value provided in the present disclosure.

[0018] Fig. 9 Another graph provided by the present disclosure shows the variation of ESFQD value of an epitaxial wafer with angular direction.

[0019] Fig.10 Provided for this disclosure Fig. 9 The SFQR value map of the epitaxial wafer is shown.

[0020] Fig.11 A schematic diagram of a base height provided in the present disclosure.

[0021] Fig.12 Schematic diagram of reducing the base height provided for the present disclosure.

[0022] Fig.13 Another graph provided by the present disclosure shows that the ESFQD value of an epitaxial wafer varies with the angular direction.

[0023] Fig.14 Provided for this disclosure Fig.13 The SFQR value map of the epitaxial wafer is shown.

[0024] Fig.15 A schematic diagram of increasing the base height provided for the present disclosure.

[0025] Fig.16 A schematic diagram of the composition of an epitaxial wafer manufacturing device provided in the present invention.

[0026] Fig.17 A schematic structural diagram of an epitaxial wafer manufacturing device provided in the present invention. DETAILED DESCRIPTION

[0027] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0028] See also Figure 1 , which shows a schematic diagram of the structure of an epitaxial growth device 1 capable of implementing the technical solution of the present disclosure. The epitaxial growth device 1 comprises: The epitaxial base 10 is used to carry the polished wafer W; The support frame 20 is used to support the epitaxial pedestal 10 and drive the epitaxial pedestal 10 to rotate around the central axis X at a certain speed during the epitaxial growth process. During the rotation of the epitaxial pedestal 10, the polished wafer W rotates around the central axis X together with the epitaxial pedestal 10, that is, the polished wafer W remains stationary relative to the epitaxial pedestal 10. Therefore, a small gap G is required between the radial edge of the epitaxial pedestal 10 and the adjacent component 10A (usually a preheating ring).

[0029] The upper bell jar 30A and the lower bell jar 30B together enclose a reaction chamber RC containing the epitaxial base 10 and the support frame 20. The epitaxial base 10 divides the reaction chamber RC into an upper reaction chamber RC1 and a lower reaction chamber RC2, and the polished wafer W is placed in the upper reaction chamber RC1. Usually, the gas pressure in the upper reaction chamber RC1 is slightly greater than the gas pressure in the lower reaction chamber RC2, so that the gas in the upper reaction chamber RC1 can enter the lower reaction chamber RC2 through the gap G.

[0030] In some examples, the upper bell 30A and the lower bell 30B are made of quartz.

[0031] The gas inlet 40 is used to transport epitaxial reaction gas, such as silicon source gas such as SiHCl3, hydrogen, and dopant gas such as B2H6 or PH3, into the upper reaction chamber RC1, so that silicon atoms are generated by the reaction of the silicon source gas and hydrogen and deposited on the surface of the polished wafer W, thereby growing an epitaxial layer on the surface of the polished wafer W. In addition, the epitaxial layer is doped by the dopant gas to obtain a desired resistivity.

[0032] The exhaust port 50 is used to discharge the reaction tail gas out of the reaction chamber RC.

[0033] The heating bulb 60 is disposed at the periphery of the upper bell jar 30A and the lower bell jar 30B and is used to provide a high temperature environment for chemical vapor deposition in the reaction chamber RC through the upper bell jar 30A and the lower bell jar 30B.

[0034] A mounting member 70 for assembling the various elements of the epitaxial growth apparatus 1 .

[0035] For the epitaxial wafer produced by the epitaxial growth device 1 , as the semiconductor manufacturing process continues to develop, the index for evaluating its flatness may change accordingly.

[0036] It should be noted that in the present disclosure, the indicators used to evaluate the flatness of the epitaxial wafer may include: the edge site front least squares deviation (ESFQD) used to characterize the flatness of the edge of the epitaxial wafer. Specifically, ESFQD is an indicator of the local flatness (Site flatness) of the edge (also referred to as the periphery) of the epitaxial wafer. ESFQD divides the edge of the epitaxial wafer into multiple (for example, 72) fan-shaped areas (local areas), and uses the least squares method to fit an imaginary plane as the reference plane within each fan-shaped area. ESFQD is the positive or negative distance deviation of each fan-shaped area relative to the reference plane within the area, expressed as a ± value. In some examples, each of the above-mentioned fan-shaped areas is an area of ​​2mm-5mm in the diameter direction from the outermost periphery of the epitaxial wafer as an excluded area, and then uses a fan-shaped area extending 15mm from the outer peripheral reference end that is inner than the excluded area to the center side of the wafer.

[0037] In the present disclosure, in addition to ESFQD, the indicators used to evaluate the flatness of epitaxial wafers may also include: Site Front surface referenced least squares range (SFQR) for evaluating the local flatness of epitaxial wafers. For example, taking a 12-inch epitaxial wafer or a 300 mm diameter epitaxial wafer as an example, the surface of the entire epitaxial wafer is divided into local areas using squares of any size (for example, 26 mm × 8 mm). In each local area (square), after calculating the reference plane based on the thickness value, the maximum difference between the thickness value of the point in the local area (square) and the reference plane is used as the SFQR value of the local area. In addition, the maximum value among the SFQR values ​​of all local areas (squares), that is, the SFQR max It can be used as an indicator to characterize the flatness of the entire surface of the epitaxial wafer.

[0038] In order to improve the flatness of the epitaxial wafer, the present disclosure intends to utilize the correlation between the above two indicators, and adjust the subsequent epitaxial process of vapor deposition on the polished wafer to be epitaxial by analyzing the above two indicators of the epitaxial wafer after vapor deposition. Figure 2 , which shows a process flow of a method for manufacturing an epitaxial wafer provided by the present disclosure, and the method may include steps S201 to S204.

[0039] In step S201, when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than the set difference threshold, the maximum local flatness SFQR of the epitaxial wafer is determined. max With SFQR max Whether the ESFQD value in the angular direction has a set correlation.

[0040] In this disclosure, Figure 3 As shown, the polished wafer W is centrally located during the epitaxial growth process. Figure 1 On the epitaxial base 10 shown, the center O of the polished wafer W completely coincides with the center P of the epitaxial base 10. In this case, the curve of the ESFQD value of the epitaxial wafer W' obtained by epitaxial growth as a function of the angle direction is as shown in FIG. Figure 4 As shown. Figure 4 In the curve graph shown, the ordinate represents the ESFQD value, and the abscissa represents the angle direction (Angle) of the epitaxial wafer W'. In the present disclosure, the angle direction refers to the angle direction relative to a set direction D0 passing through the center O of the epitaxial wafer W'. The set direction D0 may be a reference direction of 0°.

[0041] pass Figure 4It can be observed that when the wafer is centered relative to the epitaxial base, the ESFQD values ​​of the grown epitaxial wafer W' are all kept within a relatively stable normal value range, for example Figure 2 In addition, it can be observed that the ESFQD values ​​in any pair of symmetrical angular directions of the epitaxial wafer W' are substantially the same. For example, the ESFQD values ​​in two angular directions symmetrical with respect to the center of the epitaxial wafer are substantially the same, such as two opposite angular directions passing through the center (angular directions with an angle difference of 180 degrees), for example Figure 3 The pair of directions OX and OY in the figure. Alternatively, the ESFQD values ​​in any pair of two angular directions of the epitaxial wafer W' that are mirror-symmetric relative to the set reference direction are approximately the same, for example, two directions with 180 degrees as the reference direction and the absolute values ​​of the angle differences with the reference direction are equal. It should be noted that the above-mentioned "approximately the same" can be determined by whether the absolute value of the difference between the ESFQD values ​​in the two angular directions is less than the set difference threshold. For example, when the absolute value of the difference between the ESFQD values ​​in the two angular directions is less than the set difference threshold, it means that the ESFQD values ​​in the two angular directions are approximately the same. Otherwise, it is determined that the ESFQD values ​​in the two angular directions are not the same.

[0042] Based on this understanding, when the ESFQD values ​​in any pair of symmetrical angular directions are different, that is, when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in the two symmetrical angular directions is greater than the set difference threshold, it can be considered that the center O of the polished wafer W deviates from the center P of the epitaxial base 10. In this case, Figure 5 As shown, the center O of the polished wafer W no longer coincides (is offset) with the center P of the epitaxial base 10, and the curve of the ESFQD of the epitaxial wafer W" thus grown varies with the angular direction is shown in FIG. Figure 6 As shown, and the SFQR value mapping diagram of the epitaxial wafer W" is as follows Figure 7 shown.

[0043] from Figure 6 It can be observed that when the epitaxial base 10 is offset, some of the ESFQD values ​​of the grown epitaxial wafer W" are significantly beyond the range of -10 to 5, and in these values, the ESFQD values ​​in two partially symmetrical angular directions of the epitaxial wafer differ greatly. For example, the ESFQD values ​​in the 60° direction and the 240° direction are -13 and 14, respectively, indicating that the edge flatness of the epitaxial wafer W" has deteriorated.

[0044] from Figure 7It can be observed that the color depth of the area indicated by the dotted box with the wafer center as the symmetry center is quite different from the color depth of the area symmetrical with the wafer center. This means that in these two areas, the SFQR values ​​of the squares symmetrical with the wafer center are quite different, indicating that the flatness of the epitaxial wafer W" is poor.

[0045] Through the above Figure 6 and Figure 7 It can be seen from the analysis that when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angular directions is greater than or equal to the set difference threshold, it means that the center O of the polished wafer W deviates from the center P of the epitaxial base 10. In this case, the present disclosure determines that the means of improving the epitaxial process parameters for the subsequent epitaxial wafer to be grown is to adjust the position of the polished wafer on the base so that the center O of the polished wafer W coincides with the center P of the epitaxial base 10. After improving the epitaxial process parameters by adopting the above-mentioned improvement means, the ESFQD values ​​of the surface of the epitaxial wafer obtained by epitaxially growing the polished wafer to be grown epitaxially in the subsequent epitaxial growth in the two symmetrical angular directions are approximately the same.

[0046] In the present disclosure, when the ESFQD values ​​in any pair of symmetrical angle directions of the epitaxial wafer W' are approximately the same, the inventor analyzes the ESFQD value of the surface of the epitaxial wafer W' and the SFQR value of the local area of ​​the angle direction corresponding to the surface of the epitaxial wafer W' and the ESFQD value, and can obtain Figure 8 The corresponding relationship between ESFQD value and SFQR value is shown in Figure 2. Figure 8 In the figure, the horizontal and vertical coordinates of each point represent the ESFQD value and the SFQR value of the local area in the angle direction corresponding to the ESFQD value. Figure 8 It can be found that there is a correlation between the ESFQD value on the surface of the epitaxial wafer and the SFQR value of the local area in the corresponding angular direction, and this correlation can be obtained by Figure 8 The coordinate points in are characterized by the fitted straight line equation as shown by the dashed line. In some examples, Figure 8 The equation of the straight line shown by the dashed line can be used Figure 8 The coordinate points in are obtained by least square fitting, which will not be elaborated in this disclosure.

[0047] For the wafer surface with the maximum local flatness SFQR max The local area of ​​the corresponding angle direction of the ESFQD should also meet the above Figure 8In the specific implementation process, in order to determine whether the ESFQD value of the epitaxial wafer surface and the SFQR value of the local area in the corresponding angular direction meet the correlation, the ESFQD value can be first substituted into the fitted linear equation and the corresponding SFQR calculated value can be calculated. Then, the absolute value of the difference between the actual SFQR value of the local area in the angular direction corresponding to the ESFQD value and the SFQR calculated value is obtained. Finally, the absolute value is compared with the set threshold. If it is less than the threshold, it means that the correlation is met, otherwise it means that the correlation is not met. For the SFQR with the maximum local flatness max If the ESFQD value in the corresponding angle direction is equal to SFQR max If the correlation is not met, it means that the base 10 is tilted during the process of epitaxial growth on the polished wafer W to obtain the epitaxial wafer W'. This is because when the base 10 is tilted, the heated area of ​​the silicon wafer in the chamber will also change, resulting in a larger SFQR in some areas. In this case, the present disclosure determines that the means to improve the epitaxial process parameters for the subsequent epitaxial wafers to be grown is to adjust the horizontality of the base 10 so that the base 10 remains horizontal during the epitaxial growth process. After improving the epitaxial process parameters by adopting the above-mentioned improvement means, in the epitaxial wafer obtained by epitaxial growth on the polished wafer to be grown, the maximum local flatness SFQR of the epitaxial wafer surface is max With the SFQR max The ESFQD values ​​in the angular direction are correlated.

[0048] In step S202, if there is a correlation, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, an improvement measure for reducing the thickness of the edge epitaxial layer is determined.

[0049] In this disclosure, by continuing to observe Figure 8 It can also be seen that when the ESFQD value is in the range [-11,-3], Figure 8 As shown in the dashed box, the SFQR value is generally smaller than the SFQR values ​​of other coordinate points. max The value is 14.92 nm. In this case, it can be seen that in the epitaxial wafer, the flatness of the portion corresponding to the coordinate point indicated by the dotted line frame is high.

[0050] Based on this understanding, in this disclosure, by observing Fig. 9 The graph of the ESFQD value of the epitaxial wafer W' as a function of the angle direction and Fig.10It can be seen from the SFQR value mapping diagram of the epitaxial wafer W' that the ESFQD values ​​are all positive and have a large difference from the [-11, -3] interval. In the present disclosure, "biased positive" can also be used to describe this situation, and Fig.10 SFQR max The value is 32.01nm. In this case, it indicates that the flatness of the epitaxial wafer W' is poor. The inventor analyzed the reasons and found that ESFQD is the positive or negative distance deviation of each sector area relative to the reference plane in the area, expressed as ± value. When the thickness of the epitaxial layer at the edge of the epitaxial wafer W' is relatively high, the ESFQD value is more likely to be positive. Based on this, the present disclosure determines that the means to improve the epitaxial process parameters of the subsequent epitaxial wafers to be grown is to reduce the thickness of the edge epitaxial layer, so that the ESFQD value of the surface of the epitaxial wafer obtained by epitaxially growing the polished wafer to be grown epitaxially is in the range of [-11, -3].

[0051] In some examples, when the ESFQD values ​​are all positive, the set first mean threshold can be used to determine whether they are "largely different from the interval [-11, -3]", that is, when the mean of the ESFQD values ​​of the epitaxial wafer is greater than the first mean threshold, it means that the ESFQD value of the epitaxial wafer "is greatly different from the interval [-11, -3]". When the mean of the ESFQD values ​​of the epitaxial wafer is not greater than the first mean threshold, it means that the ESFQD value of the epitaxial wafer "is not much different from the interval [-11, -3]". In some examples, combined with Figure 8 The first mean threshold can be calculated based on the expected SFQR max Numerical combination Figure 8 In the present disclosure, the first mean value threshold can be determined from a range of values ​​greater than 0.

[0052] In some examples, the improvement means for reducing the thickness of the edge epitaxial layer may be implemented by at least one of the following three means: 1. Reduce the epitaxial temperature during epitaxial deposition. Specifically, affected by the temperature field distribution in the reaction chamber RC of the epitaxial growth equipment 1, the edge temperature of the base 10 is higher than the center position of the base 10. As a result, in the polished wafer W, the temperature of the area closer to the edge of the base 10 is higher. Generally speaking, the higher the temperature, the faster the epitaxial layer grows. When the temperature rises, in the epitaxial layer of the wafer, the area closer to the edge of the base 10 shows a faster growth rate, which leads to a higher thickness of the epitaxial layer at the edge of the epitaxial wafer W'. Therefore, in order to reduce the thickness of the edge epitaxial layer, the temperature during the vapor deposition (Deposition) process can be reduced to reduce the growth rate of the edge epitaxial layer, so that less single crystal silicon is deposited on the edge of the wafer, so that the ESFQD value of the improved epitaxial wafer is close to or reaches the [-11, -3] interval. In some examples, the temperature of the current epitaxial wafer during the vapor deposition (Deposition) process is reduced by 3 to 5 degrees Celsius to reduce the epitaxial temperature of subsequent epitaxial wafers during the epitaxial deposition process. For example, the current temperature of the epitaxial wafer during the deposition process is 1120 degrees Celsius. Based on this 1120 degrees, the process can be improved by reducing the temperature by 3 to 5 degrees Celsius to reduce the growth rate of the edge epitaxial layer, so that less single crystal silicon is deposited on the edge of the wafer.

[0053] 2. Increase the duration of the coating phase during the cleaning of the reaction chamber. Specifically, during the epitaxial growth process, a cleaning process will be performed in the reaction chamber RC after each epitaxial wafer is grown or multiple epitaxial wafers are grown continuously. The purpose is to clean the by-products generated during the vapor deposition process, and a coating phase will be performed to coat a layer of polysilicon on the surface of the base 10 that is used to contact the back of the wafer. The thickness of the polysilicon coating is negatively correlated with the heat radiated to the back of the polished wafer W by the heating bulb 60 arranged on the periphery of the lower bell jar 30B. Based on this, by increasing the duration of the coating phase to increase the thickness of the polysilicon coating, the heat radiated to the back of the polished wafer W is reduced, thereby reducing the growth rate of the epitaxial layer at the edge of the wafer, resulting in less single crystal silicon deposited on the edge of the wafer, so that the ESFQD value of the improved epitaxial wafer is close to or reaches the [-11, -3] range. In some examples, based on the duration of the current coating phase, 15 to 20 seconds are added to increase the duration of the coating phase in the subsequent cleaning of the reaction chamber. For example, if the duration of the current coating phase is 40 seconds, then 15 to 20 seconds are added to the 40s duration to improve the process, so as to reduce the growth rate of the edge epitaxial layer and reduce the single crystal silicon deposited on the edge of the wafer.

[0054] 3. Reduce the height of the pedestal used to support the wafer. Specifically, Fig.11 As shown in FIG. 1 , the gas flow formed by the epitaxial reaction gas delivered by the gas inlet 40 shown by the dotted arrow is usually above the wafer. Fig.12 As shown, with the adjacent component 10A as a reference, the height of the pedestal supporting the wafer is reduced by h. In this case, the epitaxial reaction gas deposited on the edge of the wafer will be reduced, thereby reducing the growth rate of the edge epitaxial layer, resulting in less single crystal silicon deposited on the edge of the wafer, and ultimately enabling the improved ESFQD value of the epitaxial wafer to approach or reach the [-11, -3] range. In some examples, the height of the bottom of the pedestal is reduced by 1-4 mm based on the bottom of the pedestal being in the same horizontal plane as the bottom of the adjacent component 10A, that is, the value range of h is -1 to -4 mm.

[0055] In step S203, if there is a correlation, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than the set second mean value threshold, an improvement measure for increasing the thickness of the edge epitaxial layer is determined.

[0056] In this disclosure, by observing Fig.13 The graph of the ESFQD value of the epitaxial wafer W' as a function of the angle direction and Fig.14 The schematic diagram of the SFQR value of the epitaxial wafer W' shows that the ESFQD values ​​are all negative and differ greatly from the [-11, -3] interval. In the present disclosure, "negative" can also be used to describe this situation, and Fig.14 SFQR max The value is 21.74nm. In this case, it also indicates that the flatness of the epitaxial wafer W' is poor. The inventor analyzed the reason and found that ESFQD is the positive or negative distance deviation of each sector area relative to the reference plane in the area, expressed as ± value. When the thickness of the epitaxial layer at the edge of the epitaxial wafer W' is relatively low, it is more likely that the ESFQD value will be negative. It can be known that the cause is the lower thickness of the epitaxial layer at the edge of the epitaxial wafer W'. Based on this, the present disclosure can determine that the means of improving the epitaxial process parameters for the subsequent epitaxial wafers to be grown is to increase the thickness of the epitaxial layer at the edge, so that the ESFQD value of the surface of the epitaxial wafer obtained by epitaxially growing the polished wafer to be grown epitaxially is in the range of [-11, -3].

[0057] In some examples, when the ESFQD values ​​are all negative, the set second mean threshold can be used to determine whether they are "largely different from the interval [-11, -3]", that is, when the mean of the ESFQD values ​​of the epitaxial wafer is less than the first mean threshold, it means that the ESFQD value of the epitaxial wafer is "largely different from the interval [-11, -3]". When the mean of the ESFQD values ​​of the epitaxial wafer is not less than the first mean threshold, it means that the ESFQD value of the epitaxial wafer is "not much different from the interval [-11, -3]". In some examples, combined with Figure 8 The second mean threshold can be calculated based on the expected SFQR max Numerical combination Figure 8 In the present disclosure, the second mean value threshold can be determined from a value range less than -13.

[0058] In the present disclosure, corresponding to the three implementation means shown in the aforementioned step S202, in some examples, for the improvement means for increasing the thickness of the edge epitaxial layer, at least one of the following three means may be used in the specific implementation process: 1. Increase the epitaxial temperature during epitaxial deposition. Specifically, since the higher the temperature, the faster the epitaxial layer grows, when the temperature rises, in the epitaxial layer of the wafer, the area closer to the edge of the base 10 shows a faster growth rate, which in turn leads to a higher thickness of the epitaxial layer at the edge of the epitaxial wafer W'. Therefore, in order to increase the thickness of the edge epitaxial layer, the temperature during the vapor deposition (Deposition) process can be increased to increase the growth rate of the edge epitaxial layer, so that more single crystal silicon is deposited on the edge of the wafer, so that the ESFQD value of the improved epitaxial wafer is close to or reaches the [-11, -3] range. In some examples, the temperature of the current epitaxial wafer during the vapor deposition (Deposition) process is increased by 3 to 5 degrees Celsius to increase the epitaxial temperature of subsequent epitaxial wafers during the epitaxial deposition process. For example, the temperature of the current epitaxial wafer during the Deposition process is 1120 degrees Celsius, then 3 to 5 degrees Celsius is increased on the basis of 1120 degrees to improve the process to increase the growth rate of the edge epitaxial layer, so that more single crystal silicon is deposited on the edge of the wafer.

[0059] 2. Reduce the duration of the coating phase during the process of cleaning the reaction chamber. Specifically, the thickness of the polysilicon coating applied to the surface of the base 10 during the coating phase is negatively correlated with the heat radiated to the back of the polished wafer W by the heating bulb 60 arranged on the periphery of the lower bell jar 30B. Based on this, by reducing the duration of the coating phase (for example, from 40 seconds to 20 seconds) to reduce the thickness of the polysilicon coating, and then increasing the heat radiated to the back of the polished wafer W, the growth rate of the epitaxial layer at the edge of the wafer is increased, resulting in more single crystal silicon deposited on the edge of the wafer, so that the ESFQD value of the improved epitaxial wafer is close to or reaches the [-11, -3] range. In some examples, based on the duration of the current coating phase, it is reduced by 15 seconds to 20 seconds to reduce the duration of the coating phase in the subsequent cleaning of the reaction chamber. For example, the current coating phase duration is 40 seconds, so based on the 40 seconds duration, the process can be improved by reducing it by 15 to 20 seconds to increase the growth rate of the edge epitaxial layer so that more single crystal silicon is deposited on the edge of the wafer.

[0060] 3. Raise the height of the base used to support the wafer. Specifically, Fig.15 As shown, when the height of the wafer-carrying pedestal is raised, for example, with the adjacent component 10A as a reference, the height of the wafer-carrying pedestal is raised by h. In this case, the epitaxial reaction gas deposited on the edge of the wafer will increase, thereby increasing the growth rate of the edge epitaxial layer, resulting in more single crystal silicon deposited on the edge of the wafer, and ultimately making the ESFQD value of the improved epitaxial wafer close to or reaching the [-11, -3] range. In some examples, the height of the bottom of the pedestal is increased by 1-4 mm based on the bottom of the pedestal being in the same horizontal plane as the bottom of the adjacent component 10A, that is, the value range of h is 1 to 4 mm.

[0061] In step S204, after the epitaxial process parameters of the epitaxial wafer are improved based on the determined improvement means, epitaxial growth is performed on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

[0062] In the present disclosure, it should be noted that after determining any improvement means according to the above steps for the epitaxial wafer that has completed epitaxial growth, the epitaxial process parameters of the epitaxial growth equipment that currently produces the epitaxial wafer are improved using the above-determined improvement means. Then, the epitaxial growth of the subsequent polished wafer is performed using the improved epitaxial process parameters, so that the ESFQD value of the epitaxial wafer produced can approach or reach the [-11, -3] range, thereby improving the flatness of the epitaxial wafer produced by the subsequent polished wafer.

[0063] According to the above technical solution, the ESFQD values ​​of the epitaxial wafers after epitaxial growth are detected to be substantially the same in the symmetrical angle direction and the SFQR of the epitaxial wafers are max With SFQR max When the ESFQD values ​​in the angular direction are correlated, the improvement measures for the subsequent polished wafers to be epitaxially grown are determined according to the mean value of the ESFQD values, so that the ESFQD values ​​of the epitaxial wafers produced by the subsequent polished wafers can be close to or reach the interval corresponding to the lower SFQR value, thereby improving the flatness of the epitaxial wafers produced by the subsequent polished wafers.

[0064] Based on the same inventive concept as the above technical solution, see Fig.16 , which shows an epitaxial wafer manufacturing device 160 provided by the present disclosure, the epitaxial wafer manufacturing device 160 includes: a first determination unit 1601, a second determination unit 1602, a determination unit 1603 and an epitaxial execution unit 1604; wherein, The first determination unit 1601 is configured to determine the maximum local flatness SFQR of the epitaxial wafer when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than a set difference threshold. max With the SFQR max Whether the ESFQD value in the angular direction has the set correlation; The second determination unit 1602 is configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold; The determining unit 1603 is configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, determine an improvement measure for reducing the thickness of the edge epitaxial layer; The second determination unit 1602 is further configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is negative and is less than a set second mean value threshold; The determining unit 1603 is further configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than a set second mean value threshold, determine an improvement means for increasing the thickness of the edge epitaxial layer; The epitaxial execution unit 1604 is configured to improve the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, and then perform epitaxial growth on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

[0065] for Fig.16 In the manufacturing device 160 of the epitaxial wafer shown in the figure, in a specific implementation process, the epitaxial execution unit 1604 can be Figure 1 The epitaxial growth device 1 shown in the figure is used to implement the epitaxial growth. Specifically, after the epitaxial process parameters of the epitaxial growth device 1 are improved according to the determined improvement means, epitaxial growth is performed on the subsequent polished wafers according to the improved epitaxial process parameters, so that the ESFQD value of the epitaxial wafer produced by the subsequent polished wafer can be close to or reach the interval corresponding to the lower SFQR value, thereby improving the flatness of the epitaxial wafer produced by the subsequent polished wafer.

[0066] In some examples, the two angular directions of symmetry include: two angular directions that are symmetrical relative to the center of the epitaxial wafer; or two angular directions that are mirror-symmetrical relative to a set reference direction.

[0067] In some examples, the improvement means for reducing the thickness of the edge epitaxial layer includes at least one of the following: The growth rate of the edge epitaxial layer is reduced by lowering the epitaxial temperature during epitaxial deposition, the thickness of the polysilicon coating is increased by increasing the length of the coating phase during cleaning the reaction chamber, and the epitaxial reaction gas deposited on the edge of the wafer is reduced by lowering the height of the pedestal used to support the wafer.

[0068] In some examples, the improvement means for increasing the thickness of the edge epitaxial layer includes at least one of the following: The growth rate of the edge epitaxial layer is increased by increasing the epitaxial temperature during the epitaxial deposition process, the thickness of the polysilicon coating is reduced by reducing the length of the coating stage during the cleaning of the reaction chamber, and the epitaxial reaction gas deposited on the edge of the wafer is increased by raising the height of the base used to support the wafer.

[0069] In some examples, the first mean threshold has a value range greater than 0; the second mean threshold has a value range less than -13.

[0070] In some examples, the determining unit 1603 is further configured to: When the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angular directions is greater than a set difference threshold, an improvement measure is determined for adjusting the position of the polished wafer on the susceptor so that the center of the wafer coincides with the center of the epitaxial susceptor.

[0071] In some examples, the determining unit 1603 is further configured to: If the maximum local flatness SFQRmax of the epitaxial wafer does not have a set correlation with the ESFQD value in the angular direction having the SFQRmax, an improvement means for adjusting the horizontality of the susceptor so that the susceptor remains horizontal during epitaxial growth is determined.

[0072] Please refer to Fig.17, which shows a structural block diagram of an epitaxial wafer manufacturing device 160 provided by an exemplary embodiment of the present disclosure. In some examples, the epitaxial wafer manufacturing device 160 can be at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The epitaxial wafer manufacturing device 160 has a communication function and can be connected to a wired network or a wireless network. The epitaxial wafer manufacturing device 160 can generally refer to one of a plurality of terminals, and those skilled in the art can know that the number of the above terminals can be more or less. In some examples, the epitaxial wafer manufacturing device 160 can receive and send data based on the wired network or wireless network to which it is connected. It can be understood that the epitaxial wafer manufacturing device 160 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0073] like Fig.17 As shown, the epitaxial wafer manufacturing apparatus 160 in the present disclosure may include one or more of the following components: a processor 1710 and a memory 1720 .

[0074] Optionally, the processor 1710 uses various interfaces and lines to connect various parts of the entire computing device, and executes various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1720, and calling data stored in the memory 1720. Optionally, the processor 1710 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1710 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1710, but may be implemented by a separate chip.

[0075] The memory 1720 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 1720 includes a non-transitory computer-readable storage medium. The memory 1720 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1720 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0076] In addition, those skilled in the art can understand that the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0077] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for manufacturing an epitaxial wafer as described in the above embodiments.

[0078] The present disclosure also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the method for manufacturing an epitaxial wafer described in each of the above embodiments.

[0079] Based on the aforementioned technical solution, the present disclosure also provides an epitaxial wafer, which is manufactured by the epitaxial wafer manufacturing method described in the aforementioned technical solution, and the ESFQD value of the epitaxial wafer is in [-10, -3], and the SFQRmax of the epitaxial wafer is less than or equal to 15.

[0080] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0081] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0082] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for manufacturing an epitaxial wafer, characterized in that: The method comprises: When the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than the set difference threshold, the maximum local flatness SFQR of the epitaxial wafer is determined. max With the SFQR max Whether the ESFQD value in the angular direction has the set correlation; If the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, determining an improvement measure for reducing the thickness of the edge epitaxial layer; If the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than the set second mean value threshold, determining an improvement means for increasing the thickness of the edge epitaxial layer; After improving the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, epitaxial growth is performed on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

2. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The two symmetrical angular directions include: two angular directions that are symmetrical relative to the center of the epitaxial wafer; or two angular directions that are mirror-symmetrical relative to a set reference direction.

3. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The improvement means for reducing the thickness of the edge epitaxial layer includes at least one of the following: By reducing the epitaxial temperature during epitaxial deposition to reduce the growth rate of the edge epitaxial layer, By increasing the length of the coating phase during the cleaning of the reaction chamber to increase the thickness of the polysilicon coating, The height of the susceptor used to support the wafer is lowered to reduce the epitaxial reaction gas deposited on the edge of the wafer.

4. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The improvement means for increasing the thickness of the edge epitaxial layer includes at least one of the following: By increasing the epitaxial temperature during epitaxial deposition to increase the growth rate of the edge epitaxial layer, By reducing the duration of the coating phase during the cleaning of the reaction chamber, the thickness of the polysilicon coating can be reduced. The height of the susceptor used to support the wafer is raised to increase the epitaxial reaction gas deposited on the edge of the wafer.

5. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The value range of the first mean threshold is greater than 0; the value range of the second mean threshold is less than -13.

6. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The method also includes: when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angular directions is greater than a set difference threshold, determining an improvement measure for adjusting the position of the polished wafer on the base so that the center of the wafer coincides with the center of the epitaxial base.

7. The method for manufacturing an epitaxial wafer according to claim 1, characterized in that: The method further comprises: if the maximum local flatness SFQR of the epitaxial wafer max With the SFQR max The ESFQD values ​​in the angular direction do not have a set correlation, and an improved means for adjusting the horizontality of the susceptor so that the susceptor remains horizontal during epitaxial growth is determined.

8. An epitaxial wafer manufacturing device, characterized in that: The epitaxial wafer manufacturing device comprises: a first determination unit, a second determination unit, a determination unit and an epitaxial execution unit; wherein, The first determination unit is configured to determine the maximum local flatness SFQR of the epitaxial wafer when the absolute value of the difference between the ESFQD values ​​of the epitaxial wafer in two symmetrical angle directions is less than a set difference threshold. max With the SFQR max Whether the ESFQD value in the angular direction has the set correlation; The second determination unit is configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold; The determining unit is configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is positive and greater than a set first mean value threshold, determine an improvement measure for reducing the thickness of the edge epitaxial layer; The second determination unit is further configured to: if the correlation exists, determine whether the mean value of the ESFQD value of the epitaxial wafer is negative and is less than a set second mean value threshold; The determining unit is further configured to: if the correlation exists, when the mean value of the ESFQD value of the epitaxial wafer is negative and less than a set second mean value threshold, determine an improvement means for increasing the thickness of the edge epitaxial layer; The epitaxial execution unit is configured to improve the epitaxial process parameters of the epitaxial wafer based on the determined improvement means, and then perform epitaxial growth on the polished wafer to be epitaxially grown according to the improved epitaxial process parameters.

9. An epitaxial wafer manufacturing device, characterized in that: The epitaxial wafer manufacturing device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the epitaxial wafer manufacturing method according to any one of claims 1 to 7.

10. An epitaxial wafer, characterized in that: The epitaxial wafer is manufactured by the method for manufacturing an epitaxial wafer according to any one of claims 1 to 7, and the ESFQD value of the epitaxial wafer is in the range of [-10, -3], and the SFQR of the epitaxial wafer is max Less than or equal to 15.

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