Interconnection structure of wafer and manufacturing method thereof
By using metal conductors in the interconnection structure of the wafer and filling organic polymer materials, the problems of poor conductivity and low thermal matching are solved, and a high-density and high-performance vertical interconnection circuit is realized, with simple processes and excellent electrical properties.
Patent Information
- Application Number
- CN202411289623.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-17
AI Technical Summary
When manufacturing high-density and high-performance vertical interconnect circuits, the prior art faces the problems of poor conductivity and low thermal matching, which makes it impossible to meet the demands of 3D ICs for high-integration and high-speed signal transmission.
Metal is used as the interconnecting wire, and a first groove and a second groove are opened at both ends thereof, and organic polymer materials such as benzocyclobutene (BCB) are filled to improve electrical conductivity and reduce thermal stress.
It realizes the improvement of conductivity, thermal matching and thermal stress buffering, simplifies the production process, reduces stress, and has a short interconnection delay time and excellent electrical performance.
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Figure CN119153441A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of microelectronic manufacturing, and in particular to an interconnection structure of a wafer and a manufacturing method thereof. Background Art
[0002] Moore's Law has always been the law guiding the development of the semiconductor industry, but in today's era, Moore's Law has been given a new definition. The International Semiconductor Development Blueprint proposes a 3D IC technology solution to advance to the post-Moore era, improving chip performance and integration through vertical interconnection between wafers.
[0003] Through Silicon Via (TSV) is a three-dimensional interconnection technology between heterogeneous multi-chips, which can achieve high-speed and flexible signal transmission between chips. It is regarded as an important enabling technology for advanced packaging. With the continuous evolution of three-dimensional integration technology, many vertical interconnection technologies have been developed, such as TGV and TMV. The core idea is to solve the problem of vertical interconnection between wafers.
[0004] The manufacturing of vertical interconnected wafers, thermal matching between materials, and thermal stress are the problems that need to be solved urgently in today's 3D ICs. Today's universities and research institutions have made a series of attempts, such as filling metal tungsten, but tungsten has poor conductivity and cannot solve the power consumption problem of high-density interconnected circuits. There is also a method of filling conductive polysilicon to manufacture vertical interconnected circuits. The advantage of conductive polysilicon is that the manufacturing process is simple and does not require the deposition of sidewall seed layers. In addition, the vertical interconnected structure manufactured by this method does not have a thermal matching problem with the substrate, and the stress is small. However, the major problem faced is the poor conductivity of polysilicon, so the above attempts are not suitable for the manufacture of high-density, high-performance vertical interconnected circuits.
[0005] There are two problems that need to be solved by current technology: the first is to improve conductivity and reduce parasitic capacitance; the second is to improve the thermal matching between the filling material and the base material and reduce stress. As mentioned above, if the vertical interconnection circuit is manufactured by filling conductive polysilicon, the advantage of conductive polysilicon is that the manufacturing process is simple, there is no need to deposit a sidewall seed layer, and the vertical interconnection structure manufactured by this method does not have a thermal matching problem with the base, and the stress is small, but the major problem is that the conductivity of polysilicon is poor, so the above attempts are not suitable for the manufacture of high-density, high-performance vertical interconnection circuits. Filling metal tungsten also faces the problem of poor conductivity. Although the performance of filling metal tungsten is much better than that of filling conductive polycrystalline, it still cannot meet the existing 3D IC's requirements for high integration and high performance. Summary of the invention
[0006] The purpose of the present invention is to provide an interconnection structure of a wafer and a manufacturing method thereof. The present application uses metal as an interconnection wire for vertical interconnection, which solves the problem of poor conductivity. At the same time, a first groove and a second groove are opened at the two ends of the interconnection wire, and organic polymer materials are filled in the first groove and the second groove, which solves the problems of thermal matching and thermal stress.
[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions:
[0008] One aspect of an embodiment of the present invention provides an interconnection structure of a wafer, the interconnection structure comprising: a substrate, the substrate being provided with an interconnection through hole connecting a first side and a second side of the substrate, the two ends of the interconnection through hole being respectively provided with a first groove and a second groove having a diameter larger than the interconnection through hole; an interconnection wire, the interconnection wire being arranged in the interconnection through hole; the first groove being filled with a first organic polymer material layer, and the second groove being filled with a second organic polymer material layer.
[0009] In some embodiments, the interconnection structure also includes a third organic polymer material layer disposed on the first side of the substrate and / or a fourth organic polymer material layer disposed on the second side of the substrate, and both ends of the interconnection wire pass through the third organic polymer material layer and / or the fourth organic polymer material layer.
[0010] In some embodiments, the first organic polymer material layer, the second organic polymer material layer, the third organic polymer material layer and the fourth organic polymer material layer are all made of benzocyclobutene.
[0011] In some embodiments, the diameters of the first groove and the second groove are the same, and the ratio of the diameter of the first groove or the second groove to the diameter of the interconnecting through hole is within a first range.
[0012] In some embodiments, the first range value is 3-5.
[0013] In some embodiments, the ratio of the depth to the width of the interconnecting through hole is within a second range of values.
[0014] In some embodiments, the second range value is 5-15.
[0015] One aspect of an embodiment of the present invention provides a method for manufacturing an interconnection structure of a wafer, and the manufacturing method is applied to the interconnection structure as described above, and the manufacturing method includes: etching a first groove on a first side of a substrate; spin-coating an organic polymer material into the first groove and the first side of the substrate, and performing a curing treatment; etching an interconnection hole in the middle of the first groove, electroplating an interconnection wire into the interconnection hole, and grinding and thinning the second side of the substrate to expose the end of the interconnection wire; etching a second groove around the end of the interconnection wire on the second side of the substrate; spin-coating an organic polymer material into the second groove and the second side of the substrate, and performing a curing treatment; grinding and thinning the second side of the substrate to expose the end of the interconnection wire.
[0016] In some embodiments, in etching an interconnect hole groove in the middle of the first groove, the method also includes: coating a photoresist on the organic polymer material on the first side of the substrate, and patterning according to the position and shape of the interconnect through hole; etching the organic polymer material in the middle of the first groove, removing the photoresist to obtain a substrate pre-groove; etching the substrate through the substrate pre-groove to obtain an interconnect hole groove.
[0017] In some embodiments, during the electroplating of the interconnection wire into the interconnection hole groove, and grinding and thinning the second side of the substrate to expose the end of the interconnection wire, the method further includes: depositing a dielectric layer in the interconnection hole groove by a PECVD process; sequentially depositing a barrier layer and a metal seed layer on the dielectric layer by an ALD process; electroplating a filling metal in the interconnection hole groove, and flattening it to obtain the interconnection wire; grinding and thinning the second side of the substrate, and when the second side of the substrate exposes the end of the interconnection wire, continuing to grind to a preset depth.
[0018] According to an embodiment of the present invention, a wafer interconnection structure and a manufacturing method thereof have at least the following beneficial effects: the present application uses metal as an interconnection wire for vertical interconnection, which solves the problem of poor conductivity. At the same time, a first groove and a second groove are opened at the two ends of the interconnection wire, and benzocyclobutene (BCB) is filled in the first groove and the second groove. Benzocyclobutene (BCB) can be used for heat dissipation and can also provide a buffer for thermal stress, solving the problem of thermal matching and thermal stress. The vertically interconnected wafer realized by the present application has the characteristics of simple production process, low stress, excellent electrical performance and short interconnection delay time.
[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 is a schematic cross-sectional structural diagram of an interconnect structure of a wafer according to an embodiment;
[0022] Figure 2 A flow chart of a method for manufacturing a portion of an interconnect structure of a wafer according to an embodiment;
[0023] Figure 3 The flowchart is another part of the method for manufacturing the interconnection structure of the wafer according to the embodiment.
[0024] The reference numerals are described as follows: 1. substrate; 2. first groove; 3. second groove; 4. interconnection wire; 5. first organic polymer material layer; 6. second organic polymer material layer; 7. third organic polymer material layer; 8. fourth organic polymer material layer. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0026] In the description of the present invention, it is necessary to understand that the orientations or positional relationships indicated by terms such as “middle”, “upper”, “lower”, “top”, “bottom”, “inside” and “outside” are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0027] The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0029] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.
[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.
[0031] The interconnect structure of the wafer of the embodiment of the present application is briefly described below:
[0032] According to some embodiments, Figure 1 As shown, the present application provides an interconnection structure of a wafer, the interconnection structure comprising:
[0033] A substrate 1, wherein the substrate 1 is provided with an interconnection through hole connecting the first side and the second side of the substrate 1, and two ends of the interconnection through hole are respectively provided with a first groove 2 and a second groove 3 having a diameter larger than the interconnection through hole;
[0034] Interconnection wire 4, interconnection wire 4 is arranged in the interconnection through hole;
[0035] The first groove 2 is filled with a first organic polymer material layer 5 , and the second groove 3 is filled with a second organic polymer material layer 6 .
[0036] Specifically, the substrate 1 may be a glass substrate or a high-resistance silicon substrate, etc., which is not limited in this application. The substrate 1 is etched with an interconnection through hole extending from the top to the bottom. A first groove 2 is provided from the upper end to the top of the interconnection through hole, and a second groove 3 is provided from the lower end to the bottom of the interconnection through hole. In some embodiments, the interconnection through hole is a circular through hole, and the first groove 2 and the second groove 3 are both circular grooves, and the first groove 2 and the second groove 3 coincide with the center of the circle of the interconnection through hole. The interconnection wire 4 is arranged in the interconnection through hole, and then the first organic polymer material layer 5 is filled in the first groove 2, and the second organic polymer material layer 6 is filled in the second groove 3.
[0037] The present application uses metal as the interconnection wire 4 for vertical interconnection, solving the problem of poor conductivity. At the same time, the first groove 2 and the second groove 3 are opened at the two ends of the interconnection wire 4, and the organic polymer material is filled in the first groove 2 and the second groove 3. The organic polymer material can be used for heat dissipation and can also provide a buffer for thermal stress, solving the problem of thermal matching and thermal stress. The vertically interconnected wafer realized by the present application has the characteristics of simple structure, low stress, excellent electrical performance and short interconnection delay time.
[0038] The following is combined with the appendix of this manual Figures 1 to 3 , the interconnection structure of the wafer of the present application is further elaborated in detail.
[0039] According to some embodiments, Figure 1 As shown and Figure 3 As shown in n, the interconnection structure also includes a third organic polymer material layer 7 arranged on the first side (top) of the substrate 1 and / or a fourth organic polymer material layer 8 arranged on the second side (bottom) of the substrate 1, and both ends of the interconnection wire 4 pass through the third organic polymer material layer 7 and / or the fourth organic polymer material layer 8 for electrical connection with the outside world.
[0040] In some embodiments, the thickness of the third organic polymer material layer 7 is 2 to 4 times the depth of the first groove 2 .
[0041] Specifically, in the first embodiment, the third organic polymer material layer 7 is arranged on the first side (top) of the substrate 1, the fourth organic polymer material layer 8 is not arranged on the second side (bottom) of the substrate 1, and the interconnection wire 4 passes through the third organic polymer material layer 7; in the second embodiment, the third organic polymer material layer 7 is arranged on the first side (top) of the substrate 1, and the fourth organic polymer material layer 8 is arranged on the second side (bottom) of the substrate 1, and both ends of the interconnection wire 4 pass through the third organic polymer material layer 7 and the fourth organic polymer material layer 8; in the third embodiment, the third organic polymer material layer 7 is not arranged on the first side (top) of the substrate 1, and the fourth organic polymer material layer 8 is arranged on the second side (bottom) of the substrate 1, and the interconnection wire 4 passes through the fourth organic polymer material layer 8.
[0042] In some preferred embodiments, the first organic polymer material layer 5 , the second organic polymer material layer 6 , the third organic polymer material layer 7 and the fourth organic polymer material layer 8 are all made of benzocyclobutene (BCB).
[0043] According to some embodiments, the diameters of the first groove 2 and the second groove 3 are the same, and the ratio of the diameter of the first groove 2 or the second groove 3 to the diameter of the interconnecting through hole is within a first range.
[0044] The first range value can be set according to actual needs. In some preferred embodiments, the first range value is 3 to 5.
[0045] According to some embodiments, a ratio of a depth to a width of the interconnect via is within a second range of values.
[0046] The second range value can be set according to actual needs. In some preferred embodiments, the second range value is 5 to 15.
[0047] The following is an explanation of the method for manufacturing the interconnect structure of the wafer according to the embodiment of the present application:
[0048] According to some embodiments, Figures 2 to 3 As shown, the present application provides a method for manufacturing an interconnection structure of a wafer, the manufacturing method is applied to the interconnection structure as described above, and the manufacturing method includes:
[0049] Step 101, such as Figure 2 As shown in step b in FIG. 1 , a first groove 2 is etched on the first side (top) of the substrate 1 .
[0050] Step 102, such as Figure 2 As shown in step c, the organic polymer material is spin-coated into the first groove 2 and the first side (top) of the substrate 1, and then cured.
[0051] Step 103, as Figure 2 Step d in Figure 3 As shown in step j, an interconnect hole is etched in the middle of the first groove 2, an interconnect wire 4 is electroplated into the interconnect hole, and the second side (bottom) of the substrate 1 is ground and thinned to expose the end of the interconnect wire 4.
[0052] Step 104, such as Figure 3 As shown in step k to step m in FIG. 1 , a second groove 3 is etched around the end of the interconnection wire 4 on the second side (bottom) of the substrate 1 .
[0053] Step 105, such as Figure 3 As shown in step n, the organic polymer material is spin-coated into the second groove 3 and the second side (bottom) of the substrate 1, and then cured.
[0054] Step 106, such as Figure 3 As shown in step o in FIG. 1 , the second side (bottom) of the substrate 1 is ground and thinned until the end of the interconnection wire 4 is exposed.
[0055] Specifically, in step 101, the method specifically includes: Figure 2 As shown in step a of FIG. 1 , a photoresist is coated on the first side (top) of the substrate 1, and patterning is performed according to the position and shape of the first groove 2, and then the first groove 2 is etched on the first side (top) of the substrate 1, and then the photoresist is removed to obtain Figure 2 Step b in .
[0056] Further, in step 104, the method specifically includes: Figure 3 As shown in step k in FIG. 1 , a photoresist is coated on the second side (bottom) of the substrate 1 and patterned according to the position and shape of the second groove 3, as shown in FIG. Figure 3 As shown in step 1, a second groove 3 is etched on the second side (bottom) of the substrate 1; after etching, the photoresist is removed to obtain Figure 3 The m steps in .
[0057] The diameters of the first groove 2 and the second groove 3 are the same, and the ratio of the diameter of the first groove 2 or the second groove 3 to the diameter of the interconnection through hole is 3 to 5. The etching depth of the first groove 2 and the second groove 3 is 5 to 30 μm.
[0058] According to some embodiments, in step 103, an interconnection hole groove is etched in the middle of the first groove 2, and the method specifically includes:
[0059] Step 1031, as Figure 2 As shown in step d in the figure, a photoresist is coated on the organic polymer material on the first side (top) of the substrate 1, and patterning is performed according to the position and shape of the interconnection through hole.
[0060] Step 1032, as Figure 2As shown in step e to step f, the organic polymer material in the middle of the first groove 2 is etched, and the etching is stopped when the substrate 1 is reached, and then the photoresist is removed to obtain a substrate pre-groove.
[0061] Step 1033, as Figure 2 As shown in step g in FIG. 1 , the substrate 1 is etched by the ICP process through the substrate pre-grooving to obtain interconnection holes. The minimum diameter of the interconnection holes is 20 μm.
[0062] According to some embodiments, in step 103, the interconnection wire 4 is electroplated into the interconnection hole groove, and the second side (bottom) of the substrate 1 is ground and thinned to expose the end of the interconnection wire 4, and the method specifically includes:
[0063] Step 1034, as Figure 2 As shown in step h, a dielectric layer is deposited in the interconnected holes by a PECVD process (about 200°C); because benzocyclobutene (BCB) cannot withstand the high temperature of the furnace tube above 900°C, and the film formed by the PECVD process has good commonality, improves the deep hole filling ability, and can repair the side wall etching defects.
[0064] Step 1035, as Figure 2 As shown in step h, a barrier layer and a metal seed layer are sequentially deposited on the dielectric layer by an ALD process; because ALD has stronger commonality than PVD, it is more suitable for the deposition of a seed layer on the sidewall of a deep hole with a high aspect ratio.
[0065] Step 1036, as Figure 3 As shown in step i, electroplating fill metal in the interconnection hole groove, the filling height is slightly higher than the interconnection hole groove depth by 5%, and then flattening treatment is performed to obtain the interconnection wire 4;
[0066] Step 1037, as Figure 3 As shown in step j, the second side (bottom) of the substrate 1 is ground and thinned, and when the second side (bottom) of the substrate 1 exposes the end of the interconnection wire 4, the grinding is continued to the preset depth. To obtain the final interconnection wire 4 and interconnection through hole. Among them, the preset depth can be set according to actual needs. In some preferred embodiments, the preset depth is 5% of the depth of the interconnection hole groove.
[0067] The present application uses metal as the interconnection wire 4 for vertical interconnection, solving the problem of poor conductivity. At the same time, a first groove 2 and a second groove 3 are opened at the two ends of the interconnection wire 4, and benzocyclobutene (BCB) is filled in the first groove 2 and the second groove 3. Benzocyclobutene (BCB) can be used for heat dissipation and can also provide a buffer for thermal stress, solving the problem of thermal matching and thermal stress. The vertically interconnected wafer realized by the present application has the characteristics of simple production process, low stress, excellent electrical performance and short interconnection delay time.
[0068] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.
[0069] Although the present disclosure has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be implemented in a variety of forms without departing from the spirit or essence of the present application, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be widely interpreted within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. A wafer interconnection structure, characterized in that: The interconnect structure comprises: A substrate, wherein the substrate is provided with an interconnection through hole connecting a first side and a second side of the substrate, and two ends of the interconnection through hole are respectively provided with a first groove and a second groove having a diameter larger than that of the interconnection through hole; An interconnection wire, wherein the interconnection wire is disposed in the interconnection through hole; The first groove is filled with a first organic polymer material layer, and the second groove is filled with a second organic polymer material layer.
2. The interconnection structure according to claim 1, characterized in that: The interconnect structure also includes a third organic polymer material layer disposed on the first side of the substrate and / or a fourth organic polymer material layer disposed on the second side of the substrate, and both ends of the interconnect wire penetrate the third organic polymer material layer and / or the fourth organic polymer material layer.
3. The interconnection structure according to claim 2, characterized in that: The first organic polymer material layer, the second organic polymer material layer, the third organic polymer material layer and the fourth organic polymer material layer are all made of benzocyclobutene.
4. The interconnect structure according to claim 1, characterized in that: The diameters of the first groove and the second groove are the same, and the ratio of the diameter of the first groove or the second groove to the diameter of the interconnection through hole is within a first range.
5. The interconnection structure according to claim 4, characterized in that: The first range value is 3-5.
6. The interconnect structure according to claim 1, characterized in that: The ratio of the depth to the width of the interconnection through hole is within a second range of values.
7. The interconnection structure according to claim 6, characterized in that: The second range value is 5-15.
8. A method for manufacturing an interconnection structure of a wafer, characterized in that: The manufacturing method is applied to the interconnect structure according to any one of claims 1 to 7, and the manufacturing method comprises: etching a first recess in a first side of the substrate; Spin coating an organic polymer material into the first groove and the first side of the substrate, and performing a curing process; Etching an interconnection hole groove in the middle of the first groove, electroplating an interconnection wire into the interconnection hole groove, and grinding and thinning the second side of the substrate to expose the end of the interconnection wire; Etching a second groove around the end of the interconnect wire on the second side of the substrate; Spin coating an organic polymer material into the second groove and the second side of the substrate, and performing a curing process; The second side of the substrate is ground and thinned until the end of the interconnection wire is exposed.
9. The manufacturing method according to claim 8, characterized in that: Etching an interconnection hole groove in the middle of the first groove, the method further comprises: Coating photoresist on the organic polymer material on the first side of the substrate, and performing patterning according to the position and shape of the interconnection through hole; Etching the organic polymer material in the middle of the first groove to remove the photoresist to obtain a substrate pre-groove; The substrate is etched through the substrate pre-grooving to obtain interconnected holes and grooves.
10. The manufacturing method according to claim 8, characterized in that: In the electroplating of the interconnection wire into the interconnection hole groove, and grinding and thinning the second side of the substrate to expose the end of the interconnection wire, the method further includes: Depositing a dielectric layer in the interconnected hole grooves by a PECVD process; Depositing a barrier layer and a metal seed layer in sequence on the dielectric layer by an ALD process; Electroplating filling metal in the interconnection hole groove, and flattening the hole groove to obtain an interconnection wire; The second side of the substrate is ground and thinned, and when the second side of the substrate exposes the end of the interconnection wire, the grinding is continued to a preset depth.