Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first device region and a second device region which are adjacent, and forming a channel structure on the substrate; forming an occupying layer protruding from the substrate between the adjacent channel structures; forming a first work function layer which is filled between the adjacent channel structures and the opposite side walls of the placeholder layer and covers the tops of the channel structures and the placeholder layer; forming a mask material layer covering the first work function layer; removing the mask material layer in the first device region, and reserving the mask material layer in the second device region as a mask layer; taking the mask layer as a mask, and removing the first work function layer located at the tops of the channel structure and the placeholder layer in the first device region; removing the mask layer; forming a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device region and the top of the first work function layer in the second device region; and forming a gate electrode layer covering the second work function layer. The working stability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] MOS (Metal-Oxide-Semiconductor) transistor is one of the most important components in modern integrated circuits. The basic structure of MOS transistor includes: semiconductor substrate; gate dielectric layer located on the surface of semiconductor substrate and gate electrode layer located on the surface of gate dielectric layer; source and drain doping regions located in the semiconductor substrate on both sides. MOS includes PMOS transistor and NMOS transistor.

[0003] In order to meet the switching speed requirements of different transistors in integrated circuit design, it is necessary to form transistors with multiple threshold voltages.

[0004] In order to reduce and adjust the threshold voltage of the PMOS transistor and the NMOS transistor, a corresponding work function layer is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. Among them, the work function layer of the PMOS transistor needs to have a higher work function, while the work function layer of the NMOS transistor needs to have a lower work function. In the PMOS transistor and the NMOS transistor, the materials of the work function layer are different to meet the needs of their respective work function adjustments. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the working stability of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention further provides a semiconductor structure, including: a substrate, including a first device region and a second device region adjacent to each other, the first device region being used to form a first device, the second device region being used to form a second device, and the first device and the second device being of different types; a channel structure protruding from the substrate; a placeholder layer protruding from the substrate and located between adjacent channel structures; a first work function layer filling between opposite side walls of adjacent channel structures and the placeholder layer, the first work function layer also covering the channel structure and the top of the placeholder layer in the second device region; a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device region, the second work function layer also covering the top of the first work function layer in the second device region; and a gate electrode layer covering the second work function layer.

[0007] Optionally, the placeholder layer is flush with the top of the channel structure.

[0008] Optionally, a distance between the placeholder layer and an adjacent channel structure is 1 nm to 3 nm.

[0009] Optionally, the material of the placeholder layer includes low-k dielectric material (low-k dielectric material refers to dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric material (high-k dielectric material refers to material with k>5.0), silicon or silicon nitride.

[0010] Optionally, the distances between adjacent placeholder layers and channel structures are equal.

[0011] Optionally, the first device region is used to form an NMOS region, and the second device region is used to form a PMOS region; the material of the first work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; the material of the second work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising an adjacent first device region and a second device region, a channel structure protruding from the substrate is formed on the substrate, the first device region is used to form a first device, the second device region is used to form a second device, and the first device and the second device are of different types; forming a placeholder layer protruding from the substrate between adjacent channel structures; forming a first work function layer filling between the relative side walls of the adjacent channel structures and the placeholder layer and covering the channel structures and the top of the placeholder layer; forming a mask material layer covering the first work function layer; removing the mask material layer in the first device region and retaining the mask material layer in the second device region as a mask layer; using the mask layer as a mask, removing the first work function layer located at the top of the channel structure and the placeholder layer in the first device region; removing the mask layer; forming a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device region, and the top of the first work function layer in the second device region; forming a gate electrode layer covering the second work function layer.

[0013] Optionally, before forming the placeholder layer, the formation method also includes: forming a sidewall material layer covering the top surface of the substrate, the sidewalls and the top surface of the channel structure; removing the sidewall material layer located on the top surface of the substrate and the top surface of the channel structure, and retaining the sidewall material layer located on the sidewall of the channel structure as a sidewall; in the step of forming the placeholder layer, forming the placeholder layer between the sidewalls of the opposite sidewalls of adjacent channel structures; before forming the first work function layer, it also includes: removing the sidewall.

[0014] Optionally, an atomic layer deposition process is used to form the sidewall material layer.

[0015] Optionally, in the step of forming a spacer material layer covering the top surface of the substrate, the sidewalls and the top surface of the channel structure, the thickness of the spacer material layer is 1 nm to 3 nm.

[0016] Optionally, the step of forming a placeholder layer includes: forming a placeholder material layer that fills the space between the sidewalls of opposite sidewalls of adjacent channel structures and covers the channel structure and the sidewalls; removing the placeholder material layer above the top of the channel structure, and retaining the placeholder material layer between the sidewalls of opposite sidewalls of adjacent channel structures as the placeholder layer.

[0017] Optionally, an atomic layer deposition process is used to form the placeholder material layer.

[0018] Optionally, after forming the placeholder layer and before forming the first work function, the formation method also includes: forming a dummy gate structure spanning and covering the top of the placeholder layer, the top of the sidewall and the top of the channel structure; forming a dielectric layer covering the dummy gate structure; removing the dummy gate structure to form a gate opening in the dielectric layer; in the step of forming a gate electrode layer, forming a gate electrode layer in the gate opening.

[0019] Optionally, in the step of removing the sidewall spacer, the exposed sidewall spacer is removed through the gate opening.

[0020] Optionally, in the step of forming a placeholder layer, the material of the placeholder layer includes low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric material (high-k dielectric material refers to a material with k>5.0), silicon or silicon nitride.

[0021] Optionally, in the step of providing a substrate, the first device region is used to form an NMOS region, and the second device region is used to form a PMOS region; in the step of forming a first work function layer, the material of the first work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; in the step of forming a second work function layer, the material of the second work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] In the semiconductor structure provided by the embodiment of the present invention, the placeholder layer protrudes from the substrate and is located between adjacent channel structures, the first work function layer is filled between the opposite side walls of the adjacent channel structure and the placeholder layer, the first work function layer also covers the channel structure and the top of the placeholder layer in the second device area, the second work function layer covers the channel structure, the placeholder layer and the top of the first work function layer in the first device area, and the second work function layer also covers the top of the first work function layer in the second device area; the embodiment of the present invention needs to form the first work function layer in the first device area and the first work function layer and the second work function layer in the second device area, so it is necessary to first form the first work function layer filled between the opposite side walls of the adjacent channel structure and the placeholder layer and cover the channel structure and the top of the placeholder layer, then form a mask material layer covering the first work function layer, then remove the mask material layer in the first device area, retain the mask material layer located in the second device area as a mask layer, and finally use the mask layer as a mask to remove the first work function layer located in the channel structure and the top of the placeholder layer in the first device area. Therefore, the embodiment of the present invention forms a protruding substrate between adjacent channel structures. The placeholder layer enables the first work function layer to fill the space between the adjacent channel structure and the relative side walls of the placeholder layer, and accordingly makes the top surface flatness of the first work function layer better. In the process of forming the mask material layer covering the first work function layer, the probability of the mask material layer being recessed between the adjacent channel structures of the first device region is reduced, and the difficulty in removing the first work function layer covered by the mask material layer due to the recess of the mask material layer is correspondingly reduced, and the side walls of the channel structure remaining in the first device region are reduced, resulting in the second work function layer covering the remaining first work function layer when the side walls of the channel structure in the first device region cover the second work function layer, causing the probability of the work function layer film layer being unstable in the first device region, thereby reducing the probability of the device threshold voltage being unstable due to the instability of the work function layer film layer in the first device region, and improving the working stability of the semiconductor structure. At the same time, in the embodiment of the present invention, the side walls of the channel structures in the first device region and the second device region are only covered by the first work function layer, and the threshold voltages of the channel structures in the first device region and the second device region can be respectively controlled according to the work function layer on the top of the channel structure, so as to realize different functions of the first device and the second device.

[0024] In the formation method provided by the embodiment of the present invention, a placeholder layer protruding from the substrate is formed between adjacent channel structures, a first work function layer filling between the opposite side walls of the adjacent channel structure and the placeholder layer and covering the channel structure and the top of the placeholder layer is formed, a mask material layer covering the first work function layer is formed, the mask material layer in the first device area is removed, the mask material layer in the second device area is retained as a mask layer, the first work function layer in the first device area between the channel structure and the top of the placeholder layer is removed using the mask layer as a mask, the mask layer is removed, and the mask layer is removed to form a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device area, and the top of the first work function layer in the second device area; in the embodiment of the present invention, by forming a placeholder layer protruding from the substrate between adjacent channel structures, the first work function layer can fill between the opposite side walls of the adjacent channel structure and the placeholder layer, and accordingly the top surface flatness of the first work function layer is better, then in the formation In the process of forming a mask material layer covering the first work function layer, the probability of the mask material layer being recessed between adjacent channel structures in the first device region is reduced, and the difficulty in removing the first work function layer covered by the mask material layer due to the recess of the mask material layer is correspondingly reduced, resulting in the second work function layer covering the remaining first work function layer when the side wall of the channel structure in the first device region covers the second work function layer, causing the probability of the work function layer film layer in the first device region being unstable, thereby reducing the probability of the device threshold voltage being unstable due to the unstable work function layer film layer in the first device region, and improving the working stability of the semiconductor structure. At the same time, in the embodiment of the present invention, the side walls of the channel structures in the first device region and the second device region are only covered by the first work function layer, and the threshold voltages of the channel structures in the first device region and the second device region can be respectively controlled according to the work function layer on the top of the channel structure, so as to realize different functions of the first device and the second device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 7 It is a method of forming a semiconductor structure;

[0026] Figure 8 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0027] Figures 9 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0028] At present, it is difficult to ensure the working stability of semiconductor structures. The reasons why it is difficult to ensure the working stability are analyzed in combination with a method for forming a semiconductor structure.

[0029] refer to Figure 1 , Figure 1 (b) Figure 1(a) A cross-sectional view along the AA direction, providing a substrate 10, including a first device region 10a and a second device region 10b adjacent to each other, a channel structure 11 protruding from the substrate 10 is formed on the substrate 10, and a dielectric layer 50 is also formed on the substrate 10, and a gate opening 41 exposing a plurality of channel structures 11 is formed in the dielectric layer 50.

[0030] refer to Figure 2 , Figure 2 (b) Figure 2 (a) A cross-sectional view along the AA direction, wherein a first work function layer 61 is formed to cover the top and sidewall of the channel structure 11 and the top of the substrate 10 .

[0031] refer to Figure 3 , Figure 3 (b) Figure 3 (a) is a cross-sectional view along the AA direction, in which a mask layer 70 is formed to cover the first work function layer 61 .

[0032] refer to Figure 4 , Figure 4 (b) Figure 4 (a) is a cross-sectional view along the AA direction, in which the mask layer 70 of the first device region 10a is removed and the mask layer 70 of the second device region 10b is retained.

[0033] Since the gap between the first work function layers 61 on the opposite sidewalls of adjacent channel structures 11 is small, and the mask layer 61 includes a bottom anti-reflective coating (BARC) material, the BARC material is difficult to remove completely. Figure 4 Indicated by the dotted circle in (b).

[0034] refer to Figure 5 , Figure 5 (b) Figure 5 (a) is a cross-sectional view along the AA direction, in which the first work function layer 61 exposed in the first device region 10a is removed.

[0035] Since part of the mask layer 70 remains between adjacent channel structures 11 and has not been completely removed, the first work function layer 61 covered by the remaining mask layer 70 has not been completely removed. Figure 5 Indicated by the dotted circle in (b).

[0036] refer to Figure 6 , Figure 6 (b) Figure 6 (a) is a cross-sectional view along the AA direction, wherein the mask layer 70 of the second device region 10b is removed; and a second work function layer 62 covering the channel structure 11 of the first device region 10a and the first work function layer 61 of the second device region 10b is formed.

[0037] Since the first work function layer 61 remains on the sidewall of the channel structure 11 in the first device region 10a, the formed second work function layer 62 covers the remaining first work function layer 61. Figure 6 Indicated by the dotted circle in (b).

[0038] refer to Figure 7 , Figure 7 (b) Figure 7 (a) A cross-sectional view along the AA direction, in which the gate electrode layer 42 is formed to cover the second work function layer 62 .

[0039] Since the second work function layer 62 covers the remaining first work function layer 61 in the first device region 10a, the coverage of the work function layer on the sidewall of the channel structure 11 in the first device region 10a is uneven (e.g. Figure 7 (b) as indicated by the dotted circle), which results in an unstable threshold voltage of the semiconductor structure, and thus makes it difficult to ensure the working stability of the semiconductor structure.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including adjacent first and second device regions, a channel structure protruding from the substrate is formed on the substrate, the first device region is used to form a first device, the second device region is used to form a second device, and the types of the first device and the second device are different; forming a placeholder layer protruding from the substrate between adjacent channel structures; forming a first work function layer filling between the opposite side walls of the adjacent channel structures and the placeholder layer and covering the channel structure and the top of the placeholder layer; forming a mask material layer covering the first work function layer; removing the mask material layer in the first device region, and retaining the mask material layer located in the second device region as a mask layer; using the mask layer as a mask, removing the first work function layer located in the channel structure and the top of the placeholder layer in the first device region; removing the mask layer; forming a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device region, and the top of the first work function layer in the second device region; forming a gate electrode layer covering the second work function layer.

[0041] In the embodiment of the present invention, a placeholder layer protruding from the substrate is formed between adjacent channel structures, so that the first work function layer can fill the space between the adjacent channel structures and the relative sidewalls of the placeholder layer, and accordingly the top surface flatness of the first work function layer is better. In the process of forming a mask material layer covering the first work function layer, the probability of the mask material layer being recessed between the adjacent channel structures in the first device region is reduced, and accordingly the difficulty in removing the first work function layer covered by the mask material layer due to the recess of the mask material layer is reduced, and the sidewall of the channel structure in the first device region is left untouched. As a result, when the sidewall of the channel structure in the first device region is covered with the second work function layer, the second work function layer covers the remaining first work function layer, causing the probability of the work function layer film layer being unstable in the first device region, thereby reducing the probability of the device threshold voltage being unstable due to the unstable work function layer film layer in the first device region, and improving the working stability of the semiconductor structure. At the same time, in the embodiment of the present invention, the sidewalls of the channel structures in the first device region and the second device region are both covered with only the first work function layer, and the threshold voltages of the channel structures in the first device region and the second device region can be respectively controlled according to the work function layer on the top of the channel structure, so as to realize different functions of the first device and the second device.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figure 8 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0044] refer to Figure 8 , Figure 8 (b) Figure 8 (a) A cross-sectional view along the AA direction, the semiconductor structure comprises: a substrate 100, comprising a first device region 100a and a second device region 100b adjacent to each other, the first device region 100a is used to form a first device, the second device region 100b is used to form a second device, and the first device and the second device are of different types; a channel structure 110 protruding from the substrate 100; a placeholder layer 300 protruding from the substrate 100 and located between adjacent channel structures 110; a first work function layer 610 filled in the adjacent channel structures 110; Between the opposite side walls of the adjacent channel structure 110 and the placeholder layer 300, the first work function layer 610 also covers the channel structure 110 and the top of the placeholder layer 300 in the second device region 100b; the second work function layer 620 covers the channel structure 110, the placeholder layer 300 and the top of the first work function layer 610 in the first device region 100a, and the second work function layer 620 also covers the top of the first work function layer 610 in the second device region 100b; the gate electrode layer 420 covers the second work function layer 620.

[0045] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0046] The base 100 includes a substrate (not labeled) and an isolation layer (not labeled) located on the substrate. The isolation layer covers a portion of the sidewall of the channel structure 110 .

[0047] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0048] The isolation layer is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer is usually formed between an NMOS transistor and a PMOS transistor.

[0049] In this embodiment, the material of the isolation layer is an insulating material. As an example, the material of the isolation layer is silicon oxide.

[0050] In this embodiment, the substrate 100 includes a first device region 100 a and a second device region 100 b adjacent to each other. The first device region 100 a is used to form a first device, and the second device region 100 b is used to form a second device.

[0051] Specifically, in this embodiment, the first device region 100a is an NMOS region for forming an NMOS transistor, and the second device region 100b is a PMOS region for forming a PMOS transistor. In order to adapt to the different performance requirements of NMOS transistors and PMOS transistors, NMOS transistors and PMOS transistors use different work function layers.

[0052] The channel structure 110 is used to provide a channel for the semiconductor structure.

[0053] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel structure 110 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0054] It should be noted that, in this embodiment, the channel structure 110 and the substrate 100 are made of the same material. In other embodiments, the channel structure and the substrate may be made of different materials.

[0055] The placeholder layer 300 is used to occupy the space between adjacent channel structures 110 so that when the first work function layer 610 is formed, it can be filled between the adjacent placeholder layer 300 and the channel structure 110, so that the first work function layer 610 between the adjacent channel structures 110 will not be recessed, forming a relatively flat top surface.

[0056] Specifically, in this embodiment, it is necessary to form a first work function layer 610 in the first device area 100a and to form a first work function layer 610 and a second work function layer 620 in the second device area 100b. It is necessary to first form a first work function layer 610 that fills between the opposite side walls of the adjacent channel structure 110 and the place-occupying layer 300 and covers the top of the channel structure 110 and the place-occupying layer 300, and then form a mask material layer covering the first work function layer 610, and then remove the mask material layer of the first device area 100a, retain the mask material layer located in the second device area 100b as a mask layer, and finally use the mask layer as a mask to remove the first work function layer 610 located at the top of the channel structure 110 and the place-occupying layer 300 in the first device area 100a. Therefore, in this embodiment, by forming a place-occupying layer 300 protruding from the substrate 100 between the adjacent channel structures 110, the first work function layer 610 can fill the adjacent channel structures 110. Between the relative side walls of the channel structure 110 and the placeholder layer 300, the top surface flatness of the first work function layer 610 is correspondingly better. Therefore, in the process of forming the mask material layer covering the first work function layer 610, the probability of the mask material layer being recessed between the adjacent channel structures 110 in the first device area 100a is reduced, and the difficulty in removing the first work function layer 610 covered by the mask material layer due to the recess of the mask material layer is correspondingly reduced, and the first work function layer 610 remaining on the side wall of the channel structure 110 in the first device area 100a is reduced, resulting in that when the side wall of the channel structure 110 in the first device area 100a covers the second work function layer 620, the second work function layer 620 covers the remaining first work function layer 610, causing the probability of the work function layer film being unstable in the first device area 100a, thereby reducing the probability of the device threshold voltage being unstable due to the unstable work function layer film in the first device area 100a, and improving the working stability of the semiconductor structure.

[0057] In this embodiment, the placeholder layer 300 is flush with the top of the channel structure 110 .

[0058] The placeholder layer 300 is flush with the top of the channel structure 110 , which is beneficial to improving the top surface flatness of the placeholder layer 300 , the channel structure 110 and the first work function layer 610 in the first device region 100 a and providing a better process platform.

[0059] It should be noted that, in this embodiment, the distance between the placeholder layer 300 and the adjacent channel structure 110 should not be too large or too small. If the spacing between the placeholder layer 300 and the adjacent channel structure 110 is too large, when the first work function layer 610 is formed to fill between the adjacent channel structure 110 and the opposite sidewalls of the placeholder layer 300 and to cover the channel structure 110 and the top of the placeholder layer 300, it is easy to cause the first work function layer 610 between the placeholder layer 300 and the adjacent channel structure 110 to have a concave morphology, and when the second work function layer 620 is subsequently covered, it is easy to cause the work function layer film of the first device area 100a to be uneven, affecting the threshold voltage stability of the semiconductor structure; if the spacing between the placeholder layer 300 and the adjacent channel structure 110 is too small, it is easy to increase the process difficulty of the first work function layer 610 filling between the adjacent channel structure 110 and the opposite sidewalls of the placeholder layer 300, resulting in poor film quality of the first work function layer 610, thereby affecting the working performance of the semiconductor structure. For this reason, in this embodiment, the spacing between the placeholder layer 300 and the adjacent channel structure 110 is 1nm to 3nm.

[0060] It should also be noted that in the process of forming the semiconductor structure, a side wall covering the side wall of the channel structure 110 is first formed, and then a placeholder layer 300 is formed between adjacent side walls, so that the spacing between adjacent placeholder layers 300 and the channel structure 110 is equal. Accordingly, it is also beneficial to make the width of the first work function layer 610 filled between the relative side walls of the adjacent channel structure 110 and the placeholder layer 300 and covering the side wall of the channel structure 110 equal, which is beneficial to make the effect of the first work function layer 610 on the side wall of the channel structure 110 more uniform. Therefore, in this embodiment, the channel structure 110 of the first device area 100a and the second device area 100b can be controlled separately according to the work function layer at the top of the channel structure 110 to realize different functions of the first device and the second device.

[0061] In this embodiment, the material of the placeholder layer 300 includes low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric material (high-k dielectric material refers to a material with k>5.0), silicon or silicon nitride.

[0062] Low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric materials (high-k dielectric materials refer to materials with k>5.0), silicon or silicon nitride are commonly used materials in semiconductor structures and can have little impact on semiconductor structures.

[0063] The second work function layer 620 is used to adjust the threshold voltage of the first device.

[0064] In this embodiment, the first device is an NMOS transistor. For the NMOS transistor, the work function layer is an N-type work function layer. The material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC. Correspondingly, the material of the second work function layer 620 includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0065] The first work function layer 610 and the second work function layer 620 are used together to adjust the threshold voltage of the second device.

[0066] In this embodiment, the second device is a PMOS transistor. For the PMOS transistor, the work function layer is a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. Correspondingly, the material of the first work function layer 610 includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN.

[0067] It should be noted that, in this embodiment, the side walls of the channel structure 110 of the first device area 100a and the second device area 100b are only covered by the first work function layer 610. The threshold voltage of the channel structure 110 of the first device area 100a and the second device area 100b can be controlled respectively according to the work function layer on the top of the channel structure 110 to realize different functions of the first device and the second device.

[0068] The gate electrode layer 420 is used to electrically lead out the gate structure of the device.

[0069] In the present embodiment, the material of the gate electrode layer 420 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0070] Figures 9 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0071] refer to Fig. 9 , Fig. 9 (b) Fig. 9 (a) A cross-sectional view along the AA direction, providing a substrate 100, including adjacent first device regions 100a and second device regions 100b, a channel structure 110 protruding from the substrate 100 is formed on the substrate 100, the first device region 100a is used to form a first device, the second device region 100b is used to form a second device, and the first device and the second device are of different types.

[0072] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0073] The base 100 includes a substrate (not labeled) and an isolation layer (not labeled) located on the substrate. The isolation layer covers a portion of the sidewall of the channel structure 110 .

[0074] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0075] The isolation layer is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer is usually formed between an NMOS transistor and a PMOS transistor.

[0076] In this embodiment, the material of the isolation layer is an insulating material. As an example, the material of the isolation layer is silicon oxide.

[0077] In this embodiment, the substrate 100 includes a first device region 100 a and a second device region 100 b adjacent to each other. The first device region 100 a is used to form a first device, and the second device region 100 b is used to form a second device.

[0078] Specifically, in this embodiment, the first device region 100a is an NMOS region for forming an NMOS transistor, and the second device region 100b is a PMOS region for forming a PMOS transistor. In order to adapt to the different performance requirements of NMOS transistors and PMOS transistors, NMOS transistors and PMOS transistors use different work function layers.

[0079] The channel structure 110 is used to provide a channel for the semiconductor structure.

[0080] In this embodiment, the material of the channel structure 110 includes silicon, germanium, silicon germanium or III-V semiconductor materials. As an example, the material of the channel structure 110 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0081] It should be noted that, in this embodiment, the channel structure 110 and the substrate 100 are made of the same material. In other embodiments, the channel structure and the substrate may be made of different materials.

[0082] refer to Fig.10 , Fig.10 (b) Fig.10 (a) is a cross-sectional view along the AA direction. Before subsequently forming the placeholder layer, the forming method further includes: forming a spacer material layer 200 covering the top surface of the substrate 100 and the sidewalls and top surface of the channel structure 110 .

[0083] The spacer material layer 200 is used for forming spacers later.

[0084] In this embodiment, the spacer material layer 200 is formed by an atomic layer deposition process.

[0085] The sidewall material layer 200 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the sidewall material layer 200 can conformally cover the top surface of the substrate 100, the sidewall and top surface of the channel structure 110, and is conducive to making the thickness uniformity of the sidewall formed subsequently better.

[0086] It should be noted that, in the present embodiment, in the step of forming the spacer material layer 200 covering the top surface of the substrate 100 and the sidewalls and top surface of the channel structure 110 , the thickness of the spacer material layer 200 should not be too large or too small. Subsequently, a placeholder layer is formed between the side walls of the opposite side walls of adjacent channel structures 110. If the thickness of the sidewall material layer 200 is too large and the width of the corresponding sidewall formed subsequently is too large, the space between the adjacent sidewalls for forming the placeholder layer is too small, which easily increases the process difficulty of forming the placeholder layer. Moreover, the position of the sidewall is subsequently used to fill and form a first work function layer. If the width of the sidewall is too large, it is easy to cause the filled first work function layer to have a concave morphology. When the second work function layer is subsequently covered, it is easy to cause the work function layer film of the first device area 100a to be uneven, affecting the threshold voltage stability of the semiconductor structure; if the thickness of the sidewall material layer 200 is too small and the width of the corresponding sidewall formed subsequently is too small, then when the first work function layer is subsequently formed at the sidewall position, it is easy to increase the process difficulty of filling the first work function layer, resulting in poor film quality of the first work function layer, thereby affecting the working performance of the semiconductor structure. To this end, in the present embodiment, in the step of forming the spacer material layer 200 covering the top surface of the substrate 100 and the sidewalls and top surface of the channel structure 110 , the thickness of the spacer material layer 200 is 1 nm to 3 nm.

[0087] It should be noted that the thickness of the spacer material layer 200 is less than the minimum thickness of the first work function layer metal required at different Vt, so as to ensure that the thinnest part of the first work function layer metal can completely fill the gap after the spacer is removed.

[0088] In the present embodiment, in the step of forming a spacer material layer 200 covering the top surface of the substrate 100, the sidewalls and the top surface of the channel structure 110, the material of the spacer material layer 200 includes a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), silicon or silicon nitride, a high-k material, etc., and is different from the material of the placeholder layer.

[0089] It should be noted that the material of the spacer material layer 200 is selected to ensure a high selectivity ratio between the gate dielectric layer and the placeholder layer during the removal of the spacer material. Usually, the selectivity ratio needs to be greater than 50:1.

[0090] refer to Fig.11 , Fig.11 (b) Fig.11 (a) is a cross-sectional view along the AA direction, wherein the spacer material layer 200 located on the top surface of the substrate 100 and the top surface of the trench structure 110 is removed, and the spacer material layer 200 located on the side wall of the trench structure 110 is retained as the spacer 210.

[0091] The spacer 210 is used to occupy a space for the subsequent formation of a first work function layer, and is also used to provide a suitable space for the subsequent formation of a placeholder layer.

[0092] In this embodiment, a dry etching process is used to remove the spacer material layer 200 located on the top surface of the substrate 100 and the top surface of the channel structure 110 .

[0093] The dry etching process has the characteristic of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce damage to the substrate 100. At the same time, the dry etching process has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the sidewall 210.

[0094] Accordingly, in this embodiment, the material of the sidewall 210 includes low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), silicon or silicon nitride, high-k material, etc., and is different from the material of the placeholder layer.

[0095] refer to Fig.12 , Fig.12 (b) Fig.12 (a) is a cross-sectional view along the AA direction, in which a placeholder layer 300 protruding from the substrate 100 is formed between adjacent channel structures 110 .

[0096] The placeholder layer 300 is used to occupy the space between adjacent channel structures 110 so that when the first work function layer is formed, it can be filled between the adjacent placeholder layer 300 and the channel structure 110, so that the first work function layer between the adjacent channel structures 110 will not be recessed, forming a relatively flat top surface.

[0097] In this embodiment, a placeholder layer 300 protruding from the substrate 100 is formed between adjacent channel structures 110, so that the first work function layer 610 can fill between the adjacent channel structures 110 and the opposite side walls of the placeholder layer 300, and accordingly the top surface flatness of the first work function layer is better. In the process of forming a mask material layer covering the first work function layer, the probability of the mask material layer being recessed between the adjacent channel structures 110 in the first device area 100a is reduced, and accordingly the difficulty in removing the first work function layer covered by the mask material layer due to the recess of the mask material layer is reduced, and the first work function layer remaining on the side wall of the channel structure 110 in the first device area 100a is reduced, resulting in that when the side wall of the channel structure 110 in the first device area 100a covers the second work function layer, the second work function layer covers the remaining first work function layer, causing the probability of the work function layer film being unstable in the first device area 100a, thereby reducing the probability of the device threshold voltage being unstable due to the unstable work function layer film in the first device area 100a, and improving the working stability of the semiconductor structure.

[0098] Accordingly, in the present embodiment, in the step of forming the placeholder layer 300 , the placeholder layer 300 is formed between the spacers 210 on opposite sidewalls of adjacent channel structures 110 .

[0099] In this embodiment, in the step of forming a placeholder layer 300 protruding from the substrate 100 between adjacent channel structures 110 , the placeholder layer 300 is flush with the top of the channel structure 110 .

[0100] The placeholder layer 300 is flush with the top of the channel structure 110 , which is beneficial to subsequently improving the top surface flatness of the placeholder layer 300 , the channel structure 110 and the first work function layer in the first device region 100 a , and provides a better process platform.

[0101] In this embodiment, in the step of forming the placeholder layer 300, the material of the placeholder layer 300 includes a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), a high-k dielectric material (a high-k dielectric material refers to a material with k>5.0), silicon or silicon nitride.

[0102] Low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric materials (high-k dielectric materials refer to materials with k>5.0), silicon or silicon nitride are commonly used materials in semiconductor structures and can have little impact on semiconductor structures.

[0103] Specifically, in this embodiment, the step of forming the placeholder layer 300 includes: forming a placeholder material layer (not shown) filling between the spacers 210 of opposite sidewalls of adjacent channel structures 110 and covering the channel structures 110 and the spacers 210 .

[0104] The placeholder material layer is used to form the placeholder layer 300 .

[0105] In this embodiment, an atomic layer deposition process is used to form the placeholder material layer.

[0106] The atomic layer deposition process has good gap filling capability, which is conducive to better filling the space between the sidewalls 210 of the opposite sidewalls of the adjacent channel structures 110, so that the film quality of the placeholder material layer is better, and correspondingly the film quality of the placeholder layer 300 is better.

[0107] In this embodiment, the placeholder material layer above the top of the channel structure 110 is removed, and the placeholder material layer between the spacers 210 of the opposite sidewalls of the adjacent channel structures 110 is retained as the placeholder layer 300 .

[0108] First, a placeholder material layer is formed between the sidewalls 210 that fill the opposite side walls of the adjacent channel structures 110 and covers the channel structures 110 and the sidewalls 210, and then the placeholder material layer above the top of the channel structure 110 is removed. This is beneficial for obtaining a placeholder layer 300 with better top surface flatness, thereby providing a better process platform for the subsequent formation of the first work function layer.

[0109] refer to Fig.13 , Fig.13 (b) Fig.13 (a) A cross-sectional view along the AA direction. After forming the placeholder layer 300 and before subsequently forming the first work function, the forming method further includes: forming a dummy gate structure 400 spanning and covering the top of the placeholder layer 300 , the top of the spacer 210 , and the top of the channel structure 110 .

[0110] The dummy gate structure 400 is used to occupy a space for the subsequent formation of a gate electrode layer.

[0111] In this embodiment, the dummy gate structure 400 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.

[0112] As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.

[0113] refer to Fig.14 , Fig.14 (b) Fig.14 (a) A cross-sectional view along the AA direction, in which a dielectric layer 500 is formed to cover the dummy gate structure 400 .

[0114] The dielectric layer 500 is used to isolate adjacent devices, and is also used to provide a process basis for subsequently removing the dummy gate structure 400 to form a gate opening.

[0115] The material of the dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0116] Continue to refer Fig.14 , remove the dummy gate structure 400 , and form a gate opening 410 in the dielectric layer 500 .

[0117] The gate opening 410 is used to provide a space for the subsequent formation of a gate electrode layer. The gate opening 410 is also used to provide a process window for removing the spacer 210 .

[0118] Continue to refer Fig.14 Before subsequently forming the first work function layer, the method further includes: removing the sidewall 210 .

[0119] The sidewall spacer 210 is removed to provide a space for the subsequent formation of a first work function layer.

[0120] Specifically, in the present embodiment, in the step of removing the sidewall spacer 210 , the exposed sidewall spacer 210 is removed through the gate opening 410 .

[0121] In this embodiment, a wet etching process is used to remove the sidewall spacer 210 .

[0122] The wet etching process has an isotropic etching characteristic, which is beneficial for completely removing the sidewall 210 . The wet etching process is also easy to obtain a larger etching selectivity ratio, which is beneficial for reducing damage to the placeholder layer 300 and the channel structure 110 during the process of removing the sidewall 210 .

[0123] refer to Fig.15 , Fig.15 (b) Fig.15 (a) is a cross-sectional view along the AA direction, wherein a first work function layer 610 is formed to fill between opposite sidewalls of adjacent channel structures 110 and placeholder layers 300 and to cover the tops of the channel structures 110 and the placeholder layers 300 .

[0124] The first work function layer 610 and the subsequently formed second work function layer are used together to adjust the threshold voltage of the second device.

[0125] In this embodiment, the second device is a PMOS transistor. For the PMOS transistor, the work function layer is a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. Correspondingly, the material of the first work function layer 610 includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN.

[0126] In this embodiment, the first work function layer 610 is formed by an atomic layer deposition process.

[0127] The atomic layer deposition process has good gap filling capability, which is conducive to better filling the gap between the adjacent channel structure 110 and the placeholder layer 300, so that the film quality of the first work function layer 610 is better.

[0128] It should be noted that, in the process of forming the semiconductor structure, a side wall covering the side wall of the channel structure 110 is first formed, and then a placeholder layer 300 is formed between adjacent side walls, so that the spacing between adjacent placeholder layers 300 and the channel structure 110 is equal. Accordingly, it is also beneficial to make the width of the first work function layer 610 filled between the relative side walls of the adjacent channel structure 110 and the placeholder layer 300 and covering the side wall of the channel structure 110 equal, which is beneficial to make the effect of the first work function layer 610 on the side wall of the channel structure 110 more uniform. Therefore, in this embodiment, the channel structure 110 of the first device area 100a and the second device area 100b can be controlled separately according to the work function layer at the top of the channel structure 110 to realize different functions of the first device and the second device.

[0129] refer to Fig.16 , Fig.16 (b) Fig.16 (a) is a cross-sectional view along the AA direction, wherein a mask material layer (not shown) is formed to cover the first work function layer 610 .

[0130] The mask material layer is used for subsequently forming a mask layer.

[0131] In this embodiment, the mask material layer includes a bottom anti-reflective coating (BARC) material.

[0132] Continue to refer Fig.16 , remove the mask material layer in the first device region 100 a , and retain the mask material layer in the second device region 100 b as the mask layer 700 .

[0133] The mask layer 700 is used as an etching mask for removing the first work function layer 610 of the first device region 100 a .

[0134] refer to Fig.17 , Fig.17 (b) Fig.17 (a) is a cross-sectional view along the AA direction, using the mask layer 700 as a mask to remove the first work function layer 610 located on the top of the channel structure 110 and the placeholder layer 300 in the first device region 100a.

[0135] The first work function layer 610 located on the top of the channel structure 110 and the placeholder layer 300 in the first device region 100 a is removed to prepare for the subsequent formation of a second work function layer covering the top of the channel structure 110 in the first device region 100 a .

[0136] Specifically, in this embodiment, in order to adapt to the different performance requirements of NMOS transistors and PMOS transistors, NMOS transistors and PMOS transistors use different work function layers, so that the channel structure 110 of the first device area 100a and the first work function layer 610 on the top of the placeholder layer 300 are removed, and a second work function layer corresponding to the performance requirements of the first device is subsequently formed.

[0137] refer to Fig.18 , Fig.18 (b) Fig.18 (a) A cross-sectional view along the AA direction, with the mask layer 700 removed.

[0138] Removing the mask layer 700 provides a process platform for subsequently forming a second work function layer.

[0139] Continue to refer Fig.18 A second work function layer 620 is formed covering the channel structure 110, the placeholder layer 300 and the top of the first work function layer 610 in the first device region 100a, and the top of the first work function layer 610 in the second device region 100b.

[0140] The second work function layer 620 is used to adjust the threshold voltage of the first device.

[0141] In this embodiment, the first device is an NMOS transistor. For the NMOS transistor, the work function layer is an N-type work function layer. The material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC. Correspondingly, the material of the second work function layer 620 includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0142] It should be noted that, in this embodiment, the side walls of the channel structure 110 of the first device area 100a and the second device area 100b are only covered by the first work function layer 610. The threshold voltage of the channel structure 110 of the first device area 100a and the second device area 100b can be controlled respectively according to the work function layer on the top of the channel structure 110 to realize different functions of the first device and the second device.

[0143] refer to Fig.19 , Fig.19 (b) Fig.19 (a) is a cross-sectional view along the AA direction, in which the gate electrode layer 420 is formed to cover the second work function layer 620 .

[0144] Specifically, in the present embodiment, in the step of forming the gate electrode layer 420 , the gate electrode layer 420 is formed in the gate opening 410 .

[0145] The gate electrode layer 420 is used to electrically lead out the gate structure of the device.

[0146] In the present embodiment, the material of the gate electrode layer 420 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A substrate, comprising a first device region and a second device region adjacent to each other, wherein the first device region is used to form a first device, and the second device region is used to form a second device, and the first device and the second device are of different types; A channel structure protrudes from the substrate; A placeholder layer protrudes from the substrate and is located between adjacent channel structures; A first work function layer is filled between opposite side walls of adjacent channel structures and the placeholder layer, and the first work function layer also covers the channel structure of the second device region and the top of the placeholder layer; A second work function layer covers the channel structure, the placeholder layer and the top of the first work function layer in the first device region, and the second work function layer also covers the top of the first work function layer in the second device region; The gate electrode layer covers the second work function layer.

2. The semiconductor structure according to claim 1, It is characterized in that The placeholder layer is flush with the top of the channel structure.

3. The semiconductor structure according to claim 1, It is characterized in that The distance between the placeholder layer and the adjacent channel structure is 1 nm to 3 nm.

4. The semiconductor structure according to claim 1, It is characterized in that The material of the placeholder layer includes low-k dielectric material (low-k dielectric material refers to dielectric material with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric material (high-k dielectric material refers to material with k>5.0), silicon or silicon nitride.

5. The semiconductor structure according to claim 1, It is characterized in that The distances between adjacent placeholder layers and channel structures are all equal.

6. The semiconductor structure according to claim 1, It is characterized in that The first device region is used to form an NMOS region, and the second device region is used to form a PMOS region; The material of the first work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; The material of the second work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

7. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, comprising a first device region and a second device region adjacent to each other, wherein a channel structure protruding from the substrate is formed on the substrate, wherein the first device region is used to form a first device, and the second device region is used to form a second device, and the first device and the second device are of different types; forming a placeholder layer protruding from the substrate between adjacent channel structures; forming a first work function layer filling between opposite sidewalls of adjacent channel structures and placeholder layers and covering the channel structures and tops of the placeholder layers; forming a mask material layer covering the first work function layer; removing the mask material layer in the first device region, and retaining the mask material layer in the second device region as a mask layer; Using the mask layer as a mask, removing the first work function layer located on top of the channel structure and the placeholder layer in the first device region; removing the mask layer; forming a second work function layer covering the channel structure, the placeholder layer and the top of the first work function layer in the first device region, and the top of the first work function layer in the second device region; A gate electrode layer covering the second work function layer is formed.

8. The method for forming a semiconductor structure according to claim 7, It is characterized in that Before forming the placeholder layer, the forming method further comprises: forming a spacer material layer covering the top surface of the substrate, the sidewalls and the top surface of the channel structure; Removing the spacer material layer located on the top surface of the substrate and the top surface of the trench structure, and retaining the spacer material layer located on the side wall of the trench structure as a spacer; In the step of forming the placeholder layer, the placeholder layer is formed between sidewalls of opposite sidewalls of adjacent channel structures; Before forming the first work function layer, the method further includes: removing the sidewalls.

9. The method for forming a semiconductor structure according to claim 8, It is characterized in that The sidewall material layer is formed by an atomic layer deposition process.

10. The method for forming a semiconductor structure according to claim 8, It is characterized in that In the step of forming a spacer material layer covering the top surface of the substrate, the sidewalls and the top surface of the channel structure, the thickness of the spacer material layer is 1 nm to 3 nm.

11. The method for forming a semiconductor structure according to claim 8, It is characterized in that The step of forming the placeholder layer includes: forming a placeholder material layer filling between the spacers of the opposite sidewalls of the adjacent channel structures and covering the channel structures and the spacers; The placeholder material layer above the top of the channel structure is removed, and the placeholder material layer between the sidewalls of the opposite sidewalls of the adjacent channel structure is retained as the placeholder layer.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that The placeholder material layer is formed by an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 8, It is characterized in that After forming the placeholder layer and before forming the first work function, the forming method further comprises: forming a dummy gate structure spanning and covering the top of the placeholder layer, the top of the spacer and the top of the channel structure; forming a dielectric layer covering the dummy gate structure; removing the dummy gate structure and forming a gate opening in the dielectric layer; In the step of forming the gate electrode layer, the gate electrode layer is formed in the gate opening.

14. The method for forming a semiconductor structure according to claim 13, It is characterized in that In the step of removing the sidewall spacer, the exposed sidewall spacer is removed through the gate opening.

15. The method for forming a semiconductor structure according to claim 7, It is characterized in that In the step of forming the placeholder layer, the material of the placeholder layer includes low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), high-k dielectric material (high-k dielectric material refers to a material with k>5.0), silicon or silicon nitride.

16. The method for forming a semiconductor structure according to claim 7, It is characterized in that In the step of providing the substrate, the first device region is used to form an NMOS region, and the second device region is used to form a PMOS region; In the step of forming the first work function layer, the material of the first work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; In the step of forming the second work function layer, a material of the second work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

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