Crystal laminate structure and semiconductor element

Abstract

The invention aims to provide a crystal laminated structure which can form good Schottky contact with metal, SnO2 series semiconductor elements are manufactured on the basis of the crystal laminated structure, and development of SnO2 materials in the field of semiconductor elements can be promoted. The laminated structure body comprises a bottom layer substrate and a SnO2 series semiconductor layer which is directly arranged on the bottom layer substrate or indirectly arranged on the bottom layer substrate through other layers, and the SnO2 series semi-body thin film has a square rutile structure; the SnO2-based semiconductor layer has, as a main surface, a (002) plane or a plane inclined at an angle of 6 DEG or less with respect to the (002) plane.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a crystal stacked structure and a semiconductor element. Background Art

[0002] The third-generation semiconductor materials have characteristics such as large bandgap width and high critical breakdown field strength, which make them suitable for the preparation of high-quality power devices. Materials such as SiC, GaN, Ga2O3, SnO2, etc. The power devices prepared still have excellent performance under high electric field, high power, strong radiation and other environments.

[0003] The third-generation semiconductor materials that have been commercialized in batches are mainly SiC and GaN. Among them, the bandgap width of SiC is about 3.26eV, the breakdown field strength is about 3MV / cm, and the Baliga quality factor is about 340; the bandgap width of GaN is about 3.44eV, the breakdown field strength is about 5MV / cm, and the Baliga quality factor is about 870. Compared with them, the bandgap width of SnO2 is about 3.6eV, the breakdown field strength is about 4.3MV / cm, and the Baliga quality factor is about 626. These characteristics of SnO2 material make it very suitable for power devices such as diodes, MOS tubes, and IGBTs.

[0004] Compared with Si material (bandgap width is about 1.1eV, breakdown field strength is about 0.3MV / cm), the breakdown field strength of SnO2 material is about 14 times that of Si, and the Baliga quality factor is about 626 times that of Si. Therefore, when SnO2 material is used to make power devices, the thickness of the semiconductor film required to achieve the same voltage resistance effect is thinner, the device response rate is therefore faster, and the device conduction loss is therefore lower.

[0005] SiC is mainly prepared by physical vapor transport (PVT) method, and the preparation temperature of SiC single crystal is in the range of 2100 ~ 2400 ℃. However, there are more than 200 isomers of SiC, and defects are prone to occur in the single crystal preparation process, affecting the quality of the single crystal; SnO2 can also be prepared by physical vapor transport (PVT) method. The single crystal preparation temperature of SnO2 is in the range of 1650 ~ 1750 ℃, and under high temperature and slightly negative pressure environment, there is only one isomer, namely tetragonal rutile SnO2, and there will be no crystal defects caused by isomer problems; based on the above comparison, compared with SiC, the single crystal preparation cost of SnO2 is relatively lower and the defects are relatively smaller.

[0006] In the past, it was known that SnO2 material can be used as a transparent electrode due to its good conductive properties. However, due to the presence of a large number of defects on the (200) surface of SnO2, it is difficult to form a good Schottky contact with metal, which affects the manufacturing and performance improvement of semiconductor components. In order to use SnO2-based semiconductor films to form semiconductor components, it is necessary to control the defects of SnO2-based semiconductor films. Summary of the invention

[0007] In view of this, an object of the present invention is to provide a crystal stacked structure and a semiconductor element to solve the problem that the existing SnO2-based semiconductor film is difficult to form Schottky contact with metal.

[0008] In order to solve the above problems, the present invention provides the following technical solutions:

[0009] (1) A first aspect of the present invention provides a crystalline stacked structure, comprising:

[0010] bottom substrate;

[0011] And a SnO2-based semiconductor layer is directly or indirectly arranged on the underlying substrate through other film layers, and the SnO2-based semiconductor layer has a tetragonal rutile structure, and the SnO2-based semiconductor layer has a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main surface.

[0012] Preferably, the surface roughness of the SnO2-based semiconductor layer is Ra≤0.1 um.

[0013] Preferably, the average dislocation density of the SnO2-based semiconductor layer is ≤ 1 x 10 5 / cm 2 .

[0014] Preferably, the thickness of the SnO2-based semiconductor layer is in the range of 0.5um to 50um.

[0015] Preferably, the bottom substrate is an m-plane sapphire substrate.

[0016] Preferably, the underlying substrate is a SnO2-based single crystal substrate having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a main plane.

[0017] To achieve the above object, the present invention provides the following technical solutions:

[0018] A second aspect of the present invention provides a semiconductor element including the above-mentioned crystal stacked structure.

[0019] Preferably, the semiconductor element is a power device.

[0020] Preferably, the power device is a diode, a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0021] (7) Preferably, the diode is a Schottky diode having an anode electrode and a cathode electrode, and the anode electrode is Ti, Mo, W, Ni, Au or Pt.

[0022] The beneficial effects of the present invention are as follows:

[0023] The crystal stacked structure of the present invention comprises a base substrate, and a SnO2-based semiconductor layer having a tetragonal rutile structure and having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a main surface, which is directly or indirectly arranged on the base substrate through other film layers. The SnO2-based semiconductor layer has small defects and a smooth surface and can form a good Schottky contact with a metal.

[0024] Furthermore, based on the fact that the SnO2-based semiconductor layer can form a good Schottky contact with metal, we can manufacture SnO2-based semiconductor components based on this and promote the use of SnO2 materials in the field of semiconductor components. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1a A cross-sectional view of a SnO2-based semiconductor layer grown on an m-plane sapphire substrate according to an embodiment of the present invention;

[0026] Figure 1b A cross-sectional view of an m-plane sapphire substrate according to an embodiment of the present invention indirectly growing a SnO2-based semiconductor layer by growing a buffer layer;

[0027] Figure 2 A three-dimensional diagram of the crystal structure of a SnO2-based semiconductor layer grown on an m-plane sapphire substrate according to an embodiment of the present invention;

[0028] Figure 3 SEM observation images of a SnO2-based first semiconductor layer and a SnO2-based second semiconductor layer with (002) plane orientation grown on an m-plane sapphire substrate provided in one embodiment of the present invention;

[0029] Figure 4 XRD full spectrum of a SnO2-based first semiconductor layer and a SnO2-based second semiconductor layer with (002) plane orientation grown on an m-plane sapphire substrate provided in one embodiment of the present invention;

[0030] Figure 5 A cross-sectional view of growing a SnO2-based semiconductor layer on a SnO2-based single crystal substrate is provided as one embodiment of the present invention;

[0031] Figure 6 A cross-sectional view of a pseudo vertical SnO2 Schottky diode provided by one embodiment of the present invention;

[0032] Figure 7 A schematic diagram of a method for preparing a pseudo vertical SnO2 Schottky diode provided by an embodiment of the present invention;

[0033] Figure 8 A current-voltage characteristic curve of a pseudo vertical SnO2 Schottky diode provided by an embodiment of the present invention;

[0034] Figure 9a A cross-sectional view of a vertical SnO2 Schottky diode provided by one embodiment of the present invention;

[0035] Figure 9b A cross-sectional view of a SnO2 Schottky diode with a vertical field plate structure provided by one embodiment of the present invention;

[0036] Fig.9c A cross-sectional view of a SnO2 Schottky diode with a vertical field limiting ring structure provided by one embodiment of the present invention;

[0037] Fig.10 A cross-sectional view of a SnO2 Schottky MOSFET provided by one embodiment of the present invention;

[0038] Fig.11 A cross-sectional view of a SnO2 IGBT provided in accordance with an embodiment of the present invention;

[0039] The reference numerals are as follows:

[0040] 1. M-plane sapphire (bottom substrate)

[0041] 2. The first semiconductor layer (bottom substrate or n + -SnO2 semiconductor layer)

[0042] 3. The second semiconductor layer (n - -SnO2 semiconductor layer)

[0043] 4. Cathode electrode

[0044] 5. Anode electrode

[0045] 6. Buffer layer

[0046] 13. Dielectric layer

[0047] 14. p-type SnO2

[0048] 21. Source Part 1

[0049] 22. Source Part 2

[0050] 23. Drain

[0051] 24. Gate insulation film

[0052] 25. Gate

[0053] 31. The third semiconductor layer (p - Type SnO2 semiconductor layer)

[0054] 32. The fourth semiconductor layer (n + Type SnO2 semiconductor layer)

[0055] 33. The fifth semiconductor layer (p + Type SnO2 semiconductor layer)

[0056] 36. Source DETAILED DESCRIPTION

[0057] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] The crystalline stacked structure of the present invention comprises an underlying substrate, and a SnO2-based semiconductor layer directly or indirectly disposed on the underlying substrate through a film layer (e.g., a buffer layer), and the SnO2-based semiconductor layer has a tetragonal rutile structure, and the SnO2-based semiconductor layer has a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main surface. The surface roughness Ra of the SnO2-based semiconductor layer is ≤0.1um. The surface roughness (Ra) is not particularly limited if it is less than 0.1um, and is preferably less than 30nm in the present invention, and more preferably less than 10nm.

[0059] The crystalline stacked structure is a structure containing more than one crystalline layer, and may also contain layers other than the crystalline layer. The crystalline layer is preferably a single crystal layer, and may also be a polycrystalline layer. The SnO2-based semiconductor layer may be annealed after film formation, and a good Schottky contact is formed between the SnO2-based semiconductor layer and the Schottky electrode by annealing. The Schottky electrode is Ti, Mo, W, Ni, Au or Pt.

[0060] As for the underlying substrate, the underlying substrate may be an m-plane sapphire having a corundum structure, or a SnO2-based single crystal having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as the main plane, and a SnO2-based semiconductor layer is directly or indirectly provided on the underlying substrate through a film layer to form a stacked structure. The underlying substrate may be an n-type SnO2-based semiconductor layer or a p-type SnO2-based semiconductor layer, preferably an n-type SnO2-based semiconductor layer, and is composed of an oxide with Sn as the main component added with one or more selected from Nb, In, Sb, Mg, Zn, etc.

[0061] As for the crystalline thin film, the crystalline thin film is a SnO2-based single crystal thin film with the (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as the main plane, and the surface roughness Ra of the SnO2-based semiconductor layer is ≤0.1um. The surface roughness (Ra) is not particularly limited if it is less than 0.1um, and is preferably less than 30nm in the present invention, and more preferably less than 10nm. The average dislocation density of the SnO2-based semiconductor layer is ≤1x 10 5 / cm 2 The thickness of the SnO2-based semiconductor layer is in the range of 0.5um to 50um, and in the present invention, it is preferably less than 30um, and more preferably less than 20um.

[0062] First embodiment

[0063] The first embodiment of the present invention provides a specific stacked structure. Figure 1a is a cross-sectional view of a crystal stacked structure of the present invention. Embodiments of the crystal stacked structure provided by the present invention include:

[0064] Bottom substrate 1, including m-plane Sapphire with corundum structure;

[0065] The first semiconductor layer 2 is n + -SnO2 semiconductor layer, formed on the underlying substrate 1, is a SnO2 single crystal with the (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as the main plane;

[0066] The second semiconductor layer 3 is n - -SnO2 semiconductor layer, formed on the n + The SnO2 semiconductor layer 2 is a SnO2-based single crystal having the (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a main plane.

[0067] In other embodiments, the SnO2-based semiconductor layer may be indirectly disposed on the bottom substrate 1 through the film layer 6 (which is the buffer layer 6). Figure 1b As shown, Figure 1b The crystal stacked structure shown in the figure grows the first semiconductor layer 2 by growing the buffer layer 6, which can reduce the stress between the underlying substrate 1 and the first semiconductor layer 2 and reduce the formation of defects.

[0068] like Figure 2 As shown, the azimuthal axis of the crystal structure of rutile SnO2 is <100> , b-axis <010> , c-axis <001> The first semiconductor layer 2 and the second semiconductor layer 3 are plate-shaped with the crystal plane indices defined by the three axes, namely, the (101) plane, the (001) plane, and the (010) plane, and the lattice constant is One or more of the elements (such as Nb, In, Sb, Mg, Zn, etc.) are selected for doping to form oxide crystals with Sn as the main component. The lattice constant, bandgap width and conductivity type of the doped SnO2 crystal may change.

[0069] In this embodiment, m-plane is selected of sapphire as the underlying substrate.

[0070] Among them, the preparation methods of the first semiconductor layer 2 and the second semiconductor layer 3 include physical vapor transport, spray thermal decomposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, etc.

[0071] In this embodiment, the radio frequency magnetron sputtering method is used to prepare the first semiconductor layer 2. The preparation process is as follows:

[0072] First, the target material is prepared by uniformly mixing the required doping elements (such as Sb), Sb2O5 with SnO2 in a certain stoichiometric ratio, sintering them at a certain temperature, and finally preparing an n-type SnO2 target material doped with a certain concentration.

[0073] Then, the m-plane sapphire substrate was ultrasonically cleaned with acetone, anhydrous ethanol and deionized water for 15 minutes in turn, and then blown dry with high-purity nitrogen to obtain a clean substrate and placed in the vacuum chamber of the magnetron sputtering system. The element-doped n-type SnO2 ceramic target material was placed in the RF sputtering target position, the working gas pressure was stabilized at 1Pa, the working temperature was stabilized at 500°C, and a suitable deposition time was used.

[0074] Finally, after reaching the specified time, the substrate is taken out and annealed at a certain time and temperature. After the SnO2 crystal is exposed with (002) as the main surface, the first semiconductor layer 2 is prepared.

[0075] The first semiconductor layer 2 is prepared by the above-mentioned RF magnetron sputtering method, and the second semiconductor layer 3 is epitaxially grown on the first semiconductor layer 2. Similarly, the second semiconductor layer 3 is prepared by the RF magnetron sputtering method. The concentration of the second semiconductor layer 3 is different from that of the first semiconductor layer 2, and the required doped target material needs to be prepared. The operation steps are the same as those of the above-mentioned first layer of semiconductor, and the thickness of the semiconductor layer can be controlled by controlling the sputtering time.

[0076] Figure 3 This is a SEM observation picture of the first semiconductor layer 2 and the second semiconductor layer 3 grown on the m-plane sapphire provided in the first embodiment of the present invention.

[0077] Figure 4 The first embodiment of the present invention provides a full XRD spectrum of the first semiconductor layer 2 and the second semiconductor layer 3 grown on the m-plane sapphire. Both spectra contain the (3030) crystal plane diffraction peak of the m-plane sapphire and the (002) crystal plane diffraction peak of SnO2, and there are no other crystal plane diffraction peaks in the spectrum, indicating that (002) plane oriented SnO2 epitaxial crystals are successfully prepared on the m-plane sapphire by radio frequency magnetron sputtering.

[0078] Second embodiment

[0079] The second embodiment of the present invention provides a specific stacked structure. Figure 5 is a cross-sectional view of a crystal stacked structure of the present invention. Embodiments of the crystal stacked structure provided by the present invention include:

[0080] The bottom substrate 2 is a first semiconductor layer, which is n + -SnO2 semiconductor layer, the bottom substrate 2 is a SnO2 single crystal substrate with the (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as the main surface; the second semiconductor layer 3 formed on the bottom substrate 2 is n - - The SnO2 semiconductor layer is a SnO2-based semiconductor layer having as its main surface the (002) plane or a plane inclined at an angle within a range of 6° relative to the (002) plane.

[0081] The preparation methods of the bottom substrate 2 in the second embodiment include physical vapor transport (PVT), chemical vapor deposition, and the like.

[0082] This embodiment uses the PVT method to prepare the bottom substrate 2, and a growth process is provided as follows:

[0083] (1) Vacuuming: Use a mechanical pump to evacuate the air pressure in the furnace cavity to below 10Pa;

[0084] (2) Removing impurity gases: slowly raise the temperature to a certain temperature, keep the pump running, and keep the gas pressure in the furnace cavity below 10Pa. The main purpose of this step is to remove the impurity gases adsorbed by the tin oxide powder source;

[0085] (3) Rapid heating - pressure reduction and constant temperature: During the rapid heating process, high-purity CO2 gas is filled into the furnace chamber, and the temperature is kept constant until it reaches 1650°C to 1750°C. During the heating process, the gas pressure needs to be reduced to control the gas pressure within a certain range.

[0086] (4) Crystal growth: The growth environment of SnO2 crystal is constant temperature and pressure, and the temperature gradient difference between the bottom of the crucible and the seed crystal is maintained between 100K and 200K. During the growth of SnO2 crystal, the height of the seed crystal rod can be slowly and dynamically adjusted to keep the temperature gradient difference stable. The reactions involved in this process are as follows:

[0087] SnO2(s)=SnO(g)+0.5O2(g)

[0088] SnO(g)+CO2(g)=SnO2(single crystal)+CO(g)

[0089] SnO(g)+0.5O2(g)=SnO2(single crystal)

[0090] (5) Stop growth: When a growth process is completed, stop heating and end the growth of SnO2 single crystal.

[0091] The single crystal obtained above is cut into a SnO2 crystal block with the (002) plane as the main surface, and then the SnO2 crystal is cleaned to remove organic and inorganic substances on the surface, so that it is in a state that can allow epitaxial growth of Sn-containing oxide.

[0092] The preparation methods of the second semiconductor layer 3 include MOCVD, sol-gel, spray pyrolysis, chemical vapor deposition, molecular beam epitaxial growth, magnetron sputtering, pulsed laser deposition, ion beam plating, and the like.

[0093] In this embodiment, when the magnetron sputtering method is used to prepare the second semiconductor layer 3, the growth method is the same as the method described in the first embodiment.

[0094] When the MOCVD method is used to prepare the second semiconductor layer 3, a preparation process is provided as follows:

[0095] (1) The reaction chamber of the MOCVD equipment is evacuated to a vacuum, and the first semiconductor layer is placed in the reaction formula and heated to the desired growth temperature;

[0096] (2) Turn on the nitrogen gas and purge the chamber with a large flow rate, then turn on the oxygen gas and keep it for a period of time, and finally introduce the organic metal Sn source to grow the second semiconductor layer by adjusting the nitrogen gas flow rate, reaction temperature, pressure in the reaction chamber and growth time;

[0097] When the crystal grows to the required thickness, the growth is stopped, and samples are taken after cooling to room temperature, thus completing the growth of the second semiconductor layer.

[0098] Third embodiment

[0099] A third embodiment of the present invention provides a semiconductor element, comprising a specific implementation of any one of the crystal stacked structures in the first embodiment.

[0100] Furthermore, the semiconductor component is a Schottky diode, and the Schottky diode further includes:

[0101] A Schottky electrode, located on the upper surface of the second semiconductor layer 3;

[0102] The ohmic electrode is located on the upper surface of the first semiconductor layer 2 and on both sides of the second semiconductor layer 3 and is separated from the second semiconductor layer 3 .

[0103] like Figure 6 FIG. 4 is a cross-sectional view of a Schottky barrier diode provided in a third embodiment of the present invention. The diode is a Schottky diode of a pseudo vertical structure, comprising:

[0104] Bottom substrate 1, m-side of sapphires;

[0105] A first semiconductor layer 2, located on the upper surface of the bottom substrate 1;

[0106] The second semiconductor layer 3 is located on the upper surface of the first semiconductor layer 2;

[0107] The cathode electrode 4 is located on the upper surface of the first semiconductor layer 2 , and the cathode electrode 4 forms an ohmic contact with the upper surface of the first semiconductor layer 2 .

[0108] The anode electrode 5 is located on the upper surface of the second semiconductor layer 3 , and the anode electrode 5 forms a Schottky contact with the upper surface of the second semiconductor layer 3 .

[0109] This embodiment also provides a method for preparing a SnO2 Schottky diode. Figure 7 FIG. 1 is a schematic diagram of a Schottky diode manufacturing process, wherein the method comprises the following steps:

[0110] S1. Select m-plane sapphire as the substrate and clean it using a standard cleaning process;

[0111] S2, depositing a first semiconductor layer 2 on the sapphire substrate using a magnetron sputtering process;

[0112] S3, depositing a second semiconductor layer 3 on the first semiconductor layer 2 using a magnetron sputtering process;

[0113] S4, using a photolithography process to prepare a photoresist mask layer of a preset shape on the second semiconductor layer 3;

[0114] S5, etching the photoresist mask layer using a dry etching process, transferring the pattern to the second semiconductor layer 3, exposing the first semiconductor layer 2, and completing the production of the mesa of the second semiconductor layer 3;

[0115] S6 and S7, preparing a photolithography mask layer in a preset area of ​​the first semiconductor layer 2 and depositing an ohmic contact metal layer by using a photolithography process and a metal plating technology;

[0116] S8 and S9, preparing a photolithography mask layer in the mesa region of the second semiconductor layer 3 and depositing a Schottky contact metal layer by using a photolithography process and a metal coating technology;

[0117] In this embodiment, the carriers flow from the anode vertically through the second semiconductor layer 3 and then horizontally through the first semiconductor layer 2 to the cathode, forming a pseudo-vertical SnO2 Schottky diode with excellent performance and reliability.

[0118] Furthermore, the ohmic contact electrode used in this experiment is indium.

[0119] Furthermore, the Schottky electrode can be a high work function metal such as tungsten, nickel, molybdenum, gold, platinum, titanium, etc. The anode metal used in this experiment is tungsten.

[0120] Figure 8 An IV characteristic curve of a pseudo-vertical SnO2 Schottky diode provided by an embodiment of the present invention is shown. As can be seen from the figure, the Schottky diode prepared by the stacked structure has an IV curve showing good Schottky contact characteristics.

[0121] Fourth embodiment

[0122] A fourth embodiment of the present invention provides a semiconductor element including a specific implementation of the crystal stacked structure in the second embodiment.

[0123] Furthermore, the semiconductor device is a vertical structure Schottky diode, such as Figure 9a The Schottky diode has a stacked first semiconductor layer 2 and a second semiconductor layer 3. The anode electrode 5 is located on the upper surface of the second semiconductor layer 3 and forms a Schottky contact therewith. The cathode electrode 4 is located on the lower surface of the first semiconductor layer 2 and forms an ohmic contact therewith.

[0124] In the Schottky barrier diode, by applying a forward voltage between the anode electrode 5 and the cathode electrode 4 (positive potential on the anode electrode 5 side), the interface barrier between the anode electrode 5 and the second semiconductor layer 3 is lowered, and current flows from the anode electrode 5 to the cathode electrode 4 .

[0125] In the Schottky barrier diode, by applying a reverse voltage between the anode electrode 5 and the cathode electrode 4 (negative potential on the anode electrode 5 side), a depletion layer expands from the interface between the anode electrode 5 and the second semiconductor layer 3 , and a withstand voltage is achieved by the depletion layer.

[0126] In reverse bias, the spatial electric field distribution is not uniform, and the electric field is denser near the Schottky junction, causing avalanche breakdown to occur earlier, thereby improving its withstand voltage characteristics.

[0127] Figure 9b It is a Schottky diode with a field plate structure. Figure 9a Compared with the Schottky diode shown, the second semiconductor layer 3 not only forms a Schottky contact with the anode electrode 5 but also covers the dielectric layer 13. Part of the anode electrode extends above the dielectric layer 13 to form a field plate. The field plate structure can reduce the electric field strength at the contact edge of the anode electrode 5 and the second semiconductor layer 3, thereby improving the withstand voltage of the device.

[0128] Fig.9c It is a Schottky diode with a field limiting ring structure. Figure 9a Compared with the Schottky diode shown in the figure, a plurality of p-type SnO2 regions 14 are formed in the second semiconductor layer 3 by ion implantation. The p-type SnO2 regions 14 form a pn junction with the second semiconductor layer 3, and a depletion region can be quickly formed during the application of a reverse withstand voltage, thereby improving the withstand voltage of the device.

[0129] Fifth embodiment

[0130] A fifth embodiment of the present invention provides a semiconductor element including a specific implementation of the crystal stacked structure in the second embodiment.

[0131] Furthermore, the semiconductor device is a vertical structure Schottky junction MOSFET, such as Fig.10 It is a cross-sectional view of a Schottky junction MOSFET. The Schottky junction MOSFET has a stacked first semiconductor layer 2 and a second semiconductor layer 3. The source electrode is located on the upper surface of the second semiconductor layer 3. The source electrode is divided into a first source part 21 and a second source part 22. The first source part 21 extends into the second semiconductor layer 3. There is a Schottky barrier between the first source part 21 and the second semiconductor layer 3. The second source part 22 forms an ohmic contact with the second semiconductor layer 3. The second source part 22 is closer to the gate insulating film 24 than the first source part 21. The gate 25 is wrapped by the gate insulating film 24 and is located in the groove of the second semiconductor layer 3.

[0132] In a Schottky junction MOSFET, by applying a forward voltage between the drain 23 and the source electrode (the drain 23 side is a positive potential), when a positive voltage is applied to the gate 25, the Schottky junction MOSFET is forward-conducted, and the on-current flows out from the second source portion 22. When no voltage is applied to the gate 25, the depletion layer formed by the Schottky contact between the first source portion 21 and the second semiconductor layer 3 cuts off the current between the drain 23 and the second source portion 22. The depletion layer formed by the Schottky contact expands in the second semiconductor 3, and the voltage is mainly borne by the second semiconductor layer 3.

[0133] Sixth embodiment

[0134] A sixth embodiment of the present invention provides a semiconductor element including a specific implementation of the crystal stacked structure in the second embodiment.

[0135] Furthermore, the semiconductor device is a vertical structure IGBT, such as Fig.11 is a cross-sectional view of an IGBT, wherein the IGBT has a stacked structure of a first semiconductor layer 2, a second semiconductor layer 3, a third semiconductor layer 31, a fourth semiconductor layer 32 and a fifth semiconductor layer 33, wherein the third semiconductor layer 31 is p - type SnO2 semiconductor layer, the fourth semiconductor layer 32 is n + type SnO2 semiconductor layer, the fifth semiconductor layer 33 is p + type SnO2 semiconductor layer, the fourth semiconductor layer 32 is located above the third semiconductor layer 31, the source 36 extends through the fourth semiconductor layer 32 and contacts the third semiconductor layer 31, the groove passes through the fourth semiconductor layer 32 and the third semiconductor layer 31, and stays in the second semiconductor layer 3, the inner surface of the groove is covered by an insulating film, and the insulating film is a gate insulating film 34, and the conductive material is filled in the groove to form a gate 35.

[0136] In the IGBT, by applying a forward voltage between the drain 23 and the source 36 (the drain 23 side is a positive potential), when a positive voltage is applied to the gate, the gate insulating film 34 forms a channel region, and the current flows from the drain to the source through the channel. When no voltage is applied to the gate, the device becomes cut-off, and the withstand voltage is mainly achieved by the expansion of the depletion layer in the second semiconductor layer 3. Compared with ordinary MOSFET, the fifth semiconductor layer 33 of IGBT provides a large number of holes to participate in conduction when it is turned on, and the current conduction capacity is much greater than that of MOSFET.

[0137] The above is a description of the preferred embodiment of the present invention, but the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the present invention, which are of course also included in the scope of the present invention. The method for forming each layer of the semiconductor element according to the present invention is not particularly limited as long as it does not hinder the purpose of the present invention, and can be a known method.

Claims

1. A crystal stacked structure, characterized in that: include: underlying substrate; as well as A SnO2-based semiconductor layer, wherein the SnO2-based semiconductor layer is disposed on the underlying substrate directly or indirectly through a film layer, wherein the SnO2-based semiconductor layer has a tetragonal rutile structure, and wherein the SnO2-based semiconductor layer has a (002) plane or a plane inclined at an angle within 6° relative to the (002) plane as a main surface.

2. The crystal stacked structure according to claim 1, characterized in that The surface roughness of the SnO2-based semiconductor layer is Ra≤0.1 um.

3. The crystal stacked structure according to claim 1, characterized in that The average dislocation density of the SnO2-based semiconductor layer is ≤1x10 5 / cm 2 .

4. The crystal stacked structure according to claim 1, characterized in that The thickness of the SnO2-based semiconductor layer is in the range of 0.5um to 50um.

5. The crystal stacked structure according to any one of claims 1 to 4, characterized in that: The bottom substrate is an m-plane sapphire substrate.

6. The crystal stacked structure according to any one of claims 1 to 4, characterized in that: The underlying substrate is a SnO2-based single crystal substrate having a (002) plane or a plane inclined within an angle range of 6° relative to the (002) plane as a main surface.

7. A semiconductor element, characterized in that: A crystal stacked structure comprising any one of claims 1 to 6.

8. The semiconductor device according to claim 7, characterized in that The semiconductor element is a power device.

9. The semiconductor device according to claim 8, characterized in that The power device is a diode, a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

10. The semiconductor device according to claim 9, characterized in that The diode is a Schottky diode having an anode electrode and a cathode electrode, and the anode electrode is Ti, Mo, W, Ni, Au or Pt.

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