NiOx / Ga2O3-based dual-heterojunction enhanced planar gate vertical bipolar transistor

Abstract

The invention discloses an enhanced planar gate vertical bipolar transistor based on NiOx / Ga2O3 double heterojunction, and mainly solves the problems that enhancement cannot be realized and the reverse voltage endurance capability is poor in the prior art. The device comprises a drain electrode, a substrate, a drift region, a p-type conductive layer and a gate electrode from bottom to top to form a planar gate structure, current blocking layers are arranged on two sides above the drift region, ohmic contact layers are arranged on two sides of the p-type conducting layer, source electrodes are arranged on two sides of the gate electrode, the substrate and the ohmic contact layers are highly doped gallium oxide, the drift region is low doped gallium oxide, the current blocking layers are high-resistivity gallium oxide, and the p-type conducting layer is p-type NiOx; and the p-type NiOx is respectively contacted with the ohmic contact layer and the drift region to form a first heterojunction J1 and a second heterojunction J2. By utilizing the plane gate structure and the double heterojunction J1 and J2, the voltage endurance capability of the device can be obviously improved, the enhancement of the device is realized, the safe working area range of the device is enlarged, and the method can be used for preparing the high-power gallium oxide transistor.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power electronic devices, and in particular relates to a double heterojunction enhanced planar gate vertical bipolar transistor, which can be used for power transmission and high-power electric energy conversion. Background Art

[0002] As a new type of ultra-wide bandgap semiconductor material, the research on Ga2O3 power devices has attracted extensive attention in recent years. g =4.8eV bandgap width, according to the critical electric field E C The direct bandgap width E g Between E C =1.73×10 5 E g 2.5 Ga2O3 has a very high critical breakdown electric field strength E C =8MV / cm. In addition, the n-type Ga2O3 material has a doping concentration of 10 15 -10 20 cm -3 Controllable, electron mobility μ n =150cm 2 / V·s and Gundam ν n,sat =2×10 7 The electron saturation velocity is cm / s. Therefore, Ga2O3 materials have great advantages in the field of power devices, and the power factor figure of merit Baliga's FoM = εμ n E C 3 It is 10 times and 4 times that of the third-generation semiconductors SiC and GaN.

[0003] The patent document with application number 202310698699.2 discloses a "Gallium oxide vertical transistor with integrated Schottky diode and preparation method". The device includes: a current blocking layer; a heavily doped contact layer located above the current blocking layer; a gate groove; a diode contact groove; an anode electrode passes through the current blocking layer and the heavily doped contact layer, and the source electrode covers the diode contact groove and the heavily doped contact layer; the gate electrode covers the gate dielectric layer and the source electrode, and there is an opening on the gate electrode, exposing at least part of the gate dielectric layer. The device realizes the integration of Ga2O3 Schottky diode and Ga2O3 vertical transistor, but because it is a unipolar device, it is usually a depletion device, and the reverse leakage increases with the increase of reverse voltage, and the reverse voltage resistance is poor.

[0004] The patent document with application number CN202111498547.5 discloses a "Ga2O3-based heterojunction field effect transistor and its preparation". Figure 1As shown, it includes: source electrode; substrate layer; drift region; drain electrode; gate electrode; P-type NiO layers are provided at both ends of the drift region to form a heterogeneous PN junction with the N-type Ga2O3 drift layer. The device mainly controls the vertical channel of the gallium oxide transistor through the heterogeneous PN junction, thereby realizing the switching characteristics of the triode, but because the channel layer is usually wide and parallel to the reverse electric field direction, it is difficult to achieve an enhanced device and a higher power figure of merit.

[0005] The patent document with application number 202410483432.6 discloses "a fin-type gate wide bandgap and ultra-wide bandgap MOSFET device with integrated heterojunction diode". The device includes: a substrate, an N-type voltage-resistant layer, a P-type semiconductor region, a gate conductor, a dielectric layer, an N-type semiconductor region, an isolation dielectric layer, an ohmic contact metal, and a drain ohmic contact metal. The device is a grooved gate FinFET structure. The grooved gate can effectively reduce the on-resistance of the device, but the etched groove introduces a large amount of interface damage, increases the reverse leakage of the device, and narrows the safe operating area SOA. Only the diode part of the device is a heterojunction structure, and it is also difficult to realize an enhanced device.

[0006] In addition, although the devices proposed in the above-mentioned comparative documents adopt a heterogeneous PN junction structure, they are all unipolar devices in terms of working principle, and it is difficult to achieve an enhanced working mode, resulting in complex back-end circuit design and poor safety performance. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to provide a method based on NiO x The invention discloses a planar gate enhanced vertical bipolar transistor with double heterojunction of Ga2O3 and a preparation method thereof, so as to widen the safe working area of ​​the transistor through the planar gate structure, improve the reverse withstand voltage capability of the device, and realize the enhanced working mode of the device through the double heterojunction.

[0008] The technical solutions for achieving the purpose of the present invention include the following:

[0009] 1. A NiO-based x The double heterojunction enhanced planar gate vertical bipolar transistor of Ga2O3 includes a substrate 1, a drift region 2, a current blocking layer 3, an ohmic contact layer 4, a p-type conductive layer 5, a drain electrode 6, a source electrode 7 and a gate electrode 8, and is characterized by:

[0010] The current blocking layer 3 is made of high resistivity Ga2O3 material, which is distributed on the left and right sides above the drift region 2 to block the flow of current and control the flow path of the current;

[0011] The ohmic contact layer 4 is made of regrown highly doped n-type Ga2O3 material to form a good ohmic contact with the source electrode 7, and is located above the current blocking layers 3 distributed on both sides;

[0012] The p-type conductive layer 5 is made of p-type conductive material and is located above the middle of the drift region 2. Its left and right sides are in contact with the ohmic contact layers 4 distributed on both sides to form a first heterogeneous pn junction J1, and its bottom is in contact with the drift region to form a second heterogeneous pn junction J2, so as to improve the reverse withstand voltage capability of the device, and control the flow of electrons from the source electrode to the drain electrode through these two heterogeneous pn junctions to achieve an enhanced working state of the device;

[0013] The gate electrode 8 is located above the p-type conductive layer 5, forming a planar gate structure that directly controls the conduction of the p-type conductive layer from above, so as to increase the safe operating area and simplify the device manufacturing process.

[0014] Furthermore, two source electrodes 7 are respectively located above the ohmic contact layer 4 on both sides, the gate electrode 8 is located above the p-type conductive layer 5 , and the drain electrode 6 is located below the substrate 1 .

[0015] Furthermore, the substrate 1 is made of highly doped n-type Ga2O3 material to reduce the on-resistance of the device and play a role in supporting the device. Its thickness T sub ≥300um, doping concentration N d,sub =1×10 17 ≤N d,sub ≤1×10 20 cm -3 The drift region 2 is made of low-doped n-type Ga2O3 material, which is used to connect the current blocking layer 3 and the p-type conductive layer 5, and its thickness T drift =1≤T sub ≤30000nm, doping concentration N d,drift =1×10 15 ≤N d,drift ≤1×10 17 cm -3 .

[0016] Furthermore, the current blocking layer 3 has a thickness T block =1≤T block ≤1000nm, resistivity ρ block is: block ≥1×10 3 Ω·cm; the ohmic contact layer 4 has a thickness T ohmic =1≤T ohmic ≤2000nm, doping concentration N d,ohmic For: N d,ohmic ≥1×10 16 cm -3 The p-type conductive layer 5 has a thickness T pNiO =1≤T pNiO ≤2000nm, doping concentration N d,pNiO For: Nd,pNiO ≥1×10 17 cm -3 .

[0017] 2. Preparation of NiO-based x The method for producing a Ga2O3 double heterojunction enhanced planar gate vertical bipolar transistor comprises the following steps:

[0018] 1) Select a sample with a Ga2O3 drift region 2 epitaxially grown on a Ga2O3 substrate 1, and sequentially place it in acetone, isopropanol, and deionized water for ultrasonic cleaning;

[0019] 2) The sample is transferred to a photolithography operation table, and a current blocking layer 3 region is photolithographically formed on the drift region 2, and then the sample is placed in a reaction chamber of an ion implanter for ion implantation to form a current blocking layer 3;

[0020] 3) Place the sample after ion implantation in the reaction chamber of the metal organic chemical vapor deposition system, and grow a layer of doping concentration not less than 1×10 16 cm -3 The n-type Ga2O3 ohmic contact layer is formed, and the regrown Ga2O3 on the photoresist is removed by a stripping process to form an ohmic contact layer 4 aligned with the current blocking layer;

[0021] 4) The sample is transferred to a photolithography operation table, a p-type conductive layer 5 region is photolithographically formed on the sample surface, and a layer of doping concentration not less than 1×10 17 cm -3 p-type NiO x , and then remove the NiO above the photoresist through the stripping process x , forming a p-type conductive layer 5;

[0022] 5) Placing the sample in a rapid thermal annealing furnace and subjecting the sample to rapid thermal annealing treatment to enhance the blocking ability of the current blocking layer and improve the re-grown n-type Ga2O3 ohmic contact layer and p-type NiO x Material quality of the conductive layer;

[0023] 6) placing the sample with its back side facing upward in a reaction chamber of an electron beam evaporation deposition system, depositing drain electrode metal on the back side of the substrate 1 by electron beam evaporation technology, and then transferring the sample to a photolithography operation table, photolithography a source electrode region in the region of the ohmic contact layer 4; transferring the sample to the reaction chamber of the electron beam evaporation deposition system again, depositing source electrode metal on the front side of the sample by electron beam evaporation technology, and removing the source electrode metal above the photoresist by a stripping process;

[0024] 7) placing the sample in a rapid thermal annealing furnace and performing a rapid thermal annealing treatment on it to achieve ohmic contact between the drain electrode and the source electrode, reduce the ohmic contact resistance, and form the drain electrode 6 and the source electrode 7;

[0025] 8) Transfer the sample to the photolithography operation station and x The gate electrode 8 region is photolithographically formed above the conductive layer, and a layer of gate electrode metal is deposited on the sample surface using electron beam evaporation technology. The gate electrode metal above the photoresist is then removed using a stripping process to form a gate electrode 8 above the p-type conductive layer to complete device manufacturing.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] First, the present invention uses a double heterojunction to control the on and off of the device, which can intrinsically realize the enhanced working state of the device without being affected by the material doping concentration.

[0028] Second, the present invention adopts a heterogeneous pn junction to bear the reverse voltage, which can make the heterogeneous second pn junction J2 perpendicular to the reverse electric field, significantly reduce the reverse leakage current of the device, and improve the voltage resistance of the device.

[0029] Third, the present invention adopts a planar gate structure, which can increase the safe operating range of the device, avoid etching damage, and simplify the preparation process.

[0030] Fourthly, the present invention adopts high-resistance Ga2O3 as the current blocking layer, which can effectively suppress device leakage and achieve a high switching ratio.

[0031] Fifth, the ohmic contact layer 4 of the present invention uses regrown highly doped n-type Ga2O3 material, which can form a good ohmic contact with the source electrode 7 and reduce the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of an existing heterojunction field effect transistor based on Ga2O3;

[0033] Figure 2 It is a schematic diagram of the structure of the device of the present invention;

[0034] Figure 3 The present invention is prepared Figure 2 Schematic diagram of the device process flow. DETAILED DESCRIPTION

[0035] In order to further illustrate the device structure described in the present invention, the following is a detailed description of the device structure based on NiO in combination with the accompanying drawings and specific embodiments. x The enhancement mode planar gate vertical bipolar transistor based on Ga2O3 double heterojunction is described in further detail.

[0036] Reference Figure 2The device structure of this example includes a substrate 1, a drift region 2, a current blocking layer 3, an ohmic contact layer 4, a p-type conductive layer 5, a drain electrode 6, a source electrode 7 and a gate electrode 8. Wherein:

[0037] The substrate 1 is n-type highly doped Ga2O3, and its thickness is T sub ≥300um, doping concentration N d,sub =1×10 17 ≤N d,sub ≤1×10 20 cm -3 , as the support bottom of the device, reducing the on-resistance.

[0038] The drift region 2 is n-type low-doped Ga2O3, located above the n-type high-doped Ga2O3 substrate 1, with a thickness of T drift 1≤T sub ≤30000nm, doping concentration N d,drift 1×10 15 ≤N d,drift ≤1×10 17 cm -3 , which serves as the main voltage-withstanding area of ​​the device and is used to improve the voltage-withstanding capability of the device.

[0039] The current blocking layer 3 is made of high resistivity Ga2O3 and is located on the left and right sides of the drift region 2. Its thickness is T block 1≤T block ≤1000nm, resistivity ρ block is block ≥1×10 3 Ω·cm to block the flow of current and control the flow path of current.

[0040] The ohmic contact layer 4 is n-type highly doped Ga2O3 and is located above the current blocking layer 3. Its thickness is T ohmic 1≤T ohmic ≤2000nm, doping concentration N d,ohmic N d,ohmic ≥1×10 16 cm -3 , so as to form a good ohmic contact with the source electrode 7 and reduce the on-resistance.

[0041] The p-type conductive layer 5 is p-type NiO x , located above the drift region 2, with a thickness of T pNiO 1≤T pNiO ≤2000nm, doping concentration N d,pNiO N d,pNiO ≥1×10 17 cm -3The left and right sides thereof form a first heterogeneous pn junction J1 with the ohmic contact layer 4 for controlling the conduction of the device; the lower part thereof forms a second heterogeneous pn junction J2 with the drift region 2 for improving the voltage resistance of the device.

[0042] The drain electrode 6 is an ohmic electrode, which is located on the back side of the substrate 1. The metal used for the drain electrode 6 is any one of Ti, Al, Ni, Au, W, Cr, Ta, Mo, TiC, TiN, and TiW, or any combination of several of them.

[0043] The source electrode 7 is an ohmic electrode, which is located above the ohmic contact layer 4. The metal used by the source electrode 7 is any one of Ti, Al, Ni, Au, W, Cr, Ta, Mo, TiC, TiN, and TiW, or any combination of several of them.

[0044] The gate electrode 8 is an ohmic electrode, located above the p-type conductive layer 5, forming a positive gate structure to directly control the conduction of the p-type conductive layer from above, so as to increase the safe working area and simplify the device manufacturing process. The metal used for the gate electrode 8 is any one of Ni, Au, Pt, Cr, Ta, Mo, TiC, TiN, and TiW, or any combination of several of them.

[0045] Reference Figure 3 The present invention provides a method for preparing NiO-based x Three embodiments of an enhancement-mode planar-gate vertical bipolar transistor with a Ga2O3 / Ga2O3 double heterojunction.

[0046] Example 1: The current blocking layer is prepared by ion implantation of N and the doping concentration of the ohmic contact layer is 1×10 17 cm -3 , the doping concentration of the p-type conductive layer is 1×10 19 cm -3 , the p-type conductive layer and the ohmic contact layer are both 500nm thick NiO x Enhancement-mode planar-gate vertical bipolar transistor based on Ga2O3 double heterojunction.

[0047] Step 1: Select a sample and clean it. Figure 3 a.

[0048] The thickness of the n-type Ga2O3 substrate is 500 μm and the doping concentration is 3×10 18 cm -3 The thickness of the n-type Ga2O3 drift region is 10um and the doping concentration is 1×10 16 cm -3 n-type Ga2O3 epitaxial wafer 1;

[0049] The selected Ga2O3 epitaxial wafer 1 was placed in acetone, isopropanol, and deionized water for ultrasonic cleaning for 5 minutes each.

[0050] The Ga2O3 epitaxial wafer 1 was cleaned with deionized water and blown dry with nitrogen.

[0051] Step 2: Perform N ion implantation on the epitaxial wafer 1 to form a current blocking layer 3.

[0052] The cleaned Ga2O3 sample is photolithographically exposed to expose the ion implantation area, such as Figure 3 b. The parameters for the four N ion implantations are:

[0053] First time: the ion incident angle was 7 degrees, the ion implantation energy was 300 keV, and the ion implantation dose was 2.5×10 13 cm -2 ,

[0054] Second time: the ion incident angle was 7 degrees, the ion implantation energy was 160 keV, and the ion implantation dose was 1.5×10 13 cm -2 ,

[0055] The third time: the ion incident angle was 7 degrees, the ion implantation energy was 80 keV, and the ion implantation dose was 9×10 12 cm -2 ,

[0056] The fourth time: the ion incident angle is 7 degrees, the ion implantation energy is 30 keV, and the ion implantation dose is 4×10 12 cm -2 ;

[0057] A current blocking layer 3 with a depth of 500 nm is formed on both sides of the drift region 2 by ion implantation technology. Figure 3 c.

[0058] Step 3, MOCVD grows Ga2O3 to prepare an ohmic contact layer 4, such as Figure 3 d.

[0059] The process conditions were set as follows: the reaction chamber temperature was 900 °C, the Ga source flow rate was 160 μmol / min, the doping atomic Si source flow rate was 5 μmol / min, and the O source flow rate was 300 sccm. Metal organic chemical vapor deposition technology was used to deposit a doping concentration of 1×10 17 cm -3 The Ga2O3 with a thickness of 500nm is removed by a stripping process to form an ohmic contact layer 4.

[0060] Step 4, magnetron sputtering NiO x A p-type conductive layer 5 is prepared.

[0061] The cleaned Ga2O3 sample is subjected to photolithography to expose the p-type conductive layer 5 region, such as Figure 3 e;

[0062] The process conditions were set as follows: magnetron sputtering power of 50 W, reaction chamber temperature of 25 °C, Ar flow rate of 140 sccm, and O2 flow rate of 20 sccm. Magnetron sputtering technology was used to deposit a hole concentration of 1×10 19 cm -3 500nm thick p-type NiO x , remove the excess NiO through the stripping process x , forming a p-type conductive layer 5, such as Figure 3 f.

[0063] Step 5: Rapid annealing to improve the quality of the current blocking layer 3 , the ohmic contact layer 4 and the p-type conductive layer 5 .

[0064] The process conditions of annealing atmosphere being O2, annealing temperature being 800°C, and annealing time being 30 min were set, and the sample was annealed using rapid thermal annealing technology to improve the current blocking ability of the current blocking layer 3 and improve the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5.

[0065] Step 6, preparing the drain electrode 6 by electron beam evaporation, such as Figure 3 g.

[0066] Set the high voltage to 7.5 kV, the Ti / Au current to 80 / 150 mA, and the pressure to 1×10 -5 Under the process conditions of 200 Å to 400 Å, metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are sequentially deposited on the back of the gallium oxide substrate by electron beam evaporation technology to form a drain electrode 6 .

[0067] Step 7, preparing source electrode 7 by electron beam evaporation, such as Figure 3 i.

[0068] Photolithography is performed on the Ga2O3 sample to expose the source electrode region, such as Figure 3 h, set the high voltage to 7.5 kV, the Ti / Au current to 80 / 150 mA, and the pressure to 1×10 -5 Under the process conditions of 1000 Å to 2000 Å, metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are deposited on the surface of gallium oxide in sequence by electron beam evaporation technology; excess Ti / Au in other parts is removed by a stripping process to form a source electrode 7.

[0069] Step 8: Rapid annealing to improve the ohmic contact quality of the drain electrode 6 and the source electrode 7.

[0070] The process conditions of annealing atmosphere being N2, annealing temperature being 450°C, and annealing time being 1 min were set, and the sample was annealed using rapid thermal annealing technology to improve the ohmic contact quality between the drain electrode 6 and the Ga2O3 substrate and the ohmic contact quality between the source electrode 7 and the ohmic contact layer.

[0071] Step 9: preparing the gate electrode 8 by electron beam evaporation.

[0072] The Ga2O3 sample is photolithographically exposed to expose the gate electrode region, such as Figure 3 j;

[0073] Set the high voltage to 7.5 kV, the Ni / Au current to 100 / 150 mA, and the pressure to 1×10 -5 Torr process conditions, using electron beam evaporation technology to deposit 50nm thick metal Ni and 150nm thick metal Au on the surface of gallium oxide, and then remove the excess Ni / Au in other parts through a stripping process to form a gate electrode 8, completing the device preparation, such as Figure 3 k.

[0074] Example 2: The current blocking layer is prepared by ion implantation of Mg, and the doping concentration of the ohmic contact layer is 1×10 18 cm -3 , the doping concentration of the p-type conductive layer is 1×10 20 cm -3 , the p-type conductive layer and the ohmic contact layer are both 700nm thick NiO x Enhancement-mode planar-gate vertical bipolar transistor based on Ga2O3 double heterojunction.

[0075] Step 1: Select a sample and clean it.

[0076] The thickness of the n-type Ga2O3 substrate is 650 μm and the doping concentration is 1×10 18 cm -3 The thickness of the n-type Ga2O3 drift region is 20um and the doping concentration is 1×10 16 cm -3 n-type Ga2O3 epitaxial wafer 2;

[0077] The selected Ga2O3 epitaxial wafer 2 was placed in acetone, isopropanol, and deionized water for ultrasonic cleaning for 5 minutes each.

[0078] The Ga2O3 epitaxial wafer 2 was cleaned with deionized water and dried with nitrogen.

[0079] Step 2: Mg ion implantation is performed on the epitaxial wafer 2 to form a current blocking layer 3, such as Figure 3 b and Figure 3 c.

[0080] 2.1) Photolithography of Ga2O3 samples to expose the current blocking layer area.

[0081] 2.2) The sample is placed in the cavity of an ion implanter, and ion implantation is performed on the two side regions above the drift region under the following process conditions of sequentially implanting Mg ions to prepare a current blocking layer 3 with a depth of 500 nm, namely:

[0082] First time: the ion incident angle was 7 degrees, the ion implantation energy was 380 keV, and the ion implantation dose was 3×10 13 cm -2 ,

[0083] Second time: the ion incident angle is 7 degrees, the ion implantation energy is 200 keV, and the ion implantation dose is 1.5×10 13 cm -2 ,

[0084] The third time: the ion incident angle was 7 degrees, the ion implantation energy was 130 keV, and the ion implantation dose was 7×10 12 cm -2 ,

[0085] The fourth time: the ion incident angle is 7 degrees, the ion implantation energy is 40 keV, and the ion implantation dose is 3×10 12 cm -2 ,

[0086] Step 3: grow Ga2O3 on the current blocking layer to prepare an ohmic contact layer 4, such as Figure 3 d.

[0087] Metal organic chemical vapor deposition technology was used to deposit a layer of doping concentration of 1×10 on the sample surface under the process conditions of a reaction chamber temperature of 900°C, a Ga source flow rate of 150 μmol / min, a doping atomic Si source flow rate of 50 μmol / min, and an O source flow rate of 300 sccm. 18 cm -3 The Ga2O3 with a thickness of 700nm is removed by a stripping process to form an ohmic contact layer 4.

[0088] Step 4: prepare a p-type conductive layer 5, such as Figure 3 e and Figure 3 f.

[0089] 4.1) Photolithography is performed on the cleaned Ga2O3 sample to expose the p-type conductive layer area;

[0090] 4.2) Using magnetron sputtering technology, under the process conditions of magnetron sputtering power of 30W, reaction chamber temperature of 25℃, Ar flow rate of 90sccm, and O2 flow rate of 30sccm, a hole concentration of 1×10 20 cm -3 700nm thick p-type NiO x , and then remove the excess NiO from other parts through the stripping process x , forming a p-type conductive layer 5.

[0091] Step five: rapid annealing to improve the quality of the current blocking layer 3 , the ohmic contact layer 4 and the p-type conductive layer 5 .

[0092] The sample is annealed using rapid thermal annealing technology under the process conditions of an annealing atmosphere of O2, an annealing temperature of 800°C, and an annealing time of 60 minutes to improve the current blocking ability of the current blocking layer 3 and improve the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5.

[0093] Step 6: Prepare the drain electrode 6 by electron beam evaporation, such as Figure 3 g.

[0094] Using electron beam evaporation technology, the high voltage is 7.5kV, the Ti / Au current is 80 / 150mA, and the pressure is 1×10 -5 Under the process conditions of 200 Å to 400 Å, metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are sequentially deposited on the back of the gallium oxide substrate to form a drain electrode 6 .

[0095] Step 7: Prepare source electrode 7 by electron beam evaporation, such as Figure 3 h and Figure 3 i.

[0096] 7.1) Perform photolithography on the Ga2O3 sample to expose the source electrode region;

[0097] 7.2) Using electron beam evaporation technology, the high voltage is 7.5kV, the Ti / Au current is 80 / 150mA, and the pressure is 1×10 - 5 Under the process condition of 200 Å to 1000 Å, metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are sequentially deposited on the surface of gallium oxide, and the excess Ti / Au in other parts are removed by a stripping process to form a source electrode 7.

[0098] Step eight, rapid annealing to improve the ohmic contact quality of the drain electrode 6 and the source electrode 7.

[0099] The sample was annealed using rapid thermal annealing technology under the process conditions of annealing atmosphere of N2, annealing temperature of 450°C, and annealing time of 1 min to improve the ohmic contact quality between the drain electrode 6 and the Ga2O3 substrate and the ohmic contact quality between the source electrode 7 and the ohmic contact layer.

[0100] Step nine: prepare the gate electrode 8 by electron beam evaporation, such as Figure 3 j and Figure 3 k.

[0101] 9.1) Perform photolithography on the Ga2O3 sample to expose the gate electrode region;

[0102] 9.2) Using electron beam evaporation technology, the high voltage is 7.5kV, the Ni / Au current is 100 / 150mA, and the pressure is 1×10 -5 Under the process conditions of 1.3 Å to 2.5 Å, metal Ni with a thickness of 50 nm and metal Au with a thickness of 150 nm are sequentially deposited on the surface of gallium oxide, and then the excess Ni / Au in other parts are removed by a stripping process to form a gate electrode 8, thereby completing the device preparation.

[0103] Example 3: The current blocking layer is prepared by ion implantation of N and P, and the doping concentration of the ohmic contact layer is 1×10 18 cm -3 , the doping concentration of the p-type conductive layer is 5×10 19 cm -3 , the p-type conductive layer and the ohmic contact layer are both 300nm thick NiO x Enhancement-mode planar-gate vertical bipolar transistor based on Ga2O3 double heterojunction.

[0104] Step A: Select a substrate and clean it.

[0105] The thickness of the n-type Ga2O3 substrate is 300 μm and the doping concentration is 2×10 18 cm -3 The thickness of the n-type Ga2O3 drift region is 15um and the doping concentration is 1×10 16 cm -3 n-type Ga2O3 epitaxial wafer 3; the selected Ga2O3 epitaxial wafer 3 is sequentially placed in acetone, isopropanol, and deionized water for ultrasonic cleaning for 5 minutes each, then cleaned with deionized water and dried with nitrogen.

[0106] Step B, N and P ion implantation is performed on the epitaxial wafer 2 to form a current blocking layer 3, such as Figure 3 b and Figure 3 c.

[0107] The Ga2O3 sample was photolithographically exposed to expose the current blocking layer area. Using ion implantation technology, the sample was placed in the ion implantation machine cavity, and N and P ion implantation was performed four times in sequence on the two sides of the drift region to form a current blocking layer 3 with a depth of 500nm. The ion implantation conditions were:

[0108] First time: N ion incident angle is 7 degrees, ion implantation energy is 300keV, and ion implantation dose is 2.5×10 13 cm -2 ; The P ion incident angle is 7 degrees, the ion implantation energy is 580keV, and the ion implantation dose is 3×10 13 cm -2 ;

[0109] Second time: N ion incident angle is 7 degrees, ion implantation energy is 160keV, and ion implantation dose is 1.5×10 13 cm -2 The P ion incident angle is 7 degrees, the ion implantation energy is 325 keV, and the ion implantation dose is 1.5×10 13 cm -2 ;

[0110] The third time: the N ion incident angle is 7 degrees, the ion implantation energy is 80 keV, and the ion implantation dose is 9×10 12 cm -2 ; The P ion incident angle is 7 degrees, the ion implantation energy is 150keV, and the ion implantation dose is 8×10 12 cm -2 ;

[0111] The fourth time: N ion incident angle is 7 degrees, ion implantation energy is 30keV, and ion implantation dose is 4×10 12 cm -2 ; The P ion incident angle is 7 degrees, the ion implantation energy is 50 keV, and the ion implantation dose is 4×10 12 cm -2 .

[0112] Step C, growing Ga2O3 on the current blocking layer 3 to prepare an ohmic contact layer 4, such as Figure 3 d.

[0113] Metal organic chemical vapor deposition technology was used to deposit a layer of doping concentration of 1×10 18 cm -3The Ga2O3 with a thickness of 300nm is removed by a stripping process to form an ohmic contact layer 4. The process conditions are: the reaction chamber temperature is 900℃, the Ga source flow rate is 150μmol / min, the doping atomic Si source flow rate is 50μmol / min, and the O source flow rate is 300sccm.

[0114] Step D, preparing a p-type conductive layer 5, such as Figure 3 e and Figure 3 f.

[0115] The cleaned Ga2O3 sample was photolithographically exposed to expose the p-type conductive layer area. Magnetron sputtering technology was used to deposit a hole concentration of 5×10 19 cm -3 300nm thick p-type NiO x , and then remove the excess NiO from other parts through the stripping process x , a p-type conductive layer 5 is formed, and the process conditions are: magnetron sputtering power is 30 W, reaction chamber temperature is 25° C., Ar flow rate is 90 sccm, and O2 flow rate is 30 sccm.

[0116] Step E: Rapid annealing to improve the quality of the current blocking layer 3 , the ohmic contact layer 4 and the p-type conductive layer 5 .

[0117] The sample is annealed using rapid thermal annealing technology to improve the current blocking ability of the current blocking layer 3 and the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5. The annealing conditions are: annealing atmosphere is N2, annealing temperature is 900°C, and annealing time is 30 minutes.

[0118] Step F, preparing the drain electrode 6 by electron beam evaporation, such as Figure 3 g.

[0119] By using electron beam evaporation technology, metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are sequentially deposited on the back of the gallium oxide substrate to form the drain electrode 6. The process conditions of the electron beam evaporation are: high voltage of 7.5 kV, Ti / Au current of 80 / 150 mA, pressure of 1×10 -5 Torr.

[0120] Step G, preparing the source electrode 7 by electron beam evaporation, such as Figure 3 h and Figure 3 i.

[0121] The Ga2O3 sample was photolithographically exposed to expose the source electrode region. Using electron beam evaporation technology, metal Ti with a thickness of 60nm and metal Au with a thickness of 150nm were deposited on the surface of gallium oxide in sequence. Then, the excess Ti / Au in other parts were removed by a stripping process to form the source electrode 7. The process conditions of the electron beam evaporation were: high voltage of 7.5kV, Ti / Au current of 80 / 150mA, and pressure of 1×10 -5 Torr.

[0122] Step H: Rapid annealing to improve the ohmic contact quality of the drain electrode 6 and the source electrode 7.

[0123] The sample was annealed using rapid thermal annealing technology to improve the ohmic contact quality between the drain electrode 6 and the Ga2O3 substrate and the ohmic contact quality between the source electrode 7 and the ohmic contact layer. The annealing conditions were: annealing atmosphere was N2, annealing temperature was 450°C, and annealing time was 1 min.

[0124] Step I: preparing the gate electrode 8 by electron beam evaporation, such as Figure 3 j and Figure 3 k.

[0125] The Ga2O3 sample was photolithographically exposed to expose the gate electrode region. Electron beam evaporation was used to deposit 50nm thick Ni and 150nm thick Au on the surface of gallium oxide. The process conditions were: high voltage of 7.5kV, Ni / Au current of 100 / 150mA, and pressure of 1×10 -5 Torr;

[0126] Then, the excess Ni / Au in other parts is removed by a stripping process to form a gate electrode 8, thus completing the device preparation.

[0127] The above descriptions are only three specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principle of the present invention, it is possible to make various modifications and changes in form and details without deviating from the principle and structure of the present invention. For example, in addition to using Ni, W, Pt, and Au metals, the gate electrode can also use any one or any combination of Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN, and TiW; in addition to using Ti, Al, Ni, TiN, and Au metals, the source electrode and the drain electrode can also use any one or a combination of two or more of Au, W, Cr, Ta, Mo, TiC, TiN, and TiW. However, the modifications and changes of these basic inventive ideas are still within the scope of protection of the claims of the present invention.

Claims

1. A NiO-based x A double heterojunction enhanced planar gate vertical bipolar transistor of Ga2O3, comprising a substrate (1), a drift region (2), a current blocking layer (3), an ohmic contact layer (4), a p-type conductive layer (5), a drain electrode (6), a source electrode (7) and a gate electrode (8), characterized in that: The current blocking layer (3) is made of high resistivity Ga2O3 material and is distributed on the left and right sides above the drift region (2) to block the flow of current and control the flow path of the current; The ohmic contact layer (4) is made of highly doped n-type Ga2O3 material to form a good ohmic contact with the source electrode (7), and is located above the current blocking layers (3) distributed on both sides; The p-type conductive layer (5) is made of p-type conductive material and is located above the middle of the drift region (2). Its left and right sides are in contact with the ohmic contact layers (4) distributed on both sides to form a first heterogeneous pn junction J1, and its bottom is in contact with the drift region to form a second heterogeneous pn junction J2, so as to improve the reverse withstand voltage capability of the device, and control the flow of electrons from the source electrode to the drain electrode through the two heterogeneous pn junctions to achieve an enhanced working state of the device; The gate electrode 8 is located above the p-type conductive layer 5, forming a planar gate structure that directly controls the conduction of the p-type conductive layer from above, so as to increase the safe operating area and simplify the device manufacturing process.

2. The transistor according to claim 1, characterized in that: The two source electrodes (7) are respectively located above the ohmic contact layers (4) on both sides, the gate electrode (8) is located above the p-type conductive layer (5), and the drain electrode (6) is located below the substrate (1).

3. The transistor according to claim 1, characterized in that: The substrate (1) is made of highly doped n-type Ga2O3 material to reduce the on-resistance of the device and play a role in supporting the device. Its thickness T sub ≥300um, doping concentration N d,sub =1×10 17 ≤N d,sub ≤1×10 20 cm -3 ; The drift region (2) is made of low-doped n-type Ga2O3 material and is used to connect the current blocking layer (3) and the p-type conductive layer (5). The thickness T drift =1≤T sub ≤30000nm, doping concentration N d,drift =1×10 15 ≤N d,drift ≤1×10 17 cm -3 .

4. The transistor according to claim 1, characterized in that: The current blocking layer (3) has a thickness T block =1≤T block ≤1000nm, resistivity ρ block is: block ≥1×10 3 Ω·cm; The ohmic contact layer (4) has a thickness T ohmic =1≤T ohmic ≤2000nm, doping concentration N d,ohmic For: N d,ohmic ≥1×10 16 cm -3 . The p-type conductive layer (5) has a thickness T pNiO =1≤T pNiO ≤2000nm, doping concentration N d,pNiO For: N d,pNiO ≥1×10 17 cm -3 .

5. The transistor according to claim 1, characterized in that: The high resistivity Ga2O3 material used in the current blocking layer (3) is any one of N, P, Mg, B, Al, Zn, Se, Fe, Cu, As, Sb, Be, Ca, Sr, and Ba, or a combination of any of them.

6. The transistor according to claim 1, characterized in that: The metal used for the drain electrode (6) is any one or a combination of any of Ti, Al, Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN, and TiW; The metal used for the source electrode (7) is any one or a combination of any of Ti, Al, Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN, and TiW; The metal used for the gate electrode (8) is any one of Ni, Au, Ti, Al, W, Cr, Ta, Mo, TiC, TiN, and TiW, or a combination of two or more thereof.

7. Preparation of NiO-based x / Ga2O3 double heterojunction enhanced planar gate vertical bipolar transistor method, characterized in that, The steps include: 1) Selecting a sample on which a Ga2O3 drift region (2) is epitaxially grown on a Ga2O3 substrate (1), and placing the sample in acetone, isopropanol, and deionized water in turn for ultrasonic cleaning; 2) transferring the sample to a photolithography operation table, photolithography a current blocking layer (3) region on the drift region (2), and then placing the sample into a reaction chamber of an ion implanter for ion implantation to form a current blocking layer (3); 3) Place the sample after ion implantation in the reaction chamber of the metal organic chemical vapor deposition system, and grow a layer of doping concentration not less than 1×10 16 cm -3 An n-type Ga2O3 ohmic contact layer is formed, and the regrown Ga2O3 on the photoresist is removed by a stripping process to form an ohmic contact layer (4) aligned with the current blocking layer; 4) The sample is transferred to a photolithography operation table, a p-type conductive layer (5) region is photolithographically formed on the sample surface, and a layer with a doping concentration of not less than 1×10 17 cm -3 p-type NiO x , and then remove the NiO above the photoresist through the stripping process x , forming a p-type conductive layer (5); 5) Placing the sample in a rapid thermal annealing furnace and subjecting the sample to rapid thermal annealing treatment to enhance the blocking ability of the current blocking layer and improve the re-grown n-type Ga2O3 ohmic contact layer and p-type NiO x Material quality of the conductive layer; 6) placing the sample with its back side facing upward in a reaction chamber of an electron beam evaporation deposition system, depositing a drain electrode metal on the back side of the substrate (1) using electron beam evaporation technology, and then transferring the sample to a photolithography operation table, and photolithographically carving out a source electrode region in the region of the ohmic contact layer (4); The sample is transferred again to the reaction chamber of the electron beam evaporation deposition system, a source electrode metal is deposited on the front side of the sample by using the electron beam evaporation technology, and the source electrode metal above the photoresist is removed by using the stripping process; 7) placing the sample in a rapid thermal annealing furnace and performing a rapid thermal annealing treatment on the sample to achieve ohmic contact between the drain electrode and the source electrode, reduce the ohmic contact resistance, and form a drain electrode (6) and a source electrode (7); 8) Transfer the sample to the photolithography operation station and x A gate electrode (8) region is photolithographically formed above the conductive layer, a layer of gate electrode metal is deposited on the sample surface using electron beam evaporation technology, and then a stripping process is used to remove the gate electrode metal above the photoresist to form a gate electrode (8) above the p-type conductive layer, thereby completing device manufacturing.

8. The method according to claim 6, characterized in that: The ion implantation process has the following parameters: the number of implantations is 0-20 times, and the single implantation dose is 0-1×10 14 cm -2 , the single injection energy is 0-500keV, and the injection angle is 0-90 degrees each time; The metal organic chemical vapor deposition process has the following condition parameters: the flow rate of the Ga source is 0-300sccm, the flow rate of the O source is 0-300sccm, the doping impurities are any one of Si, Ge, Sn or any combination of several, the impurity flow rate is 0-300sccm, and the chamber pressure is 0-200mTorr.

9. The method according to claim 6, characterized in that: The magnetron sputtering process has the following parameters: magnetron sputtering power is 10-300W, magnetron sputtering temperature is 0-200°C, Ar flow rate is 0-300sccm, O2 flow rate is 0-300sccm; The electron beam evaporation process has the following parameters: the electron gun voltage is 5000-13000V, the current intensity is 30-200mA, the deposition chamber pressure is 1×10 -7 -1×10 -5 Torr, the deposition rate is 10. The method according to claim 6, characterized in that: The rapid thermal annealing process in step 5) and step 7) is implemented by a rapid annealing furnace, and the process parameters are as follows: Step 5) The condition parameters are: annealing temperature is 600-1200°C, annealing atmosphere is N2, O2 or vacuum, and annealing time is 20-120 minutes; Step 7) The condition parameters are: annealing temperature is 300-600° C., annealing atmosphere is N2, and annealing time is 30-180 seconds.

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