Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate which comprises an array region and a peripheral region; forming a first mask layer on the substrate, and forming a first mask pattern right above the array region and the peripheral region in the first mask layer; and forming an array pattern in the array region based on the first mask pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In order to meet the demand for high integration of memory devices, it has been proposed to form array patterns through a self-aligned double patterning (SADP) process and a self-aligned quadruple patterning (SAQP) process.

[0003] However, as the integration level of memory devices is further improved, the cell size (pitch) of the array pattern is continuously reduced. In the process of forming the array pattern by using the SADP process and the SAQP process, there are still many problems to be solved. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising an array region and a peripheral region;

[0008] forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer;

[0009] An array pattern is formed in the array region based on the first mask pattern.

[0010] In an optional embodiment, the unit size of the first mask pattern directly above the array region is a first size, and the unit size of the first mask pattern directly above the peripheral region is a second size;

[0011] The first size is greater than or equal to the second size.

[0012] In an optional embodiment, the ratio of the first size to the second size ranges from 1 to 1.2.

[0013] In an optional embodiment, the method further includes: forming a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer directly above the array area, and excluding the second mask pattern directly above the peripheral area.

[0014] In an optional implementation, forming an array pattern in the array area based on the first mask pattern includes:

[0015] An array pattern is formed in the array region based on the first mask pattern and the second mask pattern, and the array pattern is not formed in the peripheral region.

[0016] In an optional implementation, forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer includes:

[0017] forming a first mask layer, a third mask layer, a fourth mask layer, and a first photoresist layer on the substrate; the first photoresist layer includes a third mask pattern located directly above the array region and directly above the peripheral region;

[0018] forming a fourth mask pattern in the fourth mask layer located directly above the array region and directly above the peripheral region based on the third mask pattern;

[0019] forming a first dielectric layer on the sidewalls of the fourth mask pattern, and removing the fourth mask pattern;

[0020] The third mask layer is etched using the first dielectric layer as a mask to form a fifth mask pattern directly above the array region and directly above the peripheral region.

[0021] In an optional embodiment, the forming of a first mask pattern located directly above the array region and the peripheral region in the first mask layer further includes:

[0022] forming a second dielectric layer on the sidewalls of the fifth mask pattern;

[0023] The first mask layer is etched using the second dielectric layer as a mask to form the first mask pattern directly above the array region and directly above the peripheral region; and the remaining portion of the second dielectric layer is formed on the first mask pattern.

[0024] In an optional embodiment, the method further includes:

[0025] A first filling layer is formed at least between the gaps of the first mask pattern and the gaps of the second dielectric layer remaining on the first mask pattern; the first filling layer directly above the array area is flush with the first filling layer directly above the peripheral area.

[0026] In an optional embodiment, the method further includes:

[0027] Etching the first filling layer and removing the second dielectric layer remaining on the first mask pattern to form a first groove;

[0028] forming a second filling layer in the first groove;

[0029] Parts of the first filling layer and the second filling layer are removed, so that the first filling layer directly above the array region is flush with the first filling layer directly above the peripheral region, and the first mask pattern is exposed.

[0030] In an optional implementation manner, etching the first filling layer includes:

[0031] The first filling layer is etched by a dry etching process.

[0032] In an optional embodiment, the material of the second filling layer is the same as that of the first filling layer.

[0033] In an optional embodiment, the forming of a second mask layer on the first mask layer, and forming a second mask pattern located directly above the array region in the second mask layer, and the second mask pattern is not included directly above the peripheral region, comprises:

[0034] A second mask layer and a fifth mask layer are sequentially formed on the first mask layer directly above the array region and directly above the peripheral region, and a second photoresist layer is formed on the fifth mask layer directly above the array region; the second photoresist layer includes a sixth mask pattern;

[0035] etching the fifth mask layer based on the sixth mask pattern to form a seventh mask pattern, and removing the fifth mask layer directly above the peripheral region;

[0036] A third dielectric layer is formed on the sidewalls and the top surface of the seventh mask pattern, between two adjacent units of the seventh mask pattern, and on the second mask layer directly above the peripheral region.

[0037] In an optional embodiment, the array region includes a boundary region close to the peripheral region; the second mask layer is formed on the first mask layer, and a second mask pattern is formed in the second mask layer directly above the array region, and the second mask pattern is not included directly above the peripheral region, and further includes:

[0038] forming a third photoresist layer on the third dielectric layer directly above the boundary region and the peripheral region;

[0039] Based on the third photoresist layer, the third dielectric layer, and the seventh mask pattern, the second mask layer is etched to form a second mask pattern in the second mask layer.

[0040] In an optional embodiment, before forming the first mask layer on the substrate, the forming method further includes:

[0041] forming an amorphous carbon layer on the substrate;

[0042] The forming of the array pattern in the array region based on the first mask pattern and the second mask pattern and not forming the array pattern in the peripheral region comprises:

[0043] Etching the amorphous carbon layer using the first mask pattern and the second mask pattern as masks, and transferring a pattern formed by overlapping the first mask pattern and the second mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer;

[0044] The substrate is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form an array pattern in the array region, and the array pattern is not formed in the peripheral region.

[0045] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure is obtained by the method for forming a semiconductor structure in any of the aforementioned embodiments.

[0046] In the technical solution provided in the present disclosure, by forming a first mask pattern directly above both the array area and the peripheral area, the difference in patterns directly above the peripheral area and directly above the array area is reduced, thereby reducing the load effect of the peripheral area and the array area in the process of forming the array pattern. The uniformity of the array pattern in the array area can be improved, and the possibility of abnormalities in the array pattern can be effectively reduced. In addition, the formation of redundant patterns in the peripheral area can be avoided, and the peripheral area can be avoided from being damaged, thereby improving the reliability of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figures 1 to 5 A schematic diagram of the structure of the array pattern forming process provided by an embodiment of the present disclosure;

[0048] Figure 6 A schematic diagram of a top view structure of an array pattern provided in an embodiment of the present disclosure;

[0049] Figure 7 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Figures 8 to 23 A structural schematic diagram of a semiconductor structure formation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0053] In the drawings, like reference numerals refer to like elements throughout.

[0054] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] In the related art, it has been proposed to form a capacitor hole array with a small unit size and a large aspect ratio (AR) by using the SADP process and the SAQP process. However, as the integration of storage devices is further improved, the unit size of the array pattern continues to shrink. In the process of forming the array pattern by using the SADP process and the SAQP process, the load effect becomes more and more serious, resulting in anomalies at the boundaries of the array pattern in the array area and causing certain damage to the peripheral area.

[0057] Figures 1 to 5 FIG. 1 is a schematic diagram of a semiconductor structure forming process according to an embodiment of the present disclosure. Figure 1 , providing a substrate 1, the substrate 1 includes an array region and a peripheral region, a mask layer 2 is formed on the substrate 1, and a mask pattern 3 is formed on the mask layer 2. Figure 2 , a filling layer 4 covering the mask pattern 3 is formed on the mask layer 2. Figure 3 , remove part of the filling layer 4 so that the top surface of the mask pattern 3 is exposed. Figure 4 , a mask layer 5 is formed on the filling layer 4, and a mask pattern 6 is formed on the mask layer 5. Figure 5 , the mask pattern 6 and the mask pattern 3 are transferred to the substrate 1 , thereby forming an array pattern 7 in the substrate 1 .

[0058] In the process of forming the above array pattern 7, since there is a mask pattern 3 directly above the array area, but no mask pattern 3 is formed directly above the peripheral area, there will be a large load effect in the process of spin coating to form the filling layer 4, so that each unit in the mask pattern 3 formed directly above the array area has asymmetry, and finally the array pattern formed in the array area appears as follows: Figure 6 The distortion shown will further affect the formation of the capacitor hole array in the subsequent steps. In addition, the pattern difference between the array area and the peripheral area will also cause the height of the filling layer 4 to be greatly different between the height of the filling layer 4 above the array area and the height of the filling layer 4 above the peripheral area, and the height of the filling layer 4 near the peripheral area above the array area and the filling layer 4 far from the peripheral area also have a certain difference, as shown in the following figure. Figure 2 As shown, the height of the filling layer 4 directly above the array area far from the peripheral area is higher, the height of the filling layer 4 directly above the array area close to the peripheral area is second, and the height of the filling layer 4 directly above the peripheral area is the lowest, so that Figure 3 After removing part of the filling layer 4 as shown, the height of the remaining filling layer 4 above the array area and the peripheral area will also be different, so that the following will occur during the formation of the array pattern 7: Figure 5 The peripheral area shown also forms an unnecessary pattern, causing some damage to the peripheral area.

[0059] Based on the above problems, how to optimize the formation process of the array pattern and reduce the load effect has become an urgent problem to be solved. In this regard, the present disclosure proposes the following implementation methods.

[0060] The present disclosure provides a method for forming a semiconductor structure. Figure 7 The following is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 7 As shown, the method for forming a semiconductor structure includes the following steps:

[0061] Step S101: providing a substrate, the substrate comprising an array region and a peripheral region;

[0062] Step S102: forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer;

[0063] Step S103: forming an array pattern in the array region based on the first mask pattern.

[0064] Figures 8 to 23 The structure diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is as follows. Figure 7 , Figures 8 to 23 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0065] Reference Figure 8 First, a substrate 101 is provided, and the substrate 101 includes an array area a and a peripheral area b.

[0066] In some embodiments, providing the substrate 101 includes: forming a metal layer; forming a stacked structure in which a sacrificial layer and a supporting layer are overlapped and arranged along the Z direction on the metal layer ( Figure 8 A polysilicon layer 134 and an oxide layer 125 are formed on the stack structure. The oxide layer 125 is a target etching layer for forming an array pattern.

[0067] In some specific examples, the material of the metal layer includes but is not limited to tungsten; the material of the supporting layer includes but is not limited to silicon oxide; the material of the sacrificial layer includes but is not limited to silicon nitride; the material of the oxide layer 125 includes but is not limited to doped silicon oxide, for example, phosphorus-doped silicon oxide, phosphorus-boron-doped silicon oxide.

[0068] The following will be combined Figure 8-Figure 17 The process of forming the first mask pattern is introduced in detail.

[0069] In some embodiments, reference Figure 8-Figure 9 , forming a first mask pattern located directly above the array region a and the peripheral region b in the first mask layer, including:

[0070] A first mask layer 102, a third mask layer 107, a fourth mask layer 108, and a first photoresist layer 109 are formed on a substrate 101; the first photoresist layer 109 includes a third mask pattern 110 located directly above the array region a and directly above the peripheral region b;

[0071] Based on the third mask pattern 110 , a fourth mask pattern 111 is formed in the fourth mask layer 108 directly above the array region a and directly above the peripheral region b.

[0072] It can be understood that the first photoresist layer 109 in the embodiment of the present disclosure includes a third mask pattern 110 located directly above the array area a and directly above the peripheral area b. That is, the third mask pattern 110 is formed directly above the array area a and directly above the peripheral area b. In this way, the difference in pattern density directly above the peripheral area b and directly above the array area a is relatively reduced, thereby reducing the load effect in the process of forming the array pattern directly above the peripheral area b and directly above the array area a.

[0073] In the embodiment of the present disclosure, the fourth mask layer 108 includes a first sub-mask layer 128 and a second sub-mask layer 129 arranged in sequence along the Z direction, and the third mask layer 107 includes a third sub-mask layer 126 and a fourth sub-mask layer 127 arranged in sequence along the Z direction. First, a first photoresist layer 109 including a third mask pattern 110 is formed on the second sub-mask layer 129, and the second sub-mask layer 129 and the first sub-mask layer 128 are etched using the first photoresist layer 109 including the third mask pattern 110 as a mask to form a fourth mask pattern 111 in the first sub-mask layer 128 and the second sub-mask layer 129. In this process, the fourth sub-mask layer 127 serves as an etching stop layer, so that the opening formed by etching the fourth mask layer 108 can stop on the fourth sub-mask layer 127.

[0074] In some specific examples, the material of the first mask layer 102 includes but is not limited to silicon-rich silicon oxynitride; the material of the third sub-mask layer 126 includes but is not limited to amorphous carbon; the material of the fourth sub-mask layer 127 includes but is not limited to silicon oxide; the material of the first sub-mask layer 128 includes but is not limited to spin-on hard mask (SOH) material (for example, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.); the material of the second sub-mask layer 129 includes but is not limited to silicon oxynitride.

[0075] In some specific examples, the first mask layer 102, the first sub-mask layer 128, the second sub-mask layer 129, the third sub-mask layer 126 and the fourth sub-mask layer 127 can be formed by a deposition process or a spin coating process, and the first sub-mask layer 128 and the second sub-mask layer 129 can be etched by a dry etching process.

[0076] In the embodiments of the present disclosure, deposition processes include but are not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD); spin coating processes include but are not limited to spin-on dielectrics (SOD) processes; dry etching processes include but are not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE) and reactive ion etching (RIE).

[0077] Next, refer to Fig.10 , Fig.11 , a first dielectric layer 112 is formed on the sidewall of the fourth mask pattern 111, and the fourth mask pattern 111 is removed; the third mask layer 107 is etched using the first dielectric layer 112 as a mask, and a fifth mask pattern 113 is formed directly above the array area a and directly above the peripheral area b.

[0078] In some specific examples, a first dielectric layer 112 can be first formed on the surface of the fourth sub-mask layer 127, the sidewalls of the fourth mask pattern 111, and the top surface of the fourth mask pattern 111, and the first dielectric layer 112 on the top surface of the fourth mask pattern 111, the first dielectric layer 112 on the surface of the fourth sub-mask layer 127, and the fourth mask pattern 111 are removed, and the first dielectric layer 112 on the sidewalls of the fourth mask pattern 111 is retained. The remaining first dielectric layer 112 constitutes a spacer, and the unit size of the spacer is half of the unit size of the fourth mask pattern 111.

[0079] In some specific examples, the first dielectric layer 112 can be etched using an anisotropic etching process, and the anisotropic etching process includes but is not limited to a plasma etching process with high selectivity. When etching away the first dielectric layer 112 on the top surface of the fourth mask pattern 111 and the first dielectric layer 112 on the surface of the fourth sub-mask layer 127, the first dielectric layer 112 on the side wall of the fourth mask pattern 111 may not be laterally etched.

[0080] In some embodiments, reference Fig.12 , Fig.13 , forming a first mask pattern 103 located directly above the array area a and the peripheral area b in the first mask layer 102, and also including: forming a second dielectric layer 114 on the sidewall of the fifth mask pattern 113; etching the first mask layer 102 using the second dielectric layer 114 as a mask to form the first mask pattern 103 directly above the array area a and directly above the peripheral area b; and the remaining portion of the second dielectric layer 114 on the first mask pattern 103.

[0081] In some specific examples, a second dielectric layer 114 may be first formed on the surface of the first mask layer 102, the sidewalls of the fifth mask pattern 113, and the top surface of the fifth mask pattern 113, and the second dielectric layer 114 on the top surface of the fifth mask pattern 113, the second dielectric layer 114 on the surface of the first mask layer 102, and the fifth mask pattern 113 may be removed, while the second dielectric layer 114 on the sidewalls of the fifth mask pattern 113 may be retained. The first mask layer 102 may then be etched using the remaining second dielectric layer 114 as a mask to obtain the first mask pattern 103.

[0082] In some specific examples, the first dielectric layer 112 and the second dielectric layer 114 may be formed by using an ALD process.

[0083] In some specific examples, the material of the first dielectric layer 112 and / or the second dielectric layer 114 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride.

[0084] It can be understood that in the embodiment of the present disclosure, the first mask pattern 103 is formed directly above the peripheral area b and the array area a, so that when the array pattern 104 is formed directly above the array area a and the peripheral area b, the difference in pattern density directly above the peripheral area and directly above the array area is reduced, thereby reducing the load effect of the array area a and the peripheral area b.

[0085] In some embodiments, the cell size of the first mask pattern 103 directly above the array region a is a first size, and the cell size of the first mask pattern 103 directly above the peripheral region b is a second size.

[0086] Here, the unit size of the mask pattern can be understood as the pitch of the mask pattern, that is, the size of a periodic pattern. The smaller the unit size, the greater the density of the pattern.

[0087] It is understandable that the unit size of the first mask pattern 103 directly above the array region a can be larger than the unit size of the first mask pattern 103 directly above the peripheral region b, or smaller than the unit size of the first mask pattern 103 directly above the peripheral region b, or the two can be equal. However, the difference between the first size and the second size cannot be too large. If it is too large, it means that the pattern density difference directly above the peripheral region b and directly above the array region a is large. When the first filling layer 115 and the second filling layer 116 are subsequently filled, the height difference between the first filling layer 115 and the second filling layer 116 formed on the peripheral region b and the array region a will be large, which will increase the difficulty of the subsequent process.

[0088] In some embodiments, the first size is greater than or equal to the second size.

[0089] In some embodiments, the ratio of the first dimension to the second dimension is in the range of 1-1.2.

[0090] It should be noted that the ratio range of the first size to the second size given in the above embodiment is only for illustrative purposes and is not intended to limit the ratio range of the first size to the second size in the embodiments of the present disclosure.

[0091] Here, the second size cannot be too small, otherwise it will lead to high process requirements; the second size cannot be too large, otherwise it will lead to a large difference between the first size and the second size, resulting in a large difference in height of the first filling layer 115 formed directly above the peripheral area b and directly above the array area a.

[0092] In some embodiments, the first size is equal to the second size.

[0093] It can be understood that when the first size is equal to the second size, the difference in pattern density between the first mask pattern 103 directly above the peripheral region b and the array region a is minimal, so that a better effect of reducing the load effect can be achieved.

[0094] In some embodiments, reference Fig.14 The method for forming a semiconductor structure also includes: forming a first filling layer 115 at least between the gaps in the first mask pattern 103 and the gaps in the second dielectric layer 114 remaining on the first mask pattern 103; the first filling layer 115 directly above the array area a is flush with the first filling layer 115 directly above the peripheral area b.

[0095] In some specific examples, the first filling layer 115 may be formed by using a spin coating process.

[0096] It can be understood that in the embodiment of the present disclosure, since the first mask pattern 103 is formed directly above the peripheral area b and directly above the array area a, the difference in pattern density between the array area a and the peripheral area b is small, so that the load effect directly above the array area a and the peripheral area b is small during the process of forming the first filling layer 115, so that a highly consistent first filling layer 115 can be formed in the peripheral area b and directly above the array area a, thereby reducing the load effect directly above the array area a and the peripheral area b in the subsequent process of forming the array pattern.

[0097] In some specific examples, such as Fig.14 As shown, a portion of the first filling layer 115 is also formed on the second dielectric layer 114 .

[0098] In some embodiments, reference Figure 15-17 The method for forming the semiconductor structure also includes: etching the first filling layer 115 and removing the remaining second dielectric layer 114 on the first mask pattern 103 to form a first groove 117; forming a second filling layer 116 in the first groove 117; removing a portion of the first filling layer 115 and the second filling layer 116 so that the first filling layer 115 directly above the array area a is flush with the first filling layer 115 directly above the peripheral area b, and the first mask pattern 103 is exposed.

[0099] In some embodiments, etching the first filling layer 115 includes: etching the first filling layer 115 using a dry etching process.

[0100] In some specific examples, the first filling layer 115 may be etched by a dry etching process to expose the remaining second dielectric layer 114 , and then the remaining second dielectric layer 114 may be removed by an etching process.

[0101] In some specific examples, removing a portion of the first filling layer 115 and the second filling layer 116 includes: removing a portion of the first filling layer 115 and the second filling layer 116 by using a dry etching process.

[0102] In some specific examples, the materials of the first filling layer 115 and the second filling layer 116 include but are not limited to spin-on hard mask materials (eg, silicon hard mask materials, carbon hard mask materials, organic hard mask materials, etc.). The materials of the first filling layer 115 and the second filling layer 116 may be the same or different.

[0103] In some embodiments, the material of the first filling layer 115 is the same as the material of the second filling layer 116 .

[0104] It is understandable that the spin-coated hard mask material is a polymer material, and a first mask pattern 103 with a smaller size is formed in the first filling layer 115. If a chemical mechanical polishing (CMP) process is used, the first mask pattern 103 is directly formed on the first filling layer 115. Fig.14 Based on the above, a portion of the first filling layer 115 and the remaining second dielectric layer 114 are removed to obtain Fig.17 The structure shown will damage the first mask pattern 103 and cannot achieve the effect of making the first filling layer 115 directly above the array region a and the first filling layer 115 directly above the peripheral region b level with each other.

[0105] It can be understood that in the embodiment of the present disclosure, a first filling layer 115 is first formed, and then the first filling layer 115 is etched using a dry etching process and the remaining second dielectric layer 114 is removed, and then a second filling layer 116 made of the same material as the first filling layer 115 is formed, and a portion of the first filling layer 115 and the second filling layer 116 are removed using a dry etching process, so that the height of the first filling layer 115 directly above the array area a is flush with the height of the first filling layer 115 directly above the peripheral area b, thereby reducing the pattern difference between the array area a and the peripheral area a, and reducing the load effect between the array area a and the peripheral area b in the subsequent formation of the array pattern.

[0106] In some specific examples, such as Fig.16 As shown, when the second filling layer 116 is formed in the first groove 117 , a portion of the second filling layer 116 is also formed on the top of the first filling layer 115 .

[0107] In some specific examples, an etching process may be used to remove a portion of the first filling layer 115 and the second filling layer 116. After removing a portion of the first filling layer 115 and the second filling layer 116, as shown in FIG. Fig.17 As shown, the height of the first filling layer 115 is flush with the height of the first mask layer, and the height of the first filling layer 115 directly above the array region a and the peripheral region b is flush.

[0108] It can be understood that in the embodiment of the present disclosure, by reducing the difference in pattern density between directly above the peripheral area b and directly above the array area a, the load effect during the corresponding etching and filling directly above the peripheral area b and directly above the array area a is reduced, so that the height difference of the first filling layer 115 directly above the peripheral area b and directly above the array area a is smaller, which is beneficial to the subsequent formation of the array pattern.

[0109] In some embodiments, the method for forming a semiconductor structure further includes: forming a second mask layer on the first mask layer 102, and forming a second mask pattern in the second mask layer directly above the array region a, and excluding the second mask pattern directly above the peripheral region b.

[0110] Next, combine Figure 18-Figure 22 The formation process of the second mask pattern is introduced in detail.

[0111] In some embodiments, reference Figure 18-Figure 20 , forming a second mask layer 105 on the first mask layer 102, and forming a second mask pattern 106 located directly above the array region a in the second mask layer 105, and excluding the second mask pattern 106 directly above the peripheral region b, including:

[0112] A second mask layer 105 and a fifth mask layer 118 are sequentially formed on the first mask layer 102 directly above the array area a and directly above the peripheral area b, and a second photoresist layer 119 is formed on the fifth mask layer 118 directly above the array area a; the second photoresist layer 119 includes a sixth mask pattern 120; based on the sixth mask pattern 120, the fifth mask layer 118 is etched to form a seventh mask pattern 121, and the fifth mask layer 118 directly above the peripheral area b is removed; a third dielectric layer 122 is formed on the sidewall and top surface of the seventh mask pattern 121, between two adjacent units of the seventh mask pattern 121, and on the second mask layer 105 directly above the peripheral area b.

[0113] In some specific examples, the fifth mask layer 118 includes a fifth sub-mask layer 130, a sixth sub-mask layer 131, a seventh sub-mask layer 132, and an eighth sub-mask layer 133 arranged in sequence along the Z direction. The specific process of forming the seventh mask pattern 121 includes: etching the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 using the patterned second photoresist layer 119 as a mask, thereby forming the seventh mask pattern 121. The seventh mask pattern 121 can be formed by a SADP process, so that the unit size of the seventh mask pattern 121 is half of the unit size of the sixth mask pattern 120.

[0114] Here, since there is no second photoresist 119 covering the peripheral region b, the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 of the peripheral region b are all removed.

[0115] In some specific examples, the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 can be formed by a deposition process or a spin coating process, and the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 can be etched by a dry etching process.

[0116] In some specific examples, the material of the second mask layer 105 includes but is not limited to silicon-rich silicon oxynitride; the material of the fifth sub-mask layer 130 includes but is not limited to amorphous carbon; the material of the sixth sub-mask layer 131 includes but is not limited to silicon oxide; the material of the seventh sub-mask layer 132 includes but is not limited to spin-on hard mask materials (for example, silicon hard mask materials, carbon hard mask materials, organic hard mask materials, etc.); the material of the eighth sub-mask layer 133 includes but is not limited to silicon oxynitride.

[0117] In some specific examples, the material of the third dielectric layer 122 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride. The material of the third dielectric layer 122 and the first dielectric layer 112 and the second dielectric layer 114 may be the same or different.

[0118] In some specific examples, the third dielectric layer 122 may be formed by using an ALD process.

[0119] In some embodiments, reference Figure 21-22 , the array area a includes a junction area close to the peripheral area b; a second mask layer 105 is formed on the first mask layer 102, and a second mask pattern 106 is formed in the second mask layer 105 and is located directly above the array area a, and the second mask pattern 106 is not included directly above the peripheral area b, and also includes: forming a third photoresist layer 123 on the third dielectric layer 122 in the junction area and directly above the peripheral area b; based on the third photoresist layer 123, the third dielectric layer 122, and the seventh mask pattern 121, the second mask layer 105 is etched to form a second mask pattern 106 in the second mask layer 105.

[0120] In some specific examples, the height of the third photoresist layer 123 directly above the boundary region may be substantially flush with the height of the third photoresist layer 123 directly above the peripheral region b.

[0121] In some embodiments, reference Figure 22-Figure 23, forming an array pattern 104 in the array region a based on the first mask pattern 103, including: forming the array pattern 104 in the array region a based on the first mask pattern 103 and the second mask pattern 106, and not forming the array pattern 104 in the peripheral region b.

[0122] It can be understood that in the embodiment of the present disclosure, by reducing the difference in pattern density between the array area and the peripheral area, the height difference between the array area and the first filling layer directly above the peripheral area is reduced, and the height difference between the array area and the second mask layer directly above the peripheral area is reduced, so that when forming the array pattern, it is possible to avoid forming redundant patterns in the peripheral area and reduce damage to the peripheral area. In addition, the reduction in the difference in pattern density between the array area and the peripheral area reduces the load effect between the array area and the peripheral area, so that the array pattern formed in the array area is more uniform, and the situation of forming abnormal patterns (such as distortion) in the array pattern is improved.

[0123] In some embodiments, before forming the first mask layer 102 on the substrate 101, the method for forming a semiconductor structure also includes: forming an amorphous carbon layer 124 on the substrate 101; when forming the array pattern 104, the amorphous carbon layer 124 can be first etched using the first mask pattern 103 and the second mask pattern 106 as masks, and the pattern formed by the overlap of the first mask pattern 103 and the second mask pattern 106 is transferred to the amorphous carbon layer 124 directly above the array area a to form a patterned amorphous carbon layer 124; then the substrate 101 is etched using the patterned amorphous carbon layer 124 as a mask, and the remaining amorphous carbon layer 124 is removed to form the array pattern 104 in the array area a, and no array pattern 104 is formed in the peripheral area b.

[0124] In the embodiment of the present disclosure, in the process of transferring the pattern formed by the overlap of the first mask pattern 103 and the second mask pattern 106 to the amorphous carbon layer 124 directly above the array region a, since the first filling layer on the peripheral region is thicker, no opening penetrating the amorphous carbon layer 124 along the Z direction is formed in the amorphous carbon layer 124 directly above the peripheral region. In addition, when etching the oxide layer 125 in the substrate 101 using the patterned amorphous carbon layer 124 as a mask, the amorphous carbon layer 124 directly above the peripheral region b completely covers the oxide layer 125, which can prevent the oxide layer 125 in the peripheral region b from being etched, thereby avoiding the formation of redundant patterns in the peripheral region b.

[0125] In some embodiments, the method for forming a semiconductor structure further includes: forming a capacitor hole array in the stacked structure using the array pattern 104 as a mask.

[0126] It should be noted that the method for forming a semiconductor structure provided by the present disclosure can be applied not only to the formation process of a capacitor hole array, but also to the formation process of other array patterns with small unit sizes and large aspect ratios.

[0127] In the embodiments of the present disclosure, the number of minimum repeating units in each mask pattern is only an example, and the present disclosure does not limit the specific number of minimum repeating units in the mask pattern set directly above the array region a and the peripheral region b. In practical applications, the width of the peripheral region b in the X direction and the number of minimum repeating units in the mask pattern formed directly above the peripheral region b can be adjusted according to the density of the array pattern, thereby reducing the load effect in the array pattern formation process according to actual needs.

[0128] In the embodiment of the present disclosure, by forming the first mask pattern directly above both the array area and the peripheral area, the difference between the patterns directly above the peripheral area and directly above the array area is reduced, thereby reducing the load effect of the peripheral area and the array area in the process of forming the array pattern. The uniformity of the array pattern in the array area can be improved, and the possibility of abnormalities in the array pattern can be effectively reduced. In addition, the formation of redundant patterns in the peripheral area can be avoided, and the peripheral area can be avoided from being damaged, thereby improving the reliability of the semiconductor structure finally formed.

[0129] Based on the same concept as the above embodiments, the present disclosure also provides a semiconductor structure, which is manufactured by the semiconductor structure forming method in any of the above embodiments. The technical effects that can be achieved by the semiconductor structure forming method in any of the above embodiments can also be achieved by the semiconductor structure, which will not be described one by one here.

[0130] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0131] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer; An array pattern is formed in the array region based on the first mask pattern.

2. The forming method according to claim 1, It is characterized in that The cell size of the first mask pattern directly above the array region is a first size, and the cell size of the first mask pattern directly above the peripheral region is a second size; The first size is greater than or equal to the second size.

3. The forming method according to claim 2, It is characterized in that The ratio of the first size to the second size is in the range of 1-1.

2.

4. The forming method according to claim 1, It is characterized in that The method further includes: forming a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer that is located directly above the array region, and the second mask pattern is not included directly above the peripheral region.

5. The forming method according to claim 4, It is characterized in that The forming an array pattern in the array area based on the first mask pattern comprises: An array pattern is formed in the array region based on the first mask pattern and the second mask pattern, and the array pattern is not formed in the peripheral region.

6. The forming method according to claim 1, It is characterized in that The step of forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer comprises: forming a first mask layer, a third mask layer, a fourth mask layer, and a first photoresist layer on the substrate; the first photoresist layer includes a third mask pattern located directly above the array region and directly above the peripheral region; forming a fourth mask pattern in the fourth mask layer located directly above the array region and directly above the peripheral region based on the third mask pattern; forming a first dielectric layer on the sidewalls of the fourth mask pattern, and removing the fourth mask pattern; The third mask layer is etched using the first dielectric layer as a mask to form a fifth mask pattern directly above the array region and directly above the peripheral region.

7. The forming method according to claim 6, It is characterized in that The step of forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer further comprises: forming a second dielectric layer on the sidewalls of the fifth mask pattern; The first mask layer is etched using the second dielectric layer as a mask to form the first mask pattern directly above the array region and directly above the peripheral region; and the remaining portion of the second dielectric layer is formed on the first mask pattern.

8. The forming method according to claim 7, It is characterized in that The method further comprises: A first filling layer is formed at least between the gaps of the first mask pattern and the gaps of the second dielectric layer remaining on the first mask pattern; the first filling layer directly above the array area is flush with the first filling layer directly above the peripheral area.

9. The forming method according to claim 8, It is characterized in that The method further comprises: Etching the first filling layer and removing the second dielectric layer remaining on the first mask pattern to form a first groove; forming a second filling layer in the first groove; Part of the first filling layer and the second filling layer is removed, so that the first filling layer directly above the array region is flush with the first filling layer directly above the peripheral region, and the first mask pattern is exposed.

10. The forming method according to claim 9, It is characterized in that The etching of the first filling layer comprises: The first filling layer is etched by a dry etching process.

11. The forming method according to claim 9, It is characterized in that The material of the second filling layer is the same as that of the first filling layer.

12. The forming method according to claim 4, It is characterized in that The step of forming a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer directly above the array region, and excluding the second mask pattern directly above the peripheral region, comprises: A second mask layer and a fifth mask layer are sequentially formed on the first mask layer directly above the array region and directly above the peripheral region, and a second photoresist layer is formed on the fifth mask layer directly above the array region; the second photoresist layer includes a sixth mask pattern; etching the fifth mask layer based on the sixth mask pattern to form a seventh mask pattern, and removing the fifth mask layer directly above the peripheral region; A third dielectric layer is formed on the sidewalls and the top surface of the seventh mask pattern, between two adjacent units of the seventh mask pattern, and on the second mask layer directly above the peripheral region.

13. The forming method according to claim 12, It is characterized in that The array region includes a boundary region close to the peripheral region; forming a second mask layer on the first mask layer, and forming a second mask pattern located directly above the array region in the second mask layer, and the peripheral region does not include the second mask pattern directly above the array region, and further comprising: forming a third photoresist layer on the third dielectric layer directly above the boundary region and the peripheral region; Based on the third photoresist layer, the third dielectric layer, and the seventh mask pattern, the second mask layer is etched to form a second mask pattern in the second mask layer.

14. The forming method according to claim 5, It is characterized in that Before forming the first mask layer on the substrate, the forming method further includes: forming an amorphous carbon layer on the substrate; The forming of the array pattern in the array region based on the first mask pattern and the second mask pattern and not forming the array pattern in the peripheral region comprises: Etching the amorphous carbon layer using the first mask pattern and the second mask pattern as masks, and transferring a pattern formed by overlapping the first mask pattern and the second mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer; The substrate is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form an array pattern in the array region, and the array pattern is not formed in the peripheral region.

15. A semiconductor structure, It is characterized in that The semiconductor structure is obtained by the method for forming a semiconductor structure according to any one of claims 1 to 14.

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