Memory, preparation method thereof and electronic equipment

Abstract

The invention relates to a memory, a preparation method thereof and electronic equipment. The memory comprises a plurality of active columns which are arranged in rows along a first direction and arranged in columns along a second direction on a substrate; the first direction is intersected with the second direction; the plurality of contact structures are respectively arranged at the tops of the corresponding active columns; wherein the top surface, deviating from the active column, of the contact structure is provided with a storage node contact area; and the storage node contact areas of the adjacent contact structures in the same row are arranged in a staggered manner in the first direction and / or the second direction. The memory is small in occupied area, and high storage density can be achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory device and a method for preparing the same, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in electronic devices such as cloud servers, computers and mobile phones.

[0003] In the related art, a DRAM memory cell based on a saddle-fin transistor occupies an area of ​​6F. 2 (Where F is the minimum process size that can be obtained under given process conditions.) As the integration level continues to increase, the number of storage cells on memory chips has increased dramatically. Therefore, how to reduce the area occupied by storage cells to further improve the storage density of devices is a problem that needs to be solved urgently. Summary of the invention

[0004] Based on this, it is necessary to provide a memory and a preparation method thereof, and an electronic device to address the deficiencies in the related art.

[0005] The present application provides a memory, comprising:

[0006] A plurality of active pillars are arranged in rows along a first direction on the substrate, and arranged in columns along a second direction; the first direction intersects the second direction;

[0007] A plurality of contact structures are respectively arranged on the tops of the corresponding active pillars;

[0008] The contact structure has a storage node contact region on a top surface facing away from the active pillar; and the storage node contact regions of the contact structures located in the same row and adjacent to each other are staggered in the first direction and / or the second direction.

[0009] In some embodiments, the contact structure has an extension end; the top surface of the extension end away from the active pillar is the storage node contact area of ​​the contact structure; wherein,

[0010] The extending end extends along the first direction;

[0011] Alternatively, the extending end extends along the second direction;

[0012] Alternatively, the extending direction of the extending end intersects both the first direction and the second direction.

[0013] In some embodiments, the extending ends of the contact structures have the same extending direction;

[0014] Wherein, the extending lengths of the extending ends of the contact structures that are located in the same row and adjacent to each other are different.

[0015] In some embodiments, the memory further comprises:

[0016] A plurality of signal line groups arranged at intervals in the second direction; the signal line groups include first signal lines and second signal lines arranged at intervals in the second direction, the first signal lines and the second signal lines both extend along the first direction and are arranged corresponding to the active pillars located in the same row;

[0017] The plurality of contact structures include a plurality of first contact structures and a plurality of second contact structures; wherein,

[0018] The first contact structure is disposed on the active pillar corresponding to the first signal line; the top surface of the first contact structure away from the active pillar is the storage node contact area of ​​the first contact structure;

[0019] The second contact structure is disposed on the active pillar corresponding to the second signal line and has an extension end; a top surface of the extension end away from the active pillar is the storage node contact region of the second contact structure.

[0020] In some embodiments, the extending end of the second contact structure extends along the first direction;

[0021] Alternatively, the extending end of the second contact structure extends along the second direction;

[0022] Alternatively, an extending direction of the extending end of the second contact structure intersects with the first direction and the second direction.

[0023] In some embodiments, the signal line group further includes a third signal line spaced apart from the first signal line in the second direction, the third signal line and the second signal line are respectively located on two opposite sides of the first signal line in the second direction, extend along the first direction and are arranged corresponding to the active pillars located in a corresponding row;

[0024] The plurality of contact structures further comprises a plurality of third contact structures;

[0025] The third contact structure is disposed on the active pillar corresponding to the third signal line and has an extension end; the top surface of the extension end away from the active pillar is the storage node contact area of ​​the third contact structure;

[0026] Wherein, the extending end of the third contact structure and the extending end of the second contact structure extend in opposite directions.

[0027] In some embodiments, the semiconductor structure further comprises:

[0028] A plurality of capacitors, each located in the storage node contact region corresponding to the contact structure;

[0029] The capacitors located in the same row and adjacent to each other are staggered in the first direction and / or the second direction, and a plurality of the capacitors are arranged in a hexagonal grid, with each capacitor being located at a vertex and a center of the hexagon.

[0030] The present application also provides a method for preparing a memory, comprising:

[0031] Providing a substrate, wherein the substrate is formed with a plurality of active pillars arranged in rows along a first direction and in columns along a second direction; the first direction intersects the second direction;

[0032] A contact structure is formed correspondingly on the top of each active pillar; the contact structure has a storage node contact area on the top surface away from the active pillar, and the storage node contact areas of the contact structures located in the same row and adjacent to each other are staggered in the first direction and / or the second direction.

[0033] In some embodiments, the method for preparing the memory further includes:

[0034] forming a plurality of signal line groups spaced apart in the second direction; the signal line groups comprising first signal lines and second signal lines spaced apart in the second direction, the first signal lines and the second signal lines both extending along the first direction and being arranged corresponding to the active pillars in the same row;

[0035] The contact structure is formed correspondingly on the top of each active pillar, including:

[0036] A first contact structure is formed on the active pillar corresponding to the first signal line; a top surface of the first contact structure away from the active pillar is the storage node contact area of ​​the first contact structure;

[0037] A second contact structure is formed on the active pillar corresponding to the second signal line; the second contact structure is formed with an extension end, and the top surface of the extension end away from the active pillar is the storage node contact area of ​​the second contact structure.

[0038] In some embodiments, the signal line group further includes a third signal line spaced apart from the first signal line in the second direction, the third signal line and the second signal line are respectively located on two opposite sides of the first signal line in the second direction, extend along the first direction and are arranged corresponding to the active pillars located in a corresponding row;

[0039] The contact structure is formed correspondingly on the top of each active pillar, and further includes:

[0040] A third contact structure is formed on the active column corresponding to the third signal line; the third contact structure is formed with an extension end, and the top surface of the extension end away from the active column is the storage node contact area of ​​the third contact structure; the extension end of the third contact structure is opposite to the extension direction of the extension end of the second contact structure.

[0041] In some embodiments, the first contact structure is formed on the active pillar connected to the first signal line, and the second contact structure is formed on the active pillar connected to the second signal line, including:

[0042] forming a first isolation material layer on the substrate;

[0043] forming first grooves extending along the first direction and arranged at intervals in the second direction in the first isolation material layer; the first grooves expose the top surfaces of the active pillars, and the first isolation material layer is retained as a first isolation layer;

[0044] forming a sacrificial material layer filling the first trench and covering the first isolation layer;

[0045] A patterned hard mask layer is formed on the sacrificial material layer; a first mask pattern and a second mask pattern are formed in the patterned hard mask layer, the first mask pattern extending along the second direction and arranged at intervals in the first direction, the orthographic projection of the first mask pattern on the substrate is located directly above the first signal line, and the orthographic projection of the second mask pattern on the substrate is offset from the second signal line in the first direction;

[0046] The sacrificial material layer is etched based on the first mask pattern and the second mask pattern to form a filling hole; the filling hole exposes the top surface of the active pillar connected to the first signal line and a portion of the top surface of the active pillar connected to the second signal line; the sacrificial material layer is retained as a sacrificial layer;

[0047] Filling a second isolation layer in the filling hole;

[0048] removing the sacrificial layer to expose a top surface of the active pillar connected to the first signal line and another portion of the top surface of the active pillar connected to the second signal line;

[0049] A contact layer is formed on the active pillar; wherein the contact layer formed on the active pillar connected to the first signal line serves as the first contact structure, and the contact layer formed on the active pillar connected to the second signal line serves as the second contact structure.

[0050] In some embodiments, the method for preparing the memory further includes:

[0051] A capacitor is formed corresponding to the storage node contact area of ​​the contact structure; wherein the capacitors located in the same row and adjacent to each other are staggered in the first direction and / or the second direction, and multiple capacitors are arranged in a hexagonal grid, and each capacitor is located at the vertex and center of the hexagon.

[0052] The present application also provides an electronic device, comprising a memory provided in any of the aforementioned embodiments.

[0053] The memory and the manufacturing method thereof, and the electronic device provided in the present application have at least the following beneficial effects:

[0054] The memory and the preparation method thereof provided by the present application have contact structures correspondingly arranged on the top of each active column, and the contact structure has a storage node contact area on the top surface facing away from the active column, and the storage node contact area can be used to set a capacitor. Since the storage node contact areas of the contact structures located in the same row and adjacent to each other are arranged in a staggered manner in the first direction and / or the second direction, the capacitors located in the same row and adjacent to each other can be staggered in the first direction and / or the second direction, which is conducive to reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0055] The electronic device provided in the present application includes the memory provided in the aforementioned embodiments. Therefore, the technical effects that can be achieved by the memory provided in the aforementioned embodiments can also be achieved by the aforementioned electronic devices, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 An equivalent structural diagram of a memory provided in some embodiments of the present application;

[0058] Figure 2 Schematic diagram of equivalent structure of memory provided in other embodiments of the present application;

[0059] Figure 3 An equivalent structural schematic diagram of a memory provided in some further embodiments of the present application;

[0060] Figure 4 Figure (a) is a schematic diagram of a three-dimensional structure of a memory provided in some embodiments of the present application; Figure 4 Figure (b) is a schematic diagram of a top view of a memory provided in some embodiments of the present application;

[0061] Figure 5 Schematic diagram of equivalent structure of memory provided in other embodiments of the present application;

[0062] Figure 6 Figure (a) is a schematic diagram of an equivalent structure of a memory provided in some other embodiments of the present application; Figure 6 Figure (b) is a schematic diagram of an equivalent structure of a memory provided in some other embodiments of the present application;

[0063] Figure 7 A schematic diagram of a process for preparing a memory provided in some embodiments of the present application;

[0064] Figure 8 A schematic flow chart of step S2 in the method for preparing a memory provided in some embodiments of the present application;

[0065] Fig. 9 A schematic flow chart of steps for preparing a first contact structure and a second contact structure in a method for preparing a memory provided in some embodiments of the present application;

[0066] Fig.10 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after forming a first isolation material layer in a method for preparing a memory provided in some embodiments of the present application; Fig.10 Figure (b) is Fig.10 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.10 Figure (c) in the figure is Fig.10 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.10 Figure (d) in the figure is Fig.10 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.10 Figure (e) in the figure is Fig.10 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0067] Fig.11 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after depositing an amorphous carbon layer, a first silicon oxynitride layer, a spin-coated hard mask layer, and a second silicon oxynitride layer in a method for preparing a memory device provided in some embodiments of the present application; Fig.11 Figure (b) is Fig.11 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.11 Figure (c) in the figure is Fig.11 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.11 Figure (d) in the figure is Fig.11 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.11 Figure (e) in the figure is Fig.11 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0068] Fig.12 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after a patterned photoresist layer is formed in a method for preparing a memory provided in some embodiments of the present application; Fig.12 Figure (b) is Fig.12 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.12 Figure (c) in the figure is Fig.12 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.12 Figure (d) in the figure is Fig.12 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.12 Figure (e) in the figure is Fig.12 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0069] Fig.13 FIG. (a) is a schematic diagram of a three-dimensional structure of a structure obtained after a mask pattern is transferred to a second silicon oxynitride layer and a spin-coated hard mask layer in a method for preparing a memory provided in some embodiments of the present application; Fig.13 Figure (b) is Fig.13 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.13 Figure (c) in the figure is Fig.13 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.13 Figure (d) in the figure is Fig.13 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.13 Figure (e) in the figure is Fig.13 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0070] Fig.14 Figure (a) is a schematic diagram of the three-dimensional structure of a structure obtained after depositing a silicon oxide layer in a method for preparing a memory provided in some embodiments of the present application; Fig.14 Figure (b) is Fig.14(a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.14 Figure (c) in the figure is Fig.14 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.14 Figure (d) in the figure is Fig.14 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.14 Figure (e) in the figure is Fig.14 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0071] Fig.15 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after anisotropic etching of a silicon oxide layer and a spin-on hard mask layer in a method for preparing a memory provided in some embodiments of the present application; Fig.15 Figure (b) is Fig.15 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.15 Figure (c) in the figure is Fig.15 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.15 Figure (d) in the figure is Fig.15 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.15 Figure (e) in the figure is Fig.15 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0072] Fig.16 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after forming a first isolation layer in a method for preparing a memory provided in some embodiments of the present application; Fig.16 Figure (b) is Fig.16 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.16 Figure (c) in the figure is Fig.16 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.16 Figure (d) in the figure is Fig.16 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.16 Figure (e) in the figure is Fig.16 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0073] Fig.17 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after forming a sacrificial material layer in a method for preparing a memory provided in some embodiments of the present application; Fig.17 Figure (b) is Fig.17 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.17 Figure (c) in the figure is Fig.17 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.17 Figure (d) in the figure is Fig.17 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.17 Figure (e) in the figure is Fig.17 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0074] Fig.18 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after depositing an amorphous carbon layer, a first silicon oxynitride layer, a spin-coated hard mask layer, and a second silicon oxynitride layer in a method for preparing a memory device provided in some embodiments of the present application; Fig.18 Figure (b) is Fig.18 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.18 Figure (c) in the figure is Fig.18 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.18 Figure (d) in the figure is Fig.18 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.18 Figure (e) in the figure is Fig.18 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0075] Fig.19 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after a patterned photoresist layer is formed in a method for preparing a memory provided in some embodiments of the present application; Fig.19 Figure (b) is Fig.19 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.19 Figure (c) in the figure is Fig.19 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.19 Figure (d) in the figure is Fig.19 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.19 Figure (e) in the figure is Fig.19 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0076] Fig. 20 FIG. (a) is a schematic diagram of a three-dimensional structure of a structure obtained after a mask pattern is transferred to a second silicon oxynitride layer and a spin-coated hard mask layer in a method for preparing a memory provided in some embodiments of the present application; Fig. 20 Figure (b) is Fig. 20 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig. 20 Figure (c) in the figure is Fig. 20 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig. 20 Figure (d) in the figure is Fig. 20 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig. 20 Figure (e) in the figure is Fig. 20 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0077] Fig.21 Figure (a) is a schematic diagram of the three-dimensional structure of a structure obtained after depositing a silicon oxide layer in a method for preparing a memory provided in some embodiments of the present application; Fig.21 Figure (b) is Fig.21 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig.21 Figure (c) in the figure is Fig.21 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.21 Figure (d) in the figure is Fig.21 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.21 Figure (e) in the figure is Fig.21 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0078] Fig. 22 Figure (a) is a schematic diagram of a three-dimensional structure of a structure obtained after coating a spin-coated hard mask layer in a method for preparing a memory provided in some embodiments of the present application; Fig. 22 Figure (b) is Fig. 22 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the aa' direction; Fig. 22 Figure (c) in the figure is Fig. 22 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig. 22 Figure (d) in the figure is Fig. 22 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig. 22 Figure (e) in the figure is Fig. 22 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0079] Fig.23 A schematic diagram of an equivalent structure of a structure obtained after forming a second trench and a third trench in a method for preparing a memory provided in some embodiments of the present application;

[0080] Fig.24 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a filling hole in a method for preparing a memory provided in some embodiments of the present application; Fig.24Figure (b) is Fig.24 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.24 Figure (c) in the figure is Fig.24 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the cc' direction; Fig.24 Figure (d) in the figure is Fig.24 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the dd' direction;

[0081] Fig.25 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after coating the spin-coated hard mask layer in the memory manufacturing method provided by other embodiments of the present application; Fig.25 Figure (b) is Fig.25 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.25 Figure (c) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a filling hole in a method for preparing a memory provided in some other embodiments of the present application; Fig.25 Figure (d) in the figure is Fig.25 (c) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0082] Fig.26 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after coating the spin-coated hard mask layer in the memory manufacturing method provided in some embodiments of the present application; Fig.26 Figure (b) is Fig.26 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction; Fig.26 FIG. (c) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a filling hole in a method for preparing a memory provided in some embodiments of the present application; Fig.26 Figure (d) in the figure is Fig.26 (c) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0083] Fig. 27 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after the second isolation layer is filled in the preparation method of the memory provided in some embodiments of the present application; Fig. 27 Figure (b) is Fig. 27 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0084] Fig.28 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after the second isolation layer is filled in the preparation method of the memory provided in other embodiments of the present application; Fig.28 Figure (b) is Fig.28(a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0085] Fig.29 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after the second isolation layer is filled in the preparation method of the memory provided in some embodiments of the present application; Fig.29 Figure (b) is Fig.29 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0086] Fig.30 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after removing the sacrificial layer in the memory manufacturing method provided by some embodiments of the present application; Fig.30 Figure (b) is Fig.30 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0087] Fig.31 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after removing the sacrificial layer in the memory manufacturing method provided by other embodiments of the present application; Fig.31 Figure (b) is Fig.31 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0088] Fig.32 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after removing the sacrificial layer in the memory manufacturing method provided in some embodiments of the present application; Fig.32 Figure (b) is Fig.32 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0089] Fig.33 Figure (a) is a schematic diagram of a cross-sectional structure in the aa' direction of a structure obtained after forming a contact layer in a method for preparing a memory provided in some embodiments of the present application; Fig.33 Figure (b) is Fig.33 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0090] Fig.34 Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after forming a contact layer in the preparation method of the memory provided in some other embodiments of the present application; Fig.34 Figure (b) is Fig.34 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction;

[0091] Fig.35Figure (a) is a schematic diagram of the cross-sectional structure in the aa' direction of the structure obtained after forming a contact layer in the preparation method of the memory provided in some embodiments of the present application; Fig.35 Figure (b) is Fig.35 (a) is a schematic diagram of the cross-sectional structure of the structure shown in the bb' direction.

[0092] Description of reference numerals:

[0093] 1. Active pillar; 10. Substrate; 1A. First end; 1B. Second end; 1C. Channel region;

[0094] 2. signal line group; 21. first signal line; 22. second signal line; 23. third signal line; 201. gate dielectric layer; 202. word line conductive layer; 203A. filling dielectric layer; 203B. top dielectric layer; 204. sidewall protection layer;

[0095] 3. contact structure; 30. storage node contact region; 3A. extension end of contact structure; 31. first contact structure; 32. second contact structure; 32A. extension end of second contact structure; 33. third contact structure; 33A. extension end of third contact structure;

[0096] 301, a first isolation material layer; 301A, a first amorphous carbon layer; 301A', a second amorphous carbon layer; 301B, a first silicon oxynitride layer; 301B', a third silicon oxynitride layer; 301C, a first spin-on hard mask layer; 301C', a second spin-on hard mask layer; 301C", a third spin-on hard mask layer; 301D, a second silicon oxynitride layer; 301D', a fourth silicon oxynitride layer; 301E, a first patterned photoresist layer; 301E', a second patterned photoresist layer; 301F, a first silicon oxide layer; 301F', a second silicon oxide layer; 302, a first isolation layer; 303, a sacrificial material layer; 304, a sacrificial layer; 305, a second isolation layer;

[0097] 4. Capacitor;

[0098] BL, bit line; BL1, first bit line; BL2, second bit line; BL3, third bit line; WL, word line; WL1, first word line; WL2, second word line; WL3, third word line; T, filling hole; T1, first trench; T2, second trench; T3, third trench. DETAILED DESCRIPTION

[0099] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0101] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first signal line may be referred to as a second signal line, and similarly, a second signal line may be referred to as a first signal line; the first signal line and the second signal line are different signal lines.

[0102] Spatially relative terms such as "on," "located above," and the like, may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, a description of "on other elements" would be oriented "below" the other elements or features. Thus, the exemplary terms "on" and "located above" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0103] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0104] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0105] In view of the deficiencies in the related art, the present application provides a memory and a method for preparing the same, and an electronic device, the details of which will be described in subsequent embodiments.

[0106] According to some embodiments, the present application provides a memory.

[0107] See also Figures 1 to 3 In some embodiments, the memory may include a plurality of active pillars 1 and a plurality of contact structures 3 .

[0108] A plurality of active pillars 1 are arranged in rows along a first direction on the substrate, and in columns along a second direction. It should be noted that in the embodiment of the present application, the first direction intersects with the second direction, the first direction may be, for example, the X direction, and correspondingly, the second direction may be, for example, the Y direction.

[0109] A plurality of contact structures 3 are respectively disposed on the top of the corresponding active pillars 1. The top surface of the contact structure 3 facing away from the active pillar 1 has a storage node contact region 30, and the storage node contact regions 30 of the contact structures 3 located in the same row and adjacent to each other are staggered in a first direction (e.g., X direction) and / or a second direction (e.g., Y direction).

[0110] In the memory provided by the above embodiment, a contact structure 3 is correspondingly arranged at the top of each active pillar 1, and the top surface of the contact structure 3 facing away from the active pillar 1 has a storage node contact area 30, and the storage node contact area 30 can be used to set a capacitor. Since the storage node contact areas 30 of the contact structures 3 located in the same row and adjacent to each other are arranged in a staggered manner in the first direction (for example, the X direction) and / or the second direction (for example, the Y direction), the capacitors located in the same row and adjacent to each other can be staggered in the first direction (for example, the X direction) and / or the second direction (for example, the Y direction), which is conducive to reducing the occupied area of ​​the memory cell and achieving a higher storage density.

[0111] Please continue reading Figures 1 to 3 In some embodiments, the contact structure 3 has an extension end 3A, and the top surface of the extension end 3A facing away from the active pillar 1 is the storage node contact region 30 of the contact structure 3 .

[0112] The embodiment of the present application does not specifically limit the extending direction of the extending end 3A of the contact structure 3. As an example, Figure 1 As shown, the extended end 3A of the contact structure 3 may extend along a first direction (eg, X direction); or Figure 2 As shown, the extended end 3A of the contact structure 3 may extend along the second direction (eg, the Y direction); or, as shown in FIG. Figure 3 As shown, the extending direction of the extending end 3A of the contact structure 3 may also intersect both the first direction (eg, the X direction) and the second direction (eg, the Y direction).

[0113] Please continue reading Figures 1 to 3 In some embodiments, the extending ends 3A of the contact structures 3 extend in the same direction. The extending ends 3A of the contact structures 3 that are adjacent to each other and located in the same row have different extending lengths.

[0114] In addition, it should be noted that in some possible embodiments of the present application, the extension end 3A of each contact structure 3 may also have a different extension direction, as long as the storage node contact areas 30 of the contact structures 3 located in the same row and adjacent to each other can form a staggered arrangement in the first direction (for example, the X direction) and / or the second direction (for example, the Y direction).

[0115] See also Figure 4 and Figure 5 In some embodiments, the memory may further include a plurality of signal line groups 2. The plurality of signal line groups 2 may be spaced apart in the second direction (e.g., the Y direction). Each signal line group 2 may include a first signal line 21 and a second signal line 22 spaced apart in the second direction (e.g., the Y direction), and the first signal line 21 and the second signal line 22 may both extend along the first direction (e.g., the X direction) and be arranged corresponding to the active pillars 1 in the same row.

[0116] In the memory provided by the above embodiment, the plurality of contact structures 3 may include a plurality of first contact structures 31 and a plurality of second contact structures 32 .

[0117] The first contact structure 31 is disposed on the active pillar 1 corresponding to the first signal line 21 , and the top surface of the first contact structure 31 away from the active pillar 1 is a storage node contact region 30 of the first contact structure 31 .

[0118] The second contact structure 32 is disposed on the active pillar 1 corresponding to the second signal line 22 and has an extension end 32A. The top surface of the extension end 32A away from the active pillar 1 is the storage node contact region 30 of the second contact structure 32 .

[0119] The memory provided by the above embodiment has a plurality of signal line groups 2 arranged at intervals in the column direction of the active pillar 1, and in each signal line group 2, a first signal line 21 and a second signal line 22 extending in the row direction of the active pillar 1 and arranged corresponding to the active pillar 1 located in the same row are arranged at intervals, and a first contact structure 31 is arranged on the active pillar 1 corresponding to the first signal line 21. In the above embodiment, by arranging a second contact structure 32 having an extended end 32A on the active pillar 1 corresponding to the second signal line 22, the storage node contact area 30 of the second contact structure 32 is misaligned with the storage node contact area 30 of the first contact structure 31. The above structure enables the storage device to be arranged on the first contact structure 31 and the extended end 32A of the second contact structure 32 to form a misalignment, thereby reducing the required spacing between adjacent signal lines. Therefore, the memory in the above embodiment is conducive to reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0120] In some embodiments, an orthographic projection area of ​​the second contact structure 32 on the substrate is larger than an orthographic projection area of ​​the first contact structure 31 on the substrate.

[0121] The embodiment of the present application does not specifically limit the form of the storage device. As an example, the storage device may include but is not limited to a capacitor.

[0122] The embodiment of the present application does not specifically limit the extension direction of the extension end 32A of the second contact structure 32. As an example, the extension end 32A of the second contact structure 32 may extend along a first direction (e.g., X direction); or, the extension end 32A of the second contact structure 32 may extend along a second direction (e.g., Y direction); or, the extension direction of the extension end 32A of the second contact structure 32 may also intersect with the first direction (e.g., X direction) and the second direction (e.g., Y direction).

[0123] For example Figure 4As shown, the extension end 32A of the second contact structure 32 extends along the first direction (e.g., the X direction). The extension end 32A of the second contact structure 32 extends along the second direction (e.g., the Y direction), and the extension direction of the extension end 32A of the second contact structure 32 intersects the first direction (e.g., the X direction) and the second direction (e.g., the Y direction). Figure 2 and Figure 3 Understood, no further elaboration here.

[0124] Please continue reading Figures 4 to 5 In some embodiments, the signal line group 2 may further include a third signal line 23 spaced apart from the first signal line 21 in the second direction (e.g., the Y direction); the third signal line 23 and the second signal line 22 may be respectively located on opposite sides of the first signal line 21 in the second direction (e.g., the Y direction), and both extend along the first direction (e.g., the X direction), and are arranged corresponding to the active columns 1 located in the corresponding rows.

[0125] In the memory provided by the above embodiment, the plurality of contact structures 3 may further include a plurality of third contact structures 33 .

[0126] The third contact structure 33 can be disposed on the active pillar 1 corresponding to the third signal line 23, and has an extension end 33A. The top surface of the extension end 33A of the third contact structure 33 away from the active pillar 1 is the storage node contact region 30 of the third contact structure 33. The extension end 33A of the third contact structure 33 extends in the opposite direction to the extension end 32A of the second contact structure 32.

[0127] The memory provided in the above embodiment is further provided with a third signal line 23, and a third contact structure 33 having an extension end 33A is provided on the active column 1 corresponding to the third signal line 23. The above structure enables the storage device to be provided on the first contact structure 31, the extension end 32A of the second contact structure 32, and the extension end 33A of the third contact structure 33 to form a misalignment; further, since the extension end 33A and the extension end 32A of the second contact structure 32 have opposite extension directions, the storage device provided on the extension end 32A of the second contact structure 32 and the storage device provided on the extension end 33A of the third contact structure 33 are respectively misaligned in opposite directions relative to the storage device provided on the first contact structure 31. The use of this structure facilitates the arrangement of multiple storage devices in a hexagonal grid, thereby further reducing the required spacing between adjacent signal lines. Therefore, the memory in the above embodiment is conducive to further reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0128] In some embodiments, the orthographic projection area of ​​the third contact structure 33 on the substrate is also larger than the orthographic projection area of ​​the first contact structure 31 on the substrate.

[0129] In some embodiments, an orthographic projection area of ​​the second contact structure 32 on the substrate is equal to an orthographic projection area of ​​the third contact structure 33 on the substrate.

[0130] In the memory provided in the above embodiment, since the orthographic projection area of ​​the second contact structure 32 on the substrate is equal to the orthographic projection area of ​​the third contact structure 33 on the substrate, that is, the extension distances of the extension end 32A of the second contact structure 32 and the extension end 33A of the third contact structure 33 are equal, the storage device arranged on the extension end 32A of the second contact structure 32 and the storage device arranged on the extension end 33A of the third contact structure 33 can form the same degree of misalignment in opposite directions relative to the storage device arranged on the first contact structure 31, so that when this structure is adopted, multiple storage devices can be arranged in a hexagonal grid, that is, arranged closely in a honeycomb shape, thereby further reducing the required spacing between adjacent signal lines. Therefore, the memory in the above embodiment is conducive to further reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0131] Please continue reading Figures 4 to 5 In some embodiments, the memory may further include a plurality of capacitors 4. That is, the storage device is, for example, a capacitor 4.

[0132] The plurality of capacitors 4 may be respectively located in the storage node contact regions 30 of the corresponding contact structures 3. The capacitors 4 located in the same row and adjacent to each other are staggered in the first direction (e.g., X direction) and / or the second direction (e.g., Y direction), and the plurality of capacitors 4 are arranged in a hexagonal grid, with each capacitor 4 being respectively located at the vertices and the center of the hexagon.

[0133] Taking the multiple contact structures 3 including multiple first contact structures 31, multiple second contact structures 32 and multiple third contact structures 33 as an example, multiple capacitors 4 can be respectively located on the extension ends 32A of the first contact structures 31, the second contact structures 32 and the extension ends 33A of the third contact structures 33. Among them, the capacitors 4 adjacent to each other in the second direction (for example, the Y direction) can be staggered in the first direction (for example, the X direction), and the multiple capacitors 4 can be arranged in a hexagonal grid, and each capacitor 4 can be respectively located at the vertices and the center of the hexagon.

[0134] It should be noted that the embodiments of the present application do not specifically limit the type of signal lines.

[0135] In some embodiments, the signal line group 2 is a bit line group. Figure 6As shown in FIG. 1 (a), the signal line group 2 may include a first bit line BL1 and a second bit line BL2 arranged at intervals in a second direction (e.g., the Y direction). The first bit line BL1 and the second bit line BL2 both extend in a first direction (e.g., the X direction) and connect in series the active pillars 1 located in the same row. By arranging a second contact structure 32 having an extending end 32A in the extending direction of the bit line group (e.g., the first direction) on the active pillar 1 corresponding to the second bit line BL2, adjacent storage devices in the second direction may be misaligned in the bit line extending direction (i.e., the first direction), thereby reducing the required spacing (BL pitch) between adjacent bit lines.

[0136] You can also, for example Figure 6 As shown in FIG. (a), the signal line group 2 includes a first bit line BL1, a second bit line BL2, and a third bit line BL3 which are arranged at intervals in a second direction (e.g., the Y direction). By arranging a third contact structure 33 having an extension end 33A in the extension direction (e.g., the first direction) of the bit line group on the active pillar 1 corresponding to the third bit line BL3, adjacent storage devices in the second direction are misaligned in the bit line extension direction (i.e., the first direction); further, since the extension end 33A and the extension end 32A of the second contact structure 32 have opposite extension directions, the storage device arranged on the extension end 32A of the second contact structure 32 and the storage device arranged on the extension end 33A of the third contact structure 33 are misaligned in opposite directions relative to the storage device arranged on the first contact structure 31. With this structure, multiple storage devices can be arranged in a hexagonal grid, thereby further reducing the required spacing between adjacent bit lines.

[0137] Please continue reading Figure 6 In (a) of FIG. 1 , in some embodiments, the memory may further include a plurality of word lines WL spaced apart in a first direction (eg, X direction). The word lines WL may extend along a second direction (eg, Y direction) and be arranged corresponding to the active pillars 1 in the same column.

[0138] In some other embodiments, the signal line group 2 is a word line group. Figure 6 As shown in FIG. 2( b), the signal line group 2 may include a first word line WL1 and a second word line WL2 spaced apart in a second direction (e.g., Y direction), the first word line WL1 and the second word line WL2 both extend in a first direction (e.g., X direction), and connect active pillars 1 in the same row in series. By providing a second contact structure 32 having an extended end 32A in the extending direction of the word line group (e.g., the first direction) on the active pillar 1 corresponding to the second word line WL2, adjacent storage devices in the second direction may be misaligned in the word line extending direction (i.e., the first direction), thereby reducing the required spacing (WL pitch) between adjacent word lines.

[0139] You can also, for example Figure 6 As shown in FIG. (b), the signal line group 2 includes a first word line WL1, a second word line WL2, and a third word line WL3 which are arranged at intervals in the second direction (e.g., the Y direction). By providing a third contact structure 33 having an extension end 33A in the extension direction (e.g., the first direction) of the word line group on the active pillar 1 corresponding to the third word line WL3, adjacent storage devices in the second direction are misaligned in the word line extension direction (i.e., the first direction); further, since the extension end 33A and the extension end 32A of the second contact structure 32 have opposite extension directions, the storage device arranged on the extension end 32A of the second contact structure 32 and the storage device arranged on the extension end 33A of the third contact structure 33 are misaligned in opposite directions relative to the storage device arranged on the first contact structure 31. With this structure, multiple storage devices can be arranged in a hexagonal grid, thereby further reducing the required spacing between adjacent word lines.

[0140] Please continue to participate Figure 6 As shown in FIG. 5( b), in some other embodiments, the memory may further include a plurality of bit lines BL spaced apart in a first direction (eg, X direction), and the bit lines BL may extend along a second direction (eg, Y direction) and connect in series the active pillars 1 in the same column.

[0141] Please continue reading Figure 1 In (a), in some embodiments, the active pillar 1 includes a first end 1A, a second end 1B, and a channel region between the first end 1A and the second end 1B. The first end 1A of the active pillar 1 is connected to the corresponding bit line; the second end 1B of the active pillar 1 is connected to the corresponding contact structure; each word line can be located on the sidewall of the channel region of the active pillar 1 in the corresponding column.

[0142] In the memory provided in the above embodiment, each word line can surround or semi-surround the side wall of the channel region of the corresponding column active pillar 1, thereby forming a storage cell with a vertical gate all around (VGAA) structure. Since each word line is located on the side wall of the channel region of the corresponding column active pillar 1, more storage cells can be arranged on the unit area, which is conducive to achieving a higher storage density.

[0143] The present application also provides a method for preparing a memory according to some embodiments. In order to more clearly explain the preparation method in some embodiments of the present application, please refer to Figures 1 to 6 Understand some embodiments of the present application.

[0144] See also Figure 7 In some embodiments, the method for preparing the memory may specifically include the following steps:

[0145] S1: providing a substrate, wherein a plurality of active pillars 1 are arranged in rows along a first direction (eg, X direction) and in columns along a second direction (eg, Y direction); the first direction (eg, X direction) intersects with the second direction (eg, Y direction).

[0146] S2: A contact structure 3 is formed correspondingly at the top of each active pillar 1; the contact structure 3 has a storage node contact area 30 on the top surface facing away from the active pillar 1, and the storage node contact areas 30 of the contact structures 3 located in the same row and adjacent to each other are staggered in a first direction (for example, X direction) and / or a second direction (for example, Y direction).

[0147] In the method for preparing the memory provided in the above embodiment, a contact structure 3 is formed correspondingly on the top of each active pillar 1, and the top surface of the contact structure 3 facing away from the active pillar 1 has a storage node contact area 30, and the storage node contact area 30 can be used to set the capacitor 4. Since the storage node contact areas 30 of the contact structures 3 located in the same row and adjacent to each other are arranged in a staggered manner in the first direction (for example, the X direction) and / or the second direction (for example, the Y direction), the capacitors 4 located in the same row and adjacent to each other can be staggered in the first direction (for example, the X direction) and / or the second direction (for example, the Y direction), which is conducive to reducing the occupied area of ​​the memory cell and achieving a higher storage density.

[0148] In some embodiments, the method for preparing the memory may further include the following steps:

[0149] A plurality of signal line groups 2 are formed and arranged at intervals in a second direction (e.g., the Y direction). The signal line group 2 includes a first signal line 21 and a second signal line 22 arranged at intervals in the second direction (e.g., the Y direction). The first signal line 21 and the second signal line 22 both extend along the first direction (e.g., the X direction) and are arranged corresponding to the active pillars 1 located in the same row.

[0150] See also Figure 7 In some embodiments, step S2 forms a contact structure corresponding to the top of each active pillar, which may specifically include the following steps:

[0151] S21 : forming a first contact structure 31 on the active pillar 1 corresponding to the first signal line 21 ; a top surface of the first contact structure 31 away from the active pillar 1 is a storage node contact region 30 of the first contact structure 31 .

[0152] S22 : forming a second contact structure 32 on the active pillar 1 corresponding to the second signal line 22 . The second contact structure 32 is formed with an extension end 32A, and the top surface of the extension end 32A away from the active pillar 1 is the storage node contact region 30 of the second contact structure 32 .

[0153] The method for preparing the memory provided in the above embodiment forms a plurality of signal line groups 2 arranged at intervals in the column direction of the active pillar 1, and in each signal line group 2, a first signal line 21 and a second signal line 22 extending in the row direction of the active pillar 1 and arranged corresponding to the active pillar 1 located in the same row are formed at intervals, and a first contact structure 31 is formed on the active pillar 1 corresponding to the first signal line 21. In the above embodiment, by forming a second contact structure 32 having an extended end 32A on the active pillar 1 corresponding to the second signal line 22, the storage node contact area 30 of the second contact structure 32 is misaligned with the storage node contact area 30 of the first contact structure 31. The formation of the above structure enables the capacitor 4 to be formed on the first contact structure 31 and the extended end 32A of the second contact structure 32, respectively, to be misaligned, thereby reducing the required spacing between adjacent signal lines. Therefore, the method for preparing the memory in the above embodiment is conducive to reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0154] It should be noted that there is no restriction on the order of the above step S21 and step S22, that is, it is allowed to execute either one of them first or at the same time.

[0155] Please continue reading Figures 4 to 5 In some embodiments, the signal line group 2 also includes a third signal line 23 spaced apart from the first signal line 21 in a second direction (e.g., Y direction), and the third signal line 23 and the second signal line 22 are respectively located on opposite sides of the first signal line 21 in the second direction (e.g., Y direction), extend along the first direction (e.g., X direction) and are arranged corresponding to the active pillars 1 located in the corresponding row.

[0156] In some embodiments, the method for preparing the memory may further include the following steps: forming a third contact structure 33 on the active pillar 1 corresponding to the third signal line 23. The third contact structure 33 is formed with an extension end 33A, and the extension end 33A of the third contact structure 33 is away from the top surface of the active pillar 1 to form a storage node contact area 30 of the third contact structure 33; the extension end 33A of the third contact structure 33 is opposite to the extension direction of the extension end 32A of the second contact structure 32.

[0157] The method for preparing the memory provided in the above embodiment further forms a third signal line 23, by forming a third contact structure 33 having an extension end 33A on the active pillar 1 corresponding to the third signal line 23. The formation of the above structure enables the storage device to be formed on the first contact structure 31, the extension end 32A of the second contact structure 32, and the extension end 33A of the third contact structure 33 to form a misalignment; further, since the extension end 33A and the extension end 32A of the second contact structure 32 have opposite extension directions, the storage device formed on the extension end 32A of the second contact structure 32 and the storage device formed on the extension end 33A of the third contact structure 33 are respectively misaligned in opposite directions relative to the storage device formed on the first contact structure 31, and the formation of this structure enables multiple storage devices to be arranged in a hexagonal grid, thereby further reducing the required spacing between adjacent signal lines. Therefore, the method for preparing the memory in the above embodiment is conducive to further reducing the occupied area of ​​the storage unit and achieving a higher storage density.

[0158] It should be noted that there is no restriction on the order of step S21, step S22 and the above steps, that is, any one of the three can be executed first or simultaneously.

[0159] In some embodiments, the method for manufacturing the memory may further include the following step: forming a capacitor 4 corresponding to the storage node contact region 30 of the contact structure 3 .

[0160] The capacitors 4 located in the same row and adjacent to each other are staggered in the first direction (eg, X direction) and / or the second direction (eg, Y direction), and the plurality of capacitors 4 are arranged in a hexagonal grid, with each capacitor 4 located at a vertex and a center of the hexagon.

[0161] Taking the multiple contact structures 3 including multiple first contact structures 31, multiple second contact structures 32 and multiple third contact structures 33 as an example, in some embodiments, the preparation method of the memory may further include the following steps: forming capacitors 4 on the extension ends 32A of the first contact structures 31, the second contact structures 32 and the extension ends 33A of the third contact structures 33. Among them, the capacitors 4 adjacent to each other in the second direction (for example, the Y direction) may be staggered in the first direction (for example, the X direction), and the multiple capacitors 4 may be arranged in a hexagonal grid, and each capacitor 4 may be located at the vertex and the center of the hexagon respectively.

[0162] In some embodiments, the signal line group 2 is formed as a bit line group. Figure 6As shown in FIG. 1 (a), the signal line group 2 may include a first bit line BL1 and a second bit line BL2 spaced apart in a second direction (e.g., the Y direction). The first bit line BL1 and the second bit line BL2 both extend in a first direction (e.g., the X direction) and connect the active pillars 1 in the same row in series. Figure 6 As shown in FIG. 8( a ), the signal line group 2 includes a first bit line BL1 , a second bit line BL2 , and a third bit line BL3 which are spaced apart in a second direction (eg, the Y direction).

[0163] In some embodiments, the method for manufacturing the memory may further include the following steps: forming a plurality of word lines WL spaced apart in a first direction (eg, X direction). The word lines WL may extend along a second direction (eg, Y direction) and be arranged corresponding to the active pillars 1 in the same column.

[0164] In some other embodiments, the signal line group 2 is a word line group. Figure 6 As shown in FIG. 2( b), the signal line group 2 may include a first word line WL1 and a second word line WL2 spaced apart in a second direction (e.g., the Y direction). The first word line WL1 and the second word line WL2 both extend in a first direction (e.g., the X direction) and connect the active pillars 1 in the same row in series. Figure 6 As shown in FIG. 2( b ), the signal line group 2 includes a first word line WL1 , a second word line WL2 , and a third word line WL3 which are spaced apart in a second direction (eg, the Y direction).

[0165] In other embodiments, the method for preparing the memory may further include the following steps: forming a plurality of bit lines BL spaced apart in a first direction (eg, X direction), the bit lines BL may extend along a second direction (eg, Y direction) and connect active pillars 1 in the same column in series.

[0166] As an example, see Fig. 9 The first contact structure 31 and the second contact structure 32 may be formed by, but not limited to, the following steps S10 to S70:

[0167] S10: forming a first isolation material layer on the substrate.

[0168] S20: forming first grooves extending along a first direction (eg, X direction) and spaced apart in a second direction (eg, Y direction) in the first isolation material layer; the first grooves expose the top surface of the active pillar 1, and the retained first isolation material layer serves as a first isolation layer.

[0169] S30 : forming a sacrificial material layer filling the first trench and covering the first isolation layer.

[0170] S40: forming a patterned hard mask layer on the sacrificial material layer; a first mask pattern and a second mask pattern extending along a second direction (e.g., Y direction) and arranged at intervals in a first direction (e.g., X direction) are formed in the patterned hard mask layer, the orthographic projection of the first mask pattern on the substrate is located directly above the first signal line 21, and the orthographic projection of the second mask pattern on the substrate is offset from the second signal line 22 in the first direction (e.g., X direction).

[0171] S50: etching the sacrificial material layer based on the first mask pattern and the second mask pattern to form a filling hole; the filling hole exposes the top surface of the active column 1 connected to the first signal line 21 and a portion of the top surface of the active column 1 connected to the second signal line 22; the retained sacrificial material layer serves as a sacrificial layer.

[0172] S60: filling the filling hole with a second isolation layer.

[0173] S70 : removing the sacrificial layer to expose the top surface of the active pillar 1 connected to the first signal line 21 and another portion of the top surface of the active pillar 1 connected to the second signal line 22 .

[0174] S80: forming a contact layer on the active pillar 1 ; wherein the contact layer formed on the active pillar 1 connected to the first signal line 21 serves as the first contact structure 31 , and the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as the second contact structure 32 .

[0175] In order to more clearly explain the above steps, the following embodiments take the signal line group 2 as a word line group, including a plurality of word lines WL spaced apart in the second direction (eg, the Y direction) as an example, and combine Figures 10 to 35 Understand.

[0176] It should be noted that the above steps S10 to S70 should be performed after forming a plurality of signal line groups 2. Therefore, a plurality of active pillars 1 arranged in rows along a first direction (e.g., X direction) and in columns along a second direction (e.g., Y direction) and a plurality of signal line groups 22 arranged at intervals in the second direction (e.g., Y direction) have been formed on the substrate 10. As mentioned above, the signal line group 22 may include a first signal line 21 and a second signal line 22 arranged at intervals in the second direction (e.g., Y direction), and the first signal line 21 and the second signal line 22 both extend along the first direction (e.g., X direction) and are arranged corresponding to the active pillars 1 located in the same row.

[0177] In step S10, Fig.10 Figure (a) in Fig.10 Figure (b) in Fig.10 Figure (c) in Fig.10 Figure (d) and Fig.10As shown in FIG. 8( e ), a first isolation material layer 301 is formed on the substrate 10 .

[0178] The present embodiment of the present application does not specifically limit the constituent material of the first isolation material layer 301. As an example, the constituent material of the first isolation material layer 301 may include but is not limited to silicon nitride (SiN x ).

[0179] In some embodiments, the first isolation material layer 301 may be formed by the following steps, for example:

[0180] A first isolation material is deposited on the substrate 10 by a deposition process, and the first isolation material can cover the active pillar 1 and fill the gap between adjacent word lines WL. Afterwards, the first isolation material is planarized, and the first isolation material of about tens of nanometers is continuously deposited to form a first isolation material layer 301.

[0181] As an example, the planarization process may include but is not limited to a chemical mechanical polishing (Chemical Mechanical Polishing, CMP for short) process.

[0182] In step S20, first trenches T1 extending along a first direction (e.g., X direction) and arranged at intervals in a second direction (e.g., Y direction) are formed in the first isolation material layer 301, and the first trenches T1 can expose the top surface of the active pillar 1. Afterwards, the retained first isolation material layer 301 is used as the first isolation layer 302.

[0183] See also Figures 11 to 16 As an example, the first trench T1 may be formed in the first isolation material layer 301 by, but not limited to, the following steps, for example:

[0184] like Fig.11 Figure (a) in Fig.11 Figure (b) in Fig.11 Figure (c) in Fig.11 Figure (d) and Fig.11 As shown in FIG. 5( e ), a first amorphous carbon layer (ACL) 301A, a first silicon oxynitride (SiON) layer 301B, a first spin on hardmask (SOH) layer 301C, and a second silicon oxynitride layer 301D are sequentially deposited on the surface of the structure obtained in the aforementioned step S10.

[0185] It can be understood that in the embodiment of the present application, the first spin-coated hard mask layer 301C can be formed by a spin coating process; for example, the first spin-coated hard mask layer 301C can be a hydrocarbon (C x Hy ) system, which may include a silicon hard mask material, a carbon hard mask material, an organic hard mask material, and the like.

[0186] like Fig.12 Figure (a) in Fig.12 Figure (b) in Fig.12 Figure (c) in Fig.12 Figure (d) and Fig.12 As shown in FIG. 5( e) , a first photoresist (PR) layer is formed on the surface of the structure obtained in the aforementioned step; a first mask pattern is formed according to the spacing (BL Pitch) between adjacent bit lines BL, and the first photoresist layer is exposed and developed to transfer the first mask pattern to the first photoresist layer to form a first patterned photoresist layer 301E.

[0187] like Fig.13 Figure (a) in Fig.13 Figure (b) in Fig.13 Figure (c) in Fig.13 Figure (d) and Fig.13 As shown in FIG. 8( e ), the second silicon oxynitride layer 301D and the first spin-coated hard mask layer 301C are etched based on the first patterned photoresist layer 301E to transfer the first mask pattern into the second silicon oxynitride layer 301D and the first spin-coated hard mask layer 301C.

[0188] like Fig.14 Figure (a) in Fig.14 Figure (b) in Fig.14 Figure (c) in Fig.14 Figure (d) and Fig.14 As shown in FIG. 8( e ), a first silicon oxide (SiO 2 ) layer 301F is deposited on the sidewalls and top of the retained second silicon oxynitride layer 301D and the first spin-on hard mask layer 301C.

[0189] like Fig.15 Figure (a) in Fig.15 Figure (b) in Fig.15 Figure (c) in Fig.15 Figure (d) and Fig.15As shown in FIG. (e), the first silicon oxide layer 301F and the first spin-coated hard mask layer 301C deposited in the above step are anisotropically etched to remove the second silicon oxynitride layer 301D, the first spin-coated hard mask layer 301C, and the first silicon oxide layer 301F located on top of the second silicon oxynitride layer 301D and the first spin-coated hard mask layer 301C. It can be understood that anisotropic etching can selectively etch materials in a preset crystal direction or crystal plane direction, while leaving only a few or almost no etching marks in other directions. In the above step, the use of anisotropic etching to remove the second silicon oxynitride layer 301D, the first spin-coated hard mask layer 301C, and the first silicon oxide layer 301F located on top of the second silicon oxynitride layer 301D and the first spin-coated hard mask layer 301C can make the morphology of the resulting structure more accurate and controllable.

[0190] like Fig.16 Figure (a) in Fig.16 Figure (b) in Fig.16 Figure (c) in Fig.16 Figure (d) and Fig.16 As shown in FIG. (e), the first silicon oxide layer 301F retained in the previous step is used as a mask to anisotropically etch the first amorphous carbon layer 301A. Then, the first silicon oxide layer 301F is removed, and the first amorphous carbon layer 301A is used as a hard mask to anisotropically etch the first isolation material layer 301 to form first trenches T1 extending along a first direction (e.g., X direction) and arranged at intervals in a second direction (e.g., Y direction) in the first isolation material layer 301, and the retained first isolation material layer 301 serves as the first isolation layer 302.

[0191] In step S30, Fig.17 Figure (a) in Fig.17 Figure (b) in Fig.17 Figure (c) in Fig.17 Figure (d) and Fig.17 As shown in FIG. 8( e ), a sacrificial material layer 303 is formed to fill the first trench T1 and cover the first isolation layer 302 .

[0192] The present embodiment of the application does not specifically limit the material of the sacrificial material layer 303. As an example, the material of the sacrificial material layer 303 may include silicon oxide. The present embodiment of the application does not specifically limit the method of forming the sacrificial material layer 303. As an example, the sacrificial material layer 303 may be formed by, but not limited to, atomic layer deposition (ALD).

[0193] In step S40, a patterned hard mask layer is formed on the sacrificial material layer 303. The patterned hard mask layer is formed with a first mask pattern and a second mask pattern extending along the second direction (e.g., the Y direction) and arranged in a first direction (e.g., the X direction). The orthographic projection of the first mask pattern on the substrate 10 is located directly above the first signal line 21, and the orthographic projection of the second mask pattern on the substrate 10 is offset from the second signal line 22 in the first direction (e.g., the X direction).

[0194] See also Figures 18 to 22 As an example, the patterned hard mask layer may be formed on the sacrificial material layer 303 by, but not limited to, the following steps, such as:

[0195] like Fig.18 Figure (a) in Fig.18 Figure (b) in Fig.18 Figure (c) in Fig.18 Figure (d) and Fig.18 As shown in FIG. 5( e ), a second amorphous carbon layer 301A′, a third silicon oxynitride layer 301B′, a second spin-on hard mask layer 301C′ and a fourth silicon oxynitride layer 301D′ are sequentially deposited on the surface of the structure obtained in step S30 .

[0196] like Fig.19 Figure (a) in Fig.19 Figure (b) in Fig.19 Figure (c) in Fig.19 Figure (d) and Fig.19 As shown in FIG. (e), a second photoresist layer is formed on the surface of the structure obtained in the above step; a second mask pattern is formed according to the spacing (WL Pitch) between adjacent word lines WL, and the second photoresist layer is exposed and developed to transfer the second mask pattern to the second photoresist layer to form a second patterned photoresist layer 301E'. It should be noted that the extension direction of the second patterned photoresist layer 301E' formed in this step intersects with the extension direction of the first trench T1 formed in step S30 at a certain angle; for example, 30°, 45° or 60°.

[0197] like Fig. 20 Figure (a) in Fig. 20 Figure (b) in Fig. 20 Figure (c) in Fig. 20 Figure (d) and Fig. 20 As shown in FIG. 8( e ), the fourth silicon oxynitride layer 301D′ and the second spin-coated hard mask layer 301C′ are etched based on the second patterned photoresist layer 301E′ to transfer the second mask pattern into the fourth silicon oxynitride layer 301D′ and the second spin-coated hard mask layer 301C′.

[0198] like Fig.21 Figure (a) in Fig.21 Figure (b) in Fig.21 Figure (c) in Fig.21 Figure (d) and Fig.21 As shown in FIG. 5( e ), a second silicon oxide layer 301F′ is deposited on the sidewalls and top of the retained fourth silicon oxynitride layer 301D′ and the second spin-on hard mask layer 301C′.

[0199] like Fig. 22 Figure (a) in Fig. 22 Figure (b) in Fig. 22 Figure (c) in Fig. 22 Figure (d) and Fig. 22 As shown in FIG. 5( e) , the fourth silicon oxynitride layer 301D′ located above the second spin-coated hard mask layer 301C′ and the second silicon oxide layer 301F′ located on the top surface of the second spin-coated hard mask layer 301C′ in the structure obtained in the above steps are removed; then, a third spin-coated hard mask layer 301C″ is coated on the obtained structure and isotropically etched.

[0200] The second silicon oxide layer 301F', the third silicon oxynitride layer 301B' and the second amorphous carbon layer 301A' are sequentially etched, and the second spin-on hard mask layer 301C' and the third spin-on hard mask layer 301C" are removed; then, the retained second amorphous carbon layer 301A' is used as the first mask pattern and the second mask pattern.

[0201] Please combine Fig.23 Understand the first mask pattern and the second mask pattern in the above steps. In the embodiment of the present application, the second trench T2 and the third trench T3 intersecting at a certain angle can be etched in the second amorphous carbon layer 301A', and the overlap of the second trench T2 and the third trench T3 can define the shape and position of the filling hole in the subsequent steps. Fig.23 As shown, the positions and shapes of the second trench T2 and the third trench T3 can be adaptively set according to actual needs, as long as the filling hole formed in the subsequent steps can expose the top surface of the active pillar 1 connected to the first signal line 21 and a portion of the top surface of the active pillar 1 connected to the second signal line 22. Among them, the top surface of the active pillar 1 connected to the first signal line 21 exposed can be used to define the shape and position of the first contact structure 31, and the top surface of the active pillar 1 connected to the second signal line 22 exposed can be used to define the shape and position of the second contact structure 32.

[0202] In step S50, Fig.24 Figure (a) in Fig.24 Figure (b) in Fig.24 Figure (c) and Fig.24 As shown in FIG. 3( d ), the sacrificial material layer 303 is etched based on the first mask pattern and the second mask pattern to form a filling hole T. The filling hole T exposes the top surface of the active pillar 1 connected to the first signal line 21 and a portion of the top surface of the active pillar 1 connected to the second signal line 22. It should be noted that the retained sacrificial material layer 303 serves as a sacrificial layer 304.

[0203] Please combine Figure 25 to Figure 26 Understand the above steps S40 and S50. Fig.23 As shown, since the second trench T2 and the third trench T3 formed by etching in the above steps intersect at a certain angle, the resulting structure is Fig.23 The cross sections in the AA' direction, the BB' direction and the CC' direction shown in the figure are different. The second silicon oxynitride layer 301D located above the spin-coated hard mask layer 301C and the silicon oxide layer 301F located on the top surface of the spin-coated hard mask layer 301C in the structure obtained in the above steps are removed; then, the spin-coated hard mask layer 301C is coated on the obtained structure, and the isotropic etching is performed. Fig.23 For example, the cross section in the BB' direction Fig.25 Figure (a) and Fig.25 As shown in Figure (b) of Fig.23 For example, the cross section in the CC' direction Fig.26 Figure (a) and Fig.26 As shown in FIG. (b) in FIG. Based on this, the filling hole T etched in step S50 will also be different. Among them, the filling hole T is Fig.23 For example, the cross section in the BB' direction Fig.25 Figure (c) and Fig.25 As shown in Figure (d) of Fig.23 For example, the cross section in the CC' direction Fig.26 Figure (c) and Fig.26 As shown in Figure (d).

[0204] In step S60, if Figure 27 to Figure 29 As shown, the filling hole T is filled with a second isolation layer 305 .

[0205] in, Fig. 27 Figure (a) and Fig. 27 The (b) figure shows: based on Fig.24 Figure (a) and Fig.24 In the structure shown in FIG. 2 (b), the second isolation layer 305 is filled in the filling hole T. Fig.28 Figure (a) and Fig.28 The (b) figure shows: based on Fig.25 Figure (c) and Fig.25In the structure shown in FIG. 5 (d), the second isolation layer 305 is filled in the filling hole T. Fig.29 Figure (a) and Fig.29 The (b) figure shows: based on Fig.26 Figure (c) and Fig.26 In the structure shown in FIG. 5 (d), the second isolation layer 305 is filled in the filling hole T.

[0206] In step S70, if Figure 30 to Figure 32 As shown, the sacrificial layer 304 is removed to expose the top surface of the active pillar 1 connected to the first signal line 21 and another portion of the top surface of the active pillar 1 connected to the second signal line 22 .

[0207] in, Fig.30 Figure (a) and Fig.30 The (b) figure shows: based on Fig. 27 Figure (a) and Fig. 27 In the structure shown in FIG. 2 (b), the sacrificial layer 304 is removed to expose the top surface of the active pillar 1 connected to the first signal line 21. Fig.31 Figure (a) and Fig.31 The (b) figure shows: based on Fig.28 Figure (a) and Fig.28 In the structure shown in FIG. 2( b ), the sacrificial layer 304 is removed to expose another portion of the top surface of the active pillar 1 connected to the second signal line 22 . Fig.32 Figure (a) and Fig.32 The (b) figure shows: based on Fig.29 Figure (a) and Fig.29 In the structure shown in FIG. 2( b ), the sacrificial layer 304 is removed to expose another portion of the top surface of the active pillar 1 connected to the second signal line 22 .

[0208] In step S80, if Figure 33 to Figure 35 As shown, a contact layer is formed on the active pillar 1 ; wherein the contact layer formed on the active pillar 1 connected to the first signal line 21 serves as a first contact structure 31 , and the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as a second contact structure 32 .

[0209] in, Fig.33 Figure (a) and Fig.33 The (b) figure shows: based on Fig.30 Figure (a) and Fig.30 In the structure shown in FIG. 2 ( b ), the contact layer formed on the active pillar 1 connected to the first signal line 21 serves as the first contact structure 31 .

[0210] In some embodiments, Fig.34Figure (a) and Fig.34 The (b) figure shows: based on Fig.31 Figure (a) and Fig.31 In the structure shown in FIG. (b), the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as the second contact structure 32. At this time, Fig.35 Figure (a) and Fig.35 The (b) figure shows: based on Fig.32 Figure (a) and Fig.32 In the structure shown in FIG. (b), the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as the third contact structure 33. Alternatively, in some other embodiments, Fig.34 Figure (a) and Fig.34 The (b) figure shows: based on Fig.31 Figure (a) and Fig.31 In the structure shown in FIG. (b), the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as the third contact structure 33. At this time, Fig.35 Figure (a) and Fig.35 The (b) figure shows: based on Fig.32 Figure (a) and Fig.32 In the structure shown in FIG. 2 ( b ), the contact layer formed on the active pillar 1 connected to the second signal line 22 serves as the second contact structure 32 .

[0211] The present embodiment does not specifically limit the constituent materials of the first contact structure 31 and the second contact structure 32. As an example, the constituent materials of the first contact structure 31 and the second contact structure 32 may include at least one of titanium (Ti), nickel (Ni) and cobalt (Co).

[0212] In some embodiments, after step S22, the method for preparing the memory may further include the following steps:

[0213] The capacitor 4 is formed on the first contact structure 31 and the extending end 32A of the second contact structure 32 .

[0214] It can be understood that in the method for preparing the memory provided in the above embodiment, the capacitors 4 adjacent to each other in the second direction (for example, the Y direction) can be staggered in the first direction (for example, the X direction), and a plurality of capacitors 4 can be arranged in a hexagonal grid, and each capacitor 4 can be located at the vertex and the center of the hexagon, respectively.

[0215] In addition, it should be noted that the memory preparation methods provided in the embodiments of the present application can be used to prepare corresponding memories. Therefore, the technical features between the aforementioned method embodiments and structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.

[0216] According to some embodiments, the present application also provides an electronic device, such as a data storage device, a copier, a network device, a home appliance, an instrument, a mobile phone, a computer, or other device with a data storage function.

[0217] The electronic device may include the memory provided by any of the above embodiments. It is understood that the structure of the memory can refer to the relevant descriptions in some of the above embodiments. In addition, the electronic device may also include other necessary elements or components, which are not specifically limited in this application.

[0218] The electronic device provided by the above embodiment includes the memory provided by the above embodiment. Therefore, the technical effects that can be achieved by the memory provided by the above embodiment can also be achieved by the above electronic device, which will not be described in detail here.

[0219] It should be understood that although Figures 7 to 9 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 7 to 9 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0220] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A memory, characterized in that: include: A plurality of active pillars are arranged in rows along a first direction on the substrate, and arranged in columns along a second direction; the first direction intersects the second direction; A plurality of contact structures are respectively arranged on the tops of the corresponding active pillars; Wherein, the contact structure has a storage node contact area on the top surface away from the active pillar; The storage node contact regions of the contact structures that are located in the same row and are adjacent to each other are arranged in a staggered manner in the first direction and / or the second direction.

2. The memory according to claim 1, characterized in that: The contact structure has an extension end; the top surface of the extension end away from the active pillar is the storage node contact area of ​​the contact structure; wherein, The extending end extends along the first direction; Alternatively, the extending end extends along the second direction; Alternatively, the extending direction of the extending end intersects both the first direction and the second direction.

3. The memory according to claim 1, characterized in that: The extending directions of the extending ends of the contact structures are the same; Wherein, the extending lengths of the extending ends of the contact structures that are located in the same row and adjacent to each other are different.

4. The memory according to claim 1, characterized in that: The memory also includes: A plurality of signal line groups arranged at intervals in the second direction; the signal line groups include first signal lines and second signal lines arranged at intervals in the second direction, the first signal lines and the second signal lines both extend along the first direction and are arranged corresponding to the active pillars located in the same row; The plurality of contact structures include a plurality of first contact structures and a plurality of second contact structures; wherein, The first contact structure is disposed on the active pillar corresponding to the first signal line; the top surface of the first contact structure away from the active pillar is the storage node contact area of ​​the first contact structure; The second contact structure is disposed on the active pillar corresponding to the second signal line and has an extension end; a top surface of the extension end away from the active pillar is the storage node contact region of the second contact structure.

5. The memory according to claim 4, characterized in that: The extending end of the second contact structure extends along the first direction; Alternatively, the extending end of the second contact structure extends along the second direction; Alternatively, an extending direction of the extending end of the second contact structure intersects with the first direction and the second direction.

6. The memory according to claim 4, characterized in that: The signal line group further includes a third signal line spaced apart from the first signal line in the second direction, the third signal line and the second signal line are respectively located on two opposite sides of the first signal line in the second direction, extend along the first direction and are arranged corresponding to the active pillars located in the corresponding row; The plurality of contact structures further comprises a plurality of third contact structures; The third contact structure is disposed on the active pillar corresponding to the third signal line and has an extension end; the top surface of the extension end away from the active pillar is the storage node contact area of ​​the third contact structure; Wherein, the extending end of the third contact structure and the extending end of the second contact structure extend in opposite directions.

7. The memory according to claim 1, characterized in that: Also includes: A plurality of capacitors, each located in the storage node contact region corresponding to the contact structure; The capacitors located in the same row and adjacent to each other are staggered in the first direction and / or the second direction, and a plurality of the capacitors are arranged in a hexagonal grid, with each capacitor being located at a vertex and a center of the hexagon.

8. A method for preparing a memory, characterized in that: include: Providing a substrate, wherein the substrate is formed with a plurality of active pillars arranged in rows along a first direction and in columns along a second direction; the first direction intersects the second direction; A contact structure is formed correspondingly on the top of each active pillar; the contact structure has a storage node contact area on the top surface away from the active pillar, and the storage node contact areas of the contact structures located in the same row and adjacent to each other are staggered in the first direction and / or the second direction.

9. The method for preparing a memory according to claim 8, characterized in that: Also includes: forming a plurality of signal line groups spaced apart in the second direction; the signal line groups comprising first signal lines and second signal lines spaced apart in the second direction, the first signal lines and the second signal lines both extending along the first direction and being arranged corresponding to the active pillars in the same row; The contact structure is formed correspondingly on the top of each active pillar, including: forming a first contact structure on the active pillar corresponding to the first signal line; The top surface of the first contact structure facing away from the active pillar is the storage node contact area of ​​the first contact structure; A second contact structure is formed on the active pillar corresponding to the second signal line; the second contact structure is formed with an extension end, and the top surface of the extension end away from the active pillar is the storage node contact area of ​​the second contact structure.

10. The method for preparing a memory according to claim 9, characterized in that: The signal line group further includes a third signal line spaced apart from the first signal line in the second direction, the third signal line and the second signal line are respectively located on two opposite sides of the first signal line in the second direction, extend along the first direction and are arranged corresponding to the active pillars located in the corresponding row; The contact structure is formed correspondingly on the top of each active pillar, and further includes: forming a third contact structure on the active pillar corresponding to the third signal line; The third contact structure is formed with an extension end, and the top surface of the extension end away from the active pillar is the storage node contact area of ​​the third contact structure; the extension end of the third contact structure and the extension end of the second contact structure extend in opposite directions.

11. The method for preparing a memory according to claim 9, characterized in that: The first contact structure is formed on the active pillar connected to the first signal line, and the second contact structure is formed on the active pillar connected to the second signal line, including: forming a first isolation material layer on the substrate; forming first grooves extending along the first direction and arranged at intervals in the second direction in the first isolation material layer; the first grooves expose the top surfaces of the active pillars, and the first isolation material layer is retained as a first isolation layer; forming a sacrificial material layer filling the first trench and covering the first isolation layer; A patterned hard mask layer is formed on the sacrificial material layer; a first mask pattern and a second mask pattern are formed in the patterned hard mask layer, the first mask pattern extending along the second direction and arranged at intervals in the first direction, the orthographic projection of the first mask pattern on the substrate is located directly above the first signal line, and the orthographic projection of the second mask pattern on the substrate is offset from the second signal line in the first direction; The sacrificial material layer is etched based on the first mask pattern and the second mask pattern to form a filling hole; the filling hole exposes the top surface of the active pillar connected to the first signal line and a portion of the top surface of the active pillar connected to the second signal line; the sacrificial material layer is retained as a sacrificial layer; Filling a second isolation layer in the filling hole; removing the sacrificial layer to expose a top surface of the active pillar connected to the first signal line and another portion of the top surface of the active pillar connected to the second signal line; A contact layer is formed on the active pillar; wherein the contact layer formed on the active pillar connected to the first signal line serves as the first contact structure, and the contact layer formed on the active pillar connected to the second signal line serves as the second contact structure.

12. The method for preparing a memory according to any one of claims 8 to 11, characterized in that: Also includes: A capacitor is formed corresponding to the storage node contact area of ​​the contact structure; wherein the capacitors located in the same row and adjacent to each other are staggered in the first direction and / or the second direction, and multiple capacitors are arranged in a hexagonal grid, and each capacitor is located at the vertex and center of the hexagon.

13. An electronic device, characterized in that: include: A memory as claimed in any one of claims 1 to 7.

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