Three-dimensional integrated circuit and through silicon via fault-tolerant repair circuit and fault-tolerant repair method thereof

Abstract

The present invention provides a three-dimensional integrated circuit and a through silicon via fault-tolerant repair circuit and a fault-tolerant repair method thereof. The fault-tolerant repair circuit includes a signal input module, an electric heat management module, a first routing module, a through silicon via array, a fault detection circuit module, a second routing module, a through silicon via status register and a signal output module; the signal input module is used to output a signal to the first routing module; the electric heat management module is used to determine the fault state of the through silicon via and the management of through-hole reuse; a plurality of working through silicon vias and redundant through silicon vias are arranged in the through silicon via array; the first routing module is used to output a signal to the through silicon via array; the fault detection circuit module is used to perform fault detection on the through silicon via; the through silicon via status register is used to store the fault state data of the through silicon via; and the signal output module is used to output a signal to the outside. The three-dimensional integrated circuit has the above-mentioned through silicon via fault-tolerant repair circuit. The present invention can improve the test efficiency of the three-dimensional integrated circuit and reduce the test cost.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional integrated circuits, and in particular to a three-dimensional integrated circuit and a through silicon via fault-tolerant repair circuit and a fault-tolerant repair method thereof. Background Art

[0002] Chiplet technology integrates multiple modular small chips (mainly in the form of bare chips) in a package through internal interconnection to form a heterogeneous chip with dedicated functions. This technology solves the problems of scale, high cost and long cycle faced in the chip development process. Through silicon via technology is a vertical interconnection path technology formed in a three-dimensional integrated circuit. It completely passes through the silicon chip or wafer to achieve the stacking and interconnection of silicon chips. Through silicon via technology allows vertical connection between chiplets, thereby achieving the stacking of multiple layers of chips, increasing the system's integration and functional density, improving the integration of the chip system, and expanding the performance of the chip system. It also has the advantages of reducing the power consumption of the chip system and optimizing space, and breaking through the physical and material limitations of the current three-dimensional integrated circuit development.

[0003] In March 2022, Intel and ten other chip giants jointly founded the Chiplet Standards Alliance and officially launched the universal interconnection standard "UCle" (Universal Chiplet Interconnect Express, UCIe). This standard aims to break down the link protocol barriers between different chip manufacturers and build an open and interoperable chiplet ecosystem.

[0004] Although the universal interconnection standard solves the interconnection problem between cores of different manufacturers, the current manufacturing and interconnection based on silicon vias brings the following problems, which affect the chip yield.

[0005] The first is the design process problem. When designing the through silicon via interconnection of a chip, a major challenge is that the redundant fault-tolerant repair ratio of the through silicon via is difficult to flexibly select according to the actual needs of the circuit. If the redundant fault-tolerant repair performance requirements of the through silicon via are too high, a large number of through silicon vias will need to be set up, resulting in a waste of resources. If the redundant fault-tolerant repair performance requirements of the through silicon via are too low, the reliability requirements of the three-dimensional integrated circuit may not be met. In addition, due to differences in the point tools and core grain design stages of each process, the fault-tolerant repair design of the through silicon via becomes particularly complicated. At the same time, there is also the problem of interconnection fault-tolerant repair design between existing finished products and new designs.

[0006] The second is the problem of chip fault tolerance and repair. Although built-in test links and redundant resources can improve the reliability of test links, this does not directly equate to enhancing the self-repair capability of the tested chiplets, which is a common problem in advanced packaged integrated circuits. In order to improve the fault tolerance and repair capabilities of chiplets, it is necessary to group through-silicon vias in the early layout and routing stage, evaluate routing resources after the routing stage, and finally use simulation tools for collaborative optimization to simulate the design of fault-tolerant repair redundant circuits. It may also be necessary to develop more complex fault detection and recovery mechanisms, such as integrating additional hardware or software modules to achieve self-diagnosis and repair functions.

[0007] The third is other potential problems, such as the electro-thermal management of TSVs. As the number of cores increases and the density increases, the heat dissipation problem becomes more severe. Most TSV failures are related to electro-thermal effects. Therefore, optimizing electro-thermal management becomes the key to solving TSV failures. Summary of the invention

[0008] The first object of the present invention is to provide a through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit that can simplify the chip design process.

[0009] A second object of the present invention is to provide a three-dimensional integrated circuit having the above-mentioned through silicon via fault-tolerant repair circuit.

[0010] A third object of the present invention is to provide a through silicon via fault-tolerant repair method implemented by using the through silicon via fault-tolerant repair circuit of the above-mentioned three-dimensional integrated circuit.

[0011] To achieve the first objective of the present invention, the TSV fault-tolerant repair circuit of the three-dimensional integrated circuit provided by the present invention comprises a signal input module, an electro-thermal management module, a first routing module, a TSV array, a fault detection circuit module, a second routing module, a TSV status register and a signal output module; wherein the signal input module is used to receive signals sent from the outside and output signals to the first routing module; the electro-thermal management module is used to determine the fault status of each TSV according to the data recorded in the TSV status register, and thermally connect the TSV with faults or excessive temperature to perform multiplexing management of thermal through vias and electrical through vias; a plurality of working TSVs and a plurality of redundant TSVs are arranged in the TSV array; the first routing module outputs signals to the TSV array according to the signals output by the signal input module and the electro-thermal management module to switch the TSV used for signal transmission; the fault detection circuit module is used to perform fault detection on the TSV, and send the detection results to the TSV status register and the signal output module through the second routing module; the TSV status register is used to store the fault status data of each TSV; the signal output module is used to output signals to the outside.

[0012] It can be seen from the above scheme that the silicon via fault-tolerant repair circuit of the three-dimensional integrated circuit provides a unified design circuit generation interface to the outside world, which can directly generate the hardware description language of the module on the logic synthesis output netlist, including setting up a signal input module and a signal output module, making the silicon via fault-tolerant repair process simpler and more efficient, thereby simplifying the chip design process and improving the chip design efficiency.

[0013] A preferred solution is that in the TSV array, the number of working TSVs is twice the number of redundant TSVs, and two adjacent working TSVs and one redundant TSV are arranged in a triangular positional relationship.

[0014] It can be seen that by reasonably arranging the TSVs in the TSV array, the number of redundant TSVs can be minimized while satisfying the function of fault-tolerant modification, thereby reducing resource waste and meeting the reliability requirements of three-dimensional integrated circuits.

[0015] A further solution is that each redundant through silicon via is connected to the first routing module and receives a signal sent by the first routing module.

[0016] It can be seen that the first routing module controls the signal to be transmitted from each redundant TSV or multiple working TSVs, thereby realizing the switching of working TSVs and redundant TSVs, thereby meeting the requirements of the fault-tolerant repair function. In this way, the first routing module can quickly realize the switching of the signal transmission path.

[0017] An optional solution is that when two adjacent working TSVs and one redundant TSV are arranged in a triangular positional relationship, the two adjacent working TSVs and one redundant TSV are respectively located at vertices of an equilateral triangle.

[0018] It can be seen that the above arrangement can achieve the maximum benefit with the minimum number of redundant through silicon vias, and can also expand the horizontal and vertical thermal areas.

[0019] A further solution is that the first routing module includes a multiplexer and a demultiplexer, the multiplexer is used to select a signal line connected to the target through silicon via according to a received signal, and the demultiplexer is used to send the signal of the target through silicon via to multiple receiving ends.

[0020] It can be seen that the signal input and output processing of the first routing module can be realized through the multiplexer and the demultiplexer, and the signal of the target through silicon via can be controlled.

[0021] A further solution is that the fault detection circuit module performs a fault test on the through silicon via including: calculating short circuit characteristic parameters of the through silicon via in an AC short circuit test and a DC short circuit characteristic parameter.

[0022] It can be seen that the fault detection circuit module is capable of detecting the short-circuit characteristics of the through silicon via in the AC test and the short-circuit characteristics of the through silicon via in the DC test, and then distinguishing and identifying the fault types of the through silicon via.

[0023] A further solution is that the TSV status register has two register status units, and the fault type of the TSV is determined using data recorded in the two register status units.

[0024] It can be seen that by recording the data of the TSV fault type through the two register status units, the electric thermal management module can quickly identify the TSV fault type by reading the data recorded by the two register status units.

[0025] To achieve the second objective, the three-dimensional integrated circuit provided by the present invention integrates the above-mentioned through silicon via fault-tolerant repair circuit of the three-dimensional integrated circuit.

[0026] To achieve the third purpose mentioned above, the silicon via fault-tolerant repair method of a three-dimensional integrated circuit provided by the present invention is applied to the silicon via fault-tolerant repair circuit of the three-dimensional integrated circuit mentioned above, and the method includes: performing layout based on an electro-thermal management module, a first routing module, a second routing module and a fault detection circuit module, determining the fault tolerance ratio of the silicon via fault-tolerant repair circuit according to the acquired data, and calculating the area and position of the silicon via fault-tolerant repair circuit; optimizing the layout of each silicon via in the silicon via array according to the arrangement of each silicon via, adding input redundancy ratio, redundant silicon vias and redundant circuit wiring, and performing circuit wiring of the first routing module, the second routing module, the electro-thermal management module and the fault detection circuit module; importing an electro-thermal model and simulating the silicon via fault-tolerant repair circuit, optimizing the connection of the redundant circuit and adjusting the fault tolerance ratio according to the hot spot distribution of the simulation results.

[0027] It can be seen from the above scheme that the silicon via fault-tolerant repair method of the present invention is implemented by using a silicon via fault-tolerant repair circuit with a unified interface, which can directly generate the hardware description language of the module and output the netlist after logic synthesis, which can simplify the chip design and testing process, thereby reducing the production cost of the chip and improving the production efficiency of the chip.

[0028] A preferred solution is to optimize the heat dissipation structure of the three-dimensional integrated circuit and design temperature monitoring points after adding input redundancy ratio, redundant through silicon vias and redundant circuit wiring.

[0029] It can be seen that by optimizing the heat dissipation structure of the three-dimensional integrated circuit and designing temperature monitoring points, the heat dissipation performance of the three-dimensional integrated circuit can be improved, and the temperature inside the three-dimensional integrated circuit can be effectively monitored and the transmission path of the circuit signal can be controlled according to the actual temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural block diagram of an embodiment of a through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit of the present invention.

[0031] Figure 2 It is a structural diagram of a first arrangement of a through silicon via array in an embodiment of a through silicon via fault-tolerant repair circuit of a three-dimensional integrated circuit of the present invention.

[0032] Figure 3 It is a structural diagram of a second arrangement of a through silicon via array in an embodiment of a through silicon via fault-tolerant repair circuit of a three-dimensional integrated circuit of the present invention.

[0033] Figure 4 is a schematic diagram of a through silicon via failure.

[0034] Figure 5 This is the equivalent circuit diagram when the TSV does not fail.

[0035] Figure 6 This is the equivalent circuit diagram of a through silicon via open circuit failure.

[0036] Figure 7 This is the equivalent circuit diagram of a through silicon via leakage failure.

[0037] Figure 8 It is a flow chart of an embodiment of a through silicon via fault-tolerant repair method for a three-dimensional integrated circuit of the present invention.

[0038] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0039] The through silicon via fault-tolerant repair circuit of the three-dimensional integrated circuit of the present invention is used for performing fault-tolerant repair on the through silicon vias of the three-dimensional integrated circuit. The through silicon via fault-tolerant repair circuit sets a unified signal input module and a signal output module as an interface for external signal transmission, and integrates multiple modules such as an electric thermal management module, a first routing module, a through silicon via array, a fault detection circuit module, a second routing module, and a through silicon via status register to form a complete test component, which facilitates the fault-tolerant test of the through silicon vias of the three-dimensional integrated circuit, thereby improving the development and testing efficiency of the three-dimensional integrated circuit and reducing the design cost of the three-dimensional integrated circuit.

[0040] Three-dimensional integrated circuit and through silicon via fault-tolerant repair circuit thereof:

[0041] See also Figure 1 The through silicon via fault-tolerant repair circuit of the three-dimensional integrated circuit of this embodiment has a signal input module 11, an electric thermal management module 12, a first routing module 13, a through silicon via array 14, a fault detection circuit module 15, a second routing module 16, a through silicon via status register 17 and a signal output module 18.

[0042] Among them, the signal input module 11 can receive external input signals, such as receiving signals from a design for testability device (Design For Test, DFT), or receiving signals sent by on-chip modules based on protocols such as UCIe, or receiving signals sent by actual logic chip signal modules after on-chip binding. The signal input module 11 provides a unified signal input interface to the outside, which facilitates different external devices to communicate with the silicon via fault-tolerant repair circuit. The signal input module 11 sends the received signal to the first routing module 13, and the first routing module 13 outputs the received signal to the corresponding silicon via.

[0043] The electric thermal management module 12 can receive data from the TSV status register 17. Preferably, the TSV status register 17 has two register status units, which are respectively recorded as D0 and D1. The TSV status register 17 uses the two register status units D0 and D1 to record the fault type of the TSV in the TSV array 14. For example, when the data recorded in the two register status units D0 and D1 are D0=1 and D1=0, respectively, it means that the current TSV has no fault, but the temperature of the TSV is too high, and the redundant circuit needs to be enabled; when the data recorded in the two register status units D0 and D1 are D0=1 and D1=1, respectively, it means that the TSV has no fault and there is no need to switch the TSV currently in use; when the data recorded in the register status unit D0 is 0, it means that the current TSV is in a fault state, and the faulty TSV needs to be switched to a thermal via state. To this end, the electric thermal management module 12 needs to read at least the data of the two register state units D0 and D1, and the electric thermal management module 12 can read the data of the two register state units D0 and D1 in a serial manner or in a parallel manner. Preferably, one or more pins can be set between the electric thermal management module 12 and the through silicon via status register 17, and these pins communicate between the electric thermal management module 12 and the through silicon via status register 17.

[0044] After reading the data of the two register state units D0 and D1, the electric heat management module 12 determines the state of the silicon via according to the read data and performs corresponding processing. For example, when the data recorded in the register state unit D0 is 0, it means that the current silicon via is in a fault state. Then, when the faulty silicon via is switched to a thermal via state, it is equivalent to adding a control switch between the silicon via and the heat sink. When it is found that the silicon via is faulty or the temperature is too high, the silicon via can be directly connected to the heat sink for heat dissipation, so as to perform multiplexing management of thermal vias and electrical vias.

[0045] The first routing module 13 can receive signals output by the signal input module 11 and the electric thermal management module 12, and can output signals to a plurality of through silicon vias in the through silicon via array 14. Figure 2The first arrangement of the through silicon via array of this embodiment is a through silicon via array arranged in a triangular manner. Specifically, the through silicon via array has 12 working through silicon vias and 6 redundant through silicon vias. The 12 working through silicon vias are working through silicon vias 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111 and 112, which are distributed at the outermost periphery of the through silicon via array 14. The 6 redundant through silicon vias are redundant through silicon vias 201, 202, 203, 204, 205 and 206, which are arranged at the inner periphery of the through silicon via array 14. The first routing module 13 is connected to each redundant through silicon via 201, 202, 203, 204, 205, 206 and is located at the geometric center of the through silicon via array 14.

[0046] from Figure 2 It can be seen that two adjacent working TSVs and one redundant TSV form a triangular positional relationship. Taking working TSVs 101 and 102 and redundant TSV 201 as an example, working TSVs 101 and 102 and redundant TSV 201 are respectively arranged at the vertices of an equilateral triangle, that is, redundant TSV 201 can respectively establish signal connections with working TSVs 101 and 102. Similarly, working TSVs 102 and 103 and redundant TSV 202 are respectively arranged at the vertices of an equilateral triangle, and working TSVs 103 and 104 and redundant TSV 202 are respectively arranged at the vertices of an equilateral triangle.

[0047] In this embodiment, each through silicon via is filled with metal, such as copper, so each through silicon via has both electrical and thermal conductivity, that is, each through silicon via can be used as both a thermal through hole and an electrical through hole. Specifically, each working through silicon via is used as a multiplexed through hole for thermal through holes and electrical through holes. If a working through silicon via fails, the first routing module 13 can perform a through silicon via switching operation, that is, switching the signal originally transmitted through the failed working through silicon via to a redundant through silicon via for signal transmission. In this way, it can be ensured that the signal transmission will not be interrupted due to the failure of a working through silicon via. In addition, since the continuous signal transmission of the through silicon via will cause the problem of excessive temperature, for this reason, after a redundant through silicon via has been used for a period of time, it can be switched to another redundant through silicon via to avoid the problem that a redundant through silicon via is used for a long time and causes excessive temperature, thereby affecting signal transmission. Furthermore, if a working TSV is only affected by excessive temperature and affects signal transmission, it can be switched to a redundant TSV in a short time. After a period of time, when the temperature of the working TSV drops, the working TSV can be reselected for signal transmission.

[0048] The first routing module 13 is located at the center of the TSV array 14, and can output signals to each redundant TSV according to the signals output by the signal input module 11 and the electric thermal management module 12, so as to switch between the working TSV and the redundant TSV. Therefore, the first routing module 13 can dynamically change the gating state of each redundant TSV and the working TSV.

[0049] Specifically, the first routing module 13 has a set of multiplexers and demultiplexers, which are used to select a signal line connected to a target through silicon via according to the received signal, wherein the target through silicon via may be a working through silicon via or a redundant through silicon via determined according to the received signal. The function of the demultiplexer is opposite to that of the multiplexer, and the function of the demultiplexer is to send the signal of the target through silicon via to multiple receiving ends.

[0050] See also Figure 3 ,Another arrangement of TSV arrays is a rectangular grid arrangement, such as Figure 3 In the example, 16 working TSVs are provided, namely working TSVs 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315 and 316, and 12 redundant TSVs are provided, including redundant TSVs 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411 and 412. The 16 working TSVs are arranged in a 4×4 array, and the 12 redundant TSVs are also arranged in a 3×4 array.

[0051] by Figure 3 In the arrangement of the TSV array shown, assuming that the diameter of each TSV is d, the spacing between two adjacent TSVs is also d, that is, the distance between the axes of two adjacent TSVs is d, assuming that the length of the TSV array is L and the width is W, then the number of TSVs that can be arranged in the length direction is [L / d], and the number of TSVs that can be arranged in the length direction is [W / d], where [L / d] is the integer operation of L / d, and [W / d] is the integer operation of W / d. Therefore, Figure 3 The number of through silicon vias N1 that can be arranged in the through silicon via array arranged in a rectangular grid is approximately LW / d 2 .

[0052] Compared to Figure 3 The arrangement shown uses Figure 2 The triangular arrangement of the TSV array shown in the figure can arrange more TSVs in the same area. Figure 2In the arrangement shown, each TSV is located at the vertex of an equilateral triangle, and the diameter of each TSV is d. The length of each side of the equilateral triangle is also d. Therefore, in the equilateral triangle grid, each TSV is located at the vertex of an equilateral triangle. Assuming that the diameter of each TSV is still d, the length of the side of the equilateral triangle is also d, then Figure 2 The number N2 of TSVs that can be arranged in the triangular TSV array shown can be calculated using the following formula:

[0053] ,

[0054] According to the above formula, we can calculate that the ratio of N2 / N1 is approximately 4 / 3, so we use Figure 2 The triangle arrangement shown is compared to Figure 3 The rectangular network arrangement shown can increase the number of through-silicon vias. In addition, this arrangement has the following advantages:

[0055] First, it has efficient heat conduction and temperature protection. According to the heat conduction model, the silicon via has excellent heat conduction performance in the vertical direction. This feature enables the silicon via to implement corresponding protection strategies according to the temperature state. For example, the fault detection circuit module 15 uses thermistors and other components to monitor in real time whether the temperature at the silicon via connection point exceeds the preset threshold. Once the temperature of the silicon via connection point is abnormal, the fault information is sent to the silicon via status register 17 through the second routing module 16. In this way, the thermal management module 12 then reads the data of the silicon via status register 17 and modifies the routing of the input signal according to the fault condition of the silicon via to select the silicon via with a lower temperature for signal transmission.

[0056] Second, it can implement advanced fault tolerance mechanisms, because Figure 2 In the TSV array shown, the ratio of the number of working TSVs to the number of redundant TSVs is 12:6, that is, the fault tolerance ratio is 12:6, which fully considers using as few redundant TSVs as possible to reduce data waste while meeting the requirements of three-dimensional integrated circuit testing.

[0057] Third, it can save costs and improve the reuse effect. Since each silicon via can be used as both a conductive via and a thermal via, the fault-tolerant circuit is cleverly combined with the thermal via to achieve resource reuse, which not only saves costs but also further improves resource utilization efficiency. Furthermore, by controlling the connection between the silicon via and the heat sink through a thermistor circuit, the yield of the three-dimensional integrated circuit can be significantly improved without adding additional costs, and the cluster failure cost caused by thermal stress and other failures can be reduced.

[0058] Fourth, it can achieve the expansion of the thermal horizontal area and vertical area. Since the route lengths from each working TSV to any connected redundant TSV in the TSV array 14 are the same, an innovative signal counting method can be used. When the number of signals reaches a certain threshold, the thermal effect generated by the number of communications is used to bypass the signals in a group of the TSV array 14 to unused idle redundant TSVs in turn. This method not only expands the thermal horizontal area and vertical area, but also achieves efficient heat transfer and heat dissipation by utilizing a thermally symmetrical equilateral triangle heat transfer and heat dissipation model.

[0059] use Figure 2 The triangular through silicon via array shown in Figure 3 The temperature comparison of the rectangular grid through silicon via array shown is shown in the following table.

[0060]

[0061] From the above table, we can see that using Figure 2 The triangular layout of the TSV array shown is compared to Figure 3 The through silicon via array with a rectangular grid layout and the through silicon via array with a triangular layout have better heat dissipation performance.

[0062] The structure and implementation function of the second routing module 16 are substantially the same as those of the first routing module 13, and in the through silicon via array, the second routing module 16 may also be configured as follows: Figure 2 or Figure 3 The connection method is not described in detail.

[0063] Since through silicon vias are subject to manufacturing defects and reliability challenges during the service life of 3D integrated circuits, due to the manufacturing process, through silicon vias will have a variety of defects, among which the three most common defects are voids, pinholes and truncation. Figure 4 The three-dimensional integrated circuit has a through silicon via 25 formed in a non-conductive substrate 24, the through silicon via 25 is filled with metal, an insulating layer 26 is formed on the periphery of the through silicon via 25, and a filled metal object 23 is arranged above the through silicon via 25. If a pinhole occurs in the through silicon via 25, such as Figure 4 As shown, the pinhole 28 is usually formed on the insulating layer 26 and radially penetrates the insulating layer 26. If a micro-hole 27 is formed in the through silicon via 25, the through silicon via 25 will form a void failure. Usually, the micro-hole 27 is not formed on the insulating layer 26, but is formed in the through silicon via 25. If a truncation 29 is formed in the through silicon via 25, since there is no metal filled in the truncation 29, the through silicon via 25 cannot transmit signals.

[0064] If a hole or truncation occurs in the TSV 25, an open circuit fault will occur in the TSV 25. If a pinhole occurs in the TSV 25, a short circuit fault to the substrate will occur in the TSV 25, also known as a leakage fault. Since the equivalent circuit model of the TSV 25 is different under different fault types, it is necessary to identify the fault type of the TSV 25 through the fault detection circuit module 15 and establish the equivalent circuit of the TSV 25 according to the fault type.

[0065] like Figure 5 As shown, if the silicon through via 25 has no fault, its equivalent circuit includes serial resistors R12 and R13, and the resistors R12 and R13 are grounded through the capacitor C11. In addition, the resistor R12 is also connected to the resistor R11, and the resistor R13 is grounded through the capacitor C12, wherein the resistor R11 drives the resistor of the gate pull-up network, and the capacitor C12 is the parasitic capacitance of the circuit. The circuit in the dotted box is the equivalent circuit of the silicon through via 25. If the silicon through via 25 has an open circuit fault, its equivalent circuit is as follows Figure 6 As shown in FIG. 1 , compared with the case where the TSV 25 has no fault, the equivalent circuit of the TSV when it has an open circuit fault is equivalent to adding an open circuit resistor, for example, adding a resistor R23 between the resistor R22 and the resistor R24, and the resistors R22 and R23 are grounded through a capacitor C21, and the resistors R23 and R24 are grounded through a capacitor C22. In addition, the resistor R22 is connected to the resistor R21, and the resistor R24 ​​is grounded through the capacitor C23. If the TSV 25 has a leakage fault, its equivalent circuit is as follows: Figure 7 As shown, the equivalent circuit of the silicon through via 25 includes resistors R32, R33 and R34, wherein the first end of the resistor R34 is connected between the resistor R32 and the resistor R33, and the other end is grounded. In addition, capacitors C31 and C32 are connected between the resistors R32 and R33. The resistor R32 is also connected to the resistor R31, and the resistor R33 is also connected to the capacitor C33.

[0066] The fault detection circuit module 15 needs to calculate the short circuit characteristic parameters of the through silicon via AC test and the DC test, wherein the short circuit characteristic parameters of the AC test correspond to the leakage fault and the DC test short circuit characteristic parameters correspond to the open circuit fault.

[0067] When calculating the short-circuit characteristic parameters of the short-circuit AC test, first, an AC signal is generated, the AC signal is input to the silicon through via to be tested, and then the time point T1 when the input AC signal reaches the first routing module 13 and is forwarded to the silicon through via to be tested is recorded. Next, when the AC signal reaches the fault detection circuit module 15 through the silicon through via to be tested, when the signal output by the silicon through via reaches a preset level, the time point T2 at this time is recorded. Then, the time T from the start of the application of the test signal to the output signal reaching a predetermined level is calculated. Specifically, T=T2-T1, and this time T is also the delay time of the RC circuit.

[0068] When calculating the short-circuit characteristic parameters of the DC test, a DC power supply signal is first generated, and the DC power supply signal is forwarded to the silicon through via to be tested through the first routing module 13. The signal can reach the fault detection circuit module 15 through the silicon through via. If there is an open circuit fault in the silicon through via, the DC power supply signal cannot reach the preset level due to the increase in resistance. Therefore, it is determined whether the silicon through via has an open circuit fault by judging whether the signal reaching the fault detection circuit module 15 can reach the preset level. In addition, the size of the truncation in the silicon through via can also be estimated based on the size of the signal reaching the fault detection circuit module 15.

[0069] The fault detection circuit module 15 can also select the optimal signal transmission path according to the fault conditions of each silicon via. Since the path lengths of the first routing module 13 and the second routing module 16 to each redundant silicon via are the same. By pre-selecting a specific silicon via, the input and output relationship of the signal can be predetermined, and thus it can be calculated which silicon via is the optimal silicon via in a certain communication, thereby determining which silicon vias are the optimal path for the signal radially. In addition, an alternative path can also be calculated. Once there is an abnormality in a silicon via on the optimal path, the alternative path can be used to transmit the signal.

[0070] The signal output module 18 receives the signal from the second routing module 16 and outputs the signal to the outside. It can be implemented by using an existing signal transmission module, and it only needs to be able to achieve signal output.

[0071] Embodiment of a through silicon via fault-tolerant repair method for a three-dimensional integrated circuit:

[0072] The above-mentioned TSV fault-tolerant repair circuit can be used to test and repair TSVs. In order to improve the efficiency of chip design, manufacturing, and fault-tolerant repair, the present invention also improves the design for testability (DFT) device by designing a DFT common component to connect and match the above-mentioned TSV fault-tolerant repair circuit. In this embodiment, the DFT common component has a layout function interface, a wiring function interface, and a simulation design optimization function interface. Figure 8This paper introduces the process of implementing TSV fault-tolerant repair method through DFT common components.

[0073] First, the layout function interface is used to receive external signals and execute step S11 to layout the circuit composed of the first routing module, the second routing module, the electric thermal management module, and the fault detection circuit module. When the above circuit modules are laid out, the fault tolerance ratio input by the user is obtained according to the actual demand of the silicon vias input by the user and the actual demand after the silicon vias are bound. The fault tolerance ratio is a suitable fault tolerance ratio selected by the user according to the actual situation, and the area of ​​the fault-tolerant circuit is calculated and the position of the fault-tolerant circuit is determined. Therefore, during the layout, the above circuits are integrated according to the quasi-standard components, so as to flexibly arrange the positions of the various modules in the fault-tolerant repair circuit so that each module can effectively cover the entire chip area and reduce the resource share of the redundant fault-tolerant circuit.

[0074] After the first routing module, the second routing module, the electric heat management module, and the fault detection circuit module are laid out, step S12 is executed to arrange the through silicon vias through the wiring function interface, so as to optimize the layout of each through silicon via in the through silicon via array during design. For example, the redundancy ratio of the through silicon vias is automatically added and input through the wiring function interface, so as to optimize the layout of the through silicon vias. Then, step S13 is executed to automatically add the wiring of redundant through silicon vias and redundant circuits, optimize the heat dissipation structure of the three-dimensional integrated circuit, and design the temperature monitoring point. Finally, the circuit wiring operation of the first routing module, the second routing module, the electric heat management module, and the fault detection circuit module is automatically performed.

[0075] After the circuit wiring operation is completed, execute step S14, import the electrothermal model according to the design file through the simulation design optimization function interface, and simulate the fault-tolerant repair circuit of the silicon via, including the simulation of signal integrity and power integrity. Finally, execute step S15 to optimize the connection of the redundant circuit and adjust the fault tolerance ratio of the silicon via that needs fault tolerance according to the hot spot distribution of the simulation results, so as to give the chip the actual simulation results. According to the simulation results, different signal characteristics are identified, and areas such as excessive current density are identified, so as to improve the signal transmission capability and thermal optimization design, optimize the fault tolerance ratio of the fault-tolerant circuit, and improve the fault-tolerant repair capability of the fault-tolerant circuit.

[0076] The above interface of DFT public component can be realized based on C++ open dynamic link library, using operating system hook technology and operating system window message transmission working principle, floating running on the top of the desktop, mainly by modifying the input and output data of each process. This component can well solve the testability problem of each process in chip design, testing and manufacturing, and can also flexibly add various collected fault-tolerant circuits by module. Since the fault-tolerant circuit is encapsulated and implemented in modular hardware description language and actual digital circuit, it can be well expanded.

[0077] The through silicon via fault-tolerant repair circuit of the present invention is provided with a unified signal input module and a signal output module, forming a unified signal input and output interface externally. Through the signal input module and the signal output module, an external device, such as a DFT common component, can call each module in the through silicon via fault-tolerant repair circuit through the signal input module and the signal output module, and realize the test of the three-dimensional integrated circuit, which greatly improves the flexibility and reliability of the design and test of the three-dimensional integrated circuit.

[0078] The present invention considers the array TSV structure in the DFT redundant circuit design process to form a built-in test circuit, which not only simplifies the test process of the three-dimensional integrated circuit, but also improves the test efficiency. By considering the testability requirements of TSVs in the early design stage, it is possible to plan and modify the DFT redundant circuit with TSVs in the layout and wiring stages, thereby ensuring high quality and low cost of the chip during the manufacturing and testing process.

[0079] The TSV fault-tolerant repair circuit can be used as a circuit component in the layout and routing tools of 3D integrated circuits, allowing designers to easily consider and evaluate the DFT requirements of TSVs and the priority of externally compatible interconnect interfaces during the chip design phase. This component-based design approach not only improves the design efficiency of 3D integrated circuits, but also reduces design complexity. It also realizes the modularization of DFT circuits during layout and routing, forms automatic module routing of DFT redundant circuits, saves routing time, and can dynamically evaluate the relationship between routing resources and DFT redundant circuits.

[0080] Since TSV is a through-hole structure design that reuses electricity and heat, it can improve the reliability and testability of three-dimensional integrated circuits. When designing DFT redundant circuits, both the problem of electrical thermal management and the design of TSV that reuses electricity and heat are considered. The heat dissipation problem of three-dimensional integrated circuits can be solved by using an equilateral triangle TSV array layout.

[0081] Finally, the present invention can significantly improve the test efficiency and accuracy of three-dimensional integrated circuits by considering the DFT requirements and redundant circuit design of through silicon vias during the design stage of three-dimensional integrated circuits. At the same time, since the array through silicon via structure has been considered in the DFT redundant circuit design process to form a built-in test circuit, no additional test equipment or additional test steps are required during the actual test process, thereby reducing the test cost of the three-dimensional integrated circuit and reducing the test time.

[0082] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit, characterized in that: include: A signal input module, an electric heat management module, a first routing module, a through silicon via array, a fault detection circuit module, a second routing module, a through silicon via status register, and a signal output module; The signal input module is used to receive signals sent from the outside and output signals to the first routing module; The electric heat management module is used to determine the fault status of each through silicon via according to the data recorded in the through silicon via status register, and to connect the through silicon via with fault or too high temperature to perform multiplexing management of thermal through vias and electrical through vias; The through silicon via array is provided with a plurality of working through silicon vias and a plurality of redundant through silicon vias; The first routing module outputs a signal to the through silicon via array according to the signals output by the signal input module and the electric heat management module, so as to switch the through silicon via used for signal transmission; The fault detection circuit module is used to perform fault detection on the through silicon via, and send the detection result to the through silicon via status register and the signal output module through the second routing module; The through silicon via status register is used to store the fault status data of each through silicon via; The signal output module is used to output signals externally; Among them, in the silicon via array, the number of the working silicon vias is twice the number of the redundant silicon vias, and two adjacent working silicon vias and one redundant silicon via are arranged in a triangular position relationship, two adjacent working silicon vias and one redundant silicon via are respectively located at the vertices of an equilateral triangle, and each of the redundant silicon vias is connected to the first routing module and receives the signal sent by the first routing module.

2. The through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit according to claim 1, characterized in that: The first routing module includes a multiplexer and a demultiplexer. The multiplexer is used to select a signal line connected to a target through silicon via according to a received signal. The demultiplexer is used to send the signal of the target through silicon via to multiple receiving ends.

3. The through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit according to claim 1 or 2, characterized in that: The fault detection circuit module performs a fault test on the through silicon via, including calculating a short circuit characteristic parameter of an AC test and a short circuit characteristic parameter of a DC test of the through silicon via.

4. The through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit according to claim 1 or 2, characterized in that: The through silicon via status register has two register status units, and the fault type of the through silicon via is determined using data recorded in the two register status units.

5. A three-dimensional integrated circuit, characterized in that: The three-dimensional integrated circuit is integrated with a through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit as claimed in any one of claims 1 to 4.

6. A through silicon via fault-tolerant repair method for a three-dimensional integrated circuit, applied to a through silicon via fault-tolerant repair circuit for a three-dimensional integrated circuit as claimed in any one of claims 1 to 4, characterized in that: The method includes: Performing layout based on the electric thermal management module, the first routing module, the second routing module, and the fault detection circuit module, determining the fault tolerance ratio of the through silicon via fault tolerance repair circuit according to the acquired data, and calculating the area and position of the through silicon via fault tolerance repair circuit; According to the arrangement of each TSV, the layout of each TSV of the TSV array is optimized, input redundancy ratio, redundant TSV and redundant circuit wiring are added, and circuit wiring of the first routing module, the second routing module, the electric thermal management module and the fault detection circuit module is performed; The electrothermal model is imported and the TSV fault-tolerant repair circuit is simulated. The connection of the redundant circuit is optimized and the fault-tolerant ratio is adjusted according to the hot spot distribution of the simulation results.

7. The method for fault-tolerant repair of through silicon vias of a three-dimensional integrated circuit according to claim 6, characterized in that: After adding input redundancy ratio, redundant through-silicon vias and redundant circuit wiring, the heat dissipation structure of the three-dimensional integrated circuit is also optimized and temperature monitoring points are designed.

Images