Semiconductor design PVT difference elimination circuit, method and integrated circuit

Abstract

The present invention discloses a semiconductor design PVT difference elimination circuit, method and integrated circuit, which relates to the technical field of integrated circuits, including a signal amplification module, a trip point tracking circuit, a cycle detection control unit and a unit under test, wherein the signal amplification module filters and amplifies the electrical signal inputted from its input end, and enhances the amplitude of the input electrical signal; the trip point tracking circuit acts as an electrical isolation element to provide a stable electrical signal for the next level circuit, and an input end of the trip point tracking circuit is electrically connected to a connection end of the cycle detection control unit; the cycle detection control unit outputs a periodic clock frequency signal. The present invention can effectively eliminate the adverse effects of the jump voltage on the calculation results of the capacitor cycle, so that the test results of the capacitor cycle can be independent of the influence of the PVT difference, and the accuracy of the charge and discharge cycle test of the measured capacitor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor design PVT difference elimination circuit, method and integrated circuit. Background Art

[0002] There are many kinds of semiconductor devices and components. Among them, oscillators, as one of the semiconductor components, exist in many electronic devices, such as radio receivers, televisions, radio and television broadcast transmitters, computers, computer peripherals, mobile phones, radars and other equipment. An oscillator is an electronic component that can generate repetitive electronic signals (usually sine waves or square waves). According to the different oscillation excitation methods, oscillators can be divided into self-excited oscillators and driven oscillators; according to the different circuit structures, they can be divided into RC oscillators, LC oscillators, crystal oscillators, fork oscillators, etc.; according to the different output waveforms, they can be divided into sine wave, square wave, sawtooth wave and other oscillators.

[0003] In the RC oscillator circuit, the filter is a network of resistors and capacitors. The RC oscillator is mainly used to generate lower frequencies. Common RC oscillator circuits include phase-shift oscillators and Wien bridge oscillators. In the LC oscillator circuit, the filter is a tuned circuit consisting of an inductor (L) and a capacitor (C) connected together and used as a resonator. Whether it is a resistor-capacitor oscillator or an LC oscillator, the charging and discharging speed of the capacitor element that generates the clock signal in the oscillator needs to be tested to ensure that the oscillator has a reliable clock frequency during use. During the test, the capacitor element needs to be tested with as independent PVT (Production Verification Test, PVT) as possible to eliminate the impact of process, voltage or temperature on the component performance.

[0004] Existing PVT test circuits often use a ring oscillator and a bidirectional transmission gate to jointly test the charging and discharging speed of a capacitor. The ring oscillator is composed of an odd number of gate circuits, and usually multiple inverters connected in series obtain a delay signal. The trip point of the first inverter in the existing test circuit determines the interval time of the cycle.

[0005] Since the existing test circuit does not eliminate the jump voltage at the input end of the first inverter, the jump voltage affects the period calculation result of the capacitor, making it difficult to separate the test result of the capacitor period from the influence of PVT differences, resulting in a large difference between the theoretical value of the oscillator period test and its actual value, which is not conducive to objectively analyzing the clock frequency value of the capacitor element in the oscillator, and is not conducive to obtaining accurate charging and discharging speed results of the tested component. Summary of the invention

[0006] The purpose of the present invention is to eliminate the jump voltage at the input end of the first inverter by using a trip point tracking circuit. By eliminating the adverse effect of the jump voltage on the capacitor cycle calculation result, the test result of the capacitor cycle can be independent of the influence of PVT differences, reducing the influence of PVT differences on the capacitor cycle test results, so as to solve the problems raised in the above-mentioned background technology.

[0007] In a first aspect, to achieve the above-mentioned purpose, the present invention provides a semiconductor design PVT difference elimination circuit, comprising a signal amplification module, a trip point tracking circuit, a cycle detection control unit and a unit under test, wherein the signal amplification module filters and amplifies the electrical signal inputted from its input end, and can reduce noise interference and enhance the amplitude of the input electrical signal by amplifying the weak electrical signal, so as to make the communication clearer and smoother, and ensure the effective reception of the input signal by the next-level circuit;

[0008] The trip point tracking circuit serves as an electrical isolation element to provide a stable electrical signal for the next level circuit. An input end of the trip point tracking circuit is electrically connected to a connection end of the period detection control unit. A pull-up resistor R is connected between an input end of the trip point tracking circuit and an output end of the signal amplification module. By connecting the pull-up resistor R, it is possible to ensure that an input signal of the trip point tracking circuit is always at a certain level, thereby ensuring the stable operation of the circuit. By setting the pull-up resistor R, electromagnetic interference can be effectively reduced by reducing the rapid change of the signal line; the period detection control unit outputs a periodic clock frequency signal; one end of the unit under test is electrically connected to the output end of the period detection control unit, and the unit under test receives the periodic electrical signal emitted by the period detection control unit.

[0009] As a further solution of the present invention: the signal amplification module includes an operational amplifier, a feedback unit and an input unit; the operational amplifier is a common-phase operational amplifier , by connecting a non-inverting operational amplifier The non-inverting operational amplifier keeps its output in phase with the input to facilitate phase adjustment. A feedback unit is connected between the inverting connection end and the output end, and an input unit is connected between the feedback unit and the ground end; the feedback unit is a feedback resistor , the input unit is an external resistor ; The circuit closed-loop gain of the signal amplification module , where A is the closed-loop gain; is the feedback resistor; is an external resistor.

[0010] As a further solution of the present invention: the trip point tracking circuit includes a proportional amplifier , proportional amplifier The output end is connected to the N-channel field effect transistor Gate, N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The drain of the proportional amplifier The inverting terminal is electrically connected to the proportional amplifier , which can realize the synthesis, comparison, correction and amplification of electrical signals to eliminate noise and distortion and improve the transmission quality of signals. The drain of is connected to one end of the resistor R to form a Y connection point.

[0011] As a further solution of the present invention: the in-phase operational amplifier The non-inverting input terminal is connected to a P-channel field effect transistor and an N-channel FET , Field Effect Transistor The source is connected to a high level , Field Effect Transistor The drain of the N-channel FET The drain connection of the N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The gate and P-channel field effect transistor The gate of the P-channel field effect transistor is connected in series. and N-channel FET When a high level is input at the gate connection point D, the P-channel field effect transistor The source and drain are cut off, and the N-channel field effect transistor The source and drain of the P-channel FET are turned on; when a low level is input at point D, The source and drain of the N-channel field effect transistor are turned on. The source and drain of the circuit are cut off, so that the trip point tracking circuit can receive input signals when the input level is high or low, and can maintain the response speed of the jump voltage at the input point of the cycle detection control unit;

[0012] The N-channel field effect transistor The gate and P-channel field effect transistor The gate is connected to an input end of the trip point tracking circuit, which can ensure effective feedback of the input end jump voltage of the period detection control unit.

[0013] The P-channel field effect transistor and N-channel FET Control the shutdown and opening of the input signal of the next level circuit, P channel field effect transistor and N-channel FET It is a complementary output stage circuit. It can improve the circuit's load capacity and switching speed by alternately turning on two field effect tubes, so that when the circuit outputs high and low levels, the circuit's on and off states can be quickly switched, reducing power consumption and improving the tolerance of each tube. and N-channel FET Connect to the non-inverting operational amplifier The input end can ensure that no matter which tube is turned on, its on resistance is very small, which helps to reduce the RC constant, speed up the current change, reduce power consumption and improve efficiency. At the same time, for the linear driver circuit, the P-channel field effect tube and N-channel FET It can ensure that the complementary output stage works in a linear state, reduce crossover distortion, and optimize the performance of the circuit by controlling the quiescent current; and when the load circuit is a differential circuit, the P-channel field effect transistor and N-channel FET It can well support this circuit structure, improve the performance and stability of the circuit, and is conducive to maintaining the circuit's high load capacity, fast switching, low power consumption and high efficiency circuit performance;

[0014] As a further solution of the present invention: the period detection control unit is any one of a primary ring oscillator, a secondary ring oscillator or a plurality of ring oscillators. When the period detection control unit is a secondary ring oscillator or a plurality of ring oscillators, since a larger number of inverters or amplifiers are cascaded in the period detection control unit, the output frequency can be significantly improved.

[0015] As a further solution of the present invention: the cycle detection control unit includes a first-level ring oscillator and a transmission delay unit, the first-level ring oscillator is connected in series with the transmission delay unit, the transmission delay unit is an RC delay circuit, the first-level ring oscillator is connected in series with the transmission delay unit, the ring oscillator can generate a clock signal, and by connecting the transmission delay unit, the cycle detection control unit can obtain a larger transmission delay, which is convenient for adjusting the whole single frequency. By adding the RC delay circuit, the transmission delay time of the inverter is delayed through the RC charging and discharging process, thereby enhancing the speed of the cycle jump.

[0016] As a further solution of the present invention: the cycle detection control unit includes a first inverter , the second inverter , the third inverter and the fourth inverter and an equivalent circuit of the fifth inverter, wherein the equivalent circuit of the fifth inverter is a P-channel field effect transistor The equivalent circuit of the fifth inverter is a P-channel field effect transistor ; The first inverter The input end of the first inverter is electrically connected to the output end of the trip point tracking circuit and the input end of the unit under test. The output terminal of the second inverter is electrically connected to The input terminal of the second inverter The output terminal of the third inverter is electrically connected to The input terminal of the third inverter The output end of the fourth inverter is electrically connected to The input terminal of the fourth inverter The output end is electrically connected to the P-channel field effect transistor The gate of the P-channel FET The source of the P-channel FET is connected to the high level input. The drain of the first inverter is connected The input terminal.

[0017] As a further solution of the present invention: the transmission delay unit is an RC oscillator delay circuit, and the RC oscillator delay circuit includes a capacitor ,capacitance One end of the first inverter is electrically connected to The output terminal of the capacitor The other end of the second inverter is electrically connected to The output terminal of the second inverter The output terminal and the capacitor A resistor is connected between , the capacitor One end of the protection resistor is connected , the protection resistor The other end is electrically connected to the third inverter Input terminal, protection resistor It can prevent the third inverter connected behind it from damage.

[0018] As a further solution of the present invention: the cycle detection control unit also includes an N-channel field effect transistor , the N-channel FET The gate of the N-channel FET is connected to the output terminal of the trip point tracking circuit. The source of the N-channel FET is grounded. The drain of the first inverter The input terminal is connected to the N-channel field effect transistor The gate input level is greater than its turn-on voltage, which can turn on its drain-source, thus The positive plate of capacitor C is charged. When the voltage of the positive plate of capacitor C rises to saturation, capacitor C is discharged to the ground, completing a charge and discharge process.

[0019] As a further solution of the present invention: one connection end of the measured unit is grounded, the measured unit is a capacitor C, and the capacitor C is any one of a fixed capacitor, a variable capacitor or a fine-tuning capacitor.

[0020] In a second aspect, the present invention discloses a method for eliminating PVT differences in semiconductor design, including the semiconductor design PVT difference elimination circuit described in the first aspect, the method comprising:

[0021] Connect a voltmeter in parallel to the non-inverting input of the operational amplifier to measure the input voltage. , and the voltage As an input electrical signal to the trip point tracking circuit;

[0022] Make the feedback signal of the trip point tracking circuit a voltage , so that the feedback voltage = ;

[0023] Use a certain method to get the current flowing through the resistor R ;

[0024] Differentiate the time period of the unit under test to obtain ;

[0025] calculate ;

[0026] , complete the PVT independent test of the time period, and obtain the differential period by differentiating the time period of the unit under test using the differential idea. At the same time, on the basis of the differential voltage, the differential voltage is accurately calculated. By bringing it into the RC time constant calculation formula, the input point jump voltage of the control unit can be detected by tracking the period, eliminating the detection difference of the jump voltage on the RC circuit constant value, which greatly improves the accuracy of the test results of the unit under test.

[0027] As a further solution of the present invention: obtaining the current flowing through the resistor R The method is either calculation or measurement, or a combination of the two methods;

[0028] The calculation method is , is the output voltage of the signal amplification module;

[0029] The measurement method is to connect an ammeter in series on the branch where the resistor R is located.

[0030] In a third aspect, the present invention discloses an integrated circuit, comprising the semiconductor design PVT difference elimination circuit described in the first aspect.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. The present invention eliminates the jump voltage at the input end of the first inverter by adopting a trip point tracking circuit, which can effectively eliminate the adverse effect of the jump voltage on the capacitor cycle calculation result, so that the test result of the capacitor cycle can be independent of the influence of PVT differences, effectively reducing the difference amplitude between the theoretical value and the actual value of the oscillator cycle test, which is conducive to objectively analyzing the clock frequency value of the capacitor element in the oscillator, and at the same time is conducive to obtaining accurate charging and discharging speed results of the measured element, greatly improving the accuracy of the charging and discharging cycle test of the measured capacitor.

[0033] 2. The present invention adopts a P-channel field effect transistor and N-channel FET Controlling the input signal of the next stage circuit helps to reduce the RC constant, speed up the current change, reduce power consumption and improve efficiency. At the same time, for the linear driver circuit, the P-channel field effect transistor and N-channel FET By ensuring that the complementary output stages work in a linear state, crossover distortion can be reduced, which is beneficial to maintaining the circuit's high load capacity, fast switching, low power consumption and high efficiency circuit performance.

[0034] 3. The present invention adopts a differential idea to differentiate the time period of the unit under test to obtain the differential period, and at the same time, based on the differential voltage, realizes accurate calculation of the differential voltage. By bringing it into the RC time constant calculation formula, it can detect the input point jump voltage of the control unit by tracking the period, eliminate the detection difference of the jump voltage on the RC circuit constant value, and greatly improve the accuracy of the calculation result of the unit under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a module circuit diagram of the present invention;

[0036] Figure 2 An electrical connection diagram of a difference elimination circuit module of the present invention;

[0037] Figure 3 A difference elimination circuit diagram of the present invention;

[0038] Figure 4 FIG. 4 is a circuit diagram for eliminating the difference in transmission delay according to the present invention.

[0039] In the figure: 1. signal amplification module; 101. operational amplifier; 102. feedback unit; 103. input unit; 2. unit under test; 3. trip point tracking circuit; 4. cycle detection control unit. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0041] Embodiment 1:

[0042] like Figure 1 The module circuit diagram of the present invention is shown, which provides a semiconductor design PVT difference elimination circuit, including a signal amplification module 1, a trip point tracking circuit 3, a cycle detection control unit 4 and a unit under test 2. The signal amplification module 1 filters and amplifies the electrical signal input to its input end, and can reduce noise interference and enhance the amplitude of the input electrical signal by amplifying weak electrical signals, making communication clearer and smoother, and ensuring that the next-level circuit can effectively receive the input signal.

[0043] like Figure 2 The figure shows the electrical connection diagram of the difference elimination circuit module of the present invention. The input end of the trip point tracking circuit 3 is coupled to the P-channel field effect transistor and N-channel FET The gates of the two can ensure that no matter which tube is turned on, its on resistance is very small, which helps to reduce the RC constant, speed up the current change, reduce power consumption and improve efficiency. At the same time, for the linear driver circuit, the P-channel field effect tube and N-channel FET It can ensure that the complementary output stage works in a linear state, reduce crossover distortion, and optimize the performance of the circuit by controlling the quiescent current; and when the load circuit is a differential circuit, the complementary output stage circuit can well support this circuit structure, improve the performance and stability of the circuit, and help maintain the circuit's high load capacity, fast switching, low power consumption and high efficiency; the trip point tracking circuit 3 acts as an electrical isolation element to provide a stable electrical signal for the next stage circuit, and the in-phase operational amplifier The non-inverting input terminal of the P-channel field effect transistor and N-channel FET A pull-up resistor R is connected between an input end of the trip point tracking circuit 3 and an output end of the signal amplifying module 1. By connecting the pull-up resistor R, it is possible to ensure that the P-channel field effect transistor and N-channel FET An input signal is always at a certain level, thereby ensuring the stable operation of the circuit. By setting the pull-up resistor R, the electromagnetic interference can be effectively reduced by reducing the rapid change of the signal line; the period detection control unit 4 outputs a periodic clock frequency signal; one end of the unit under test 2 is electrically connected to the output end of the period detection control unit 4, and the unit under test 2 receives the periodic electrical signal sent by the period detection control unit 4.

[0044] Preferably, the signal amplification module 1 comprises an operational amplifier 101, a feedback unit 102 and an input unit 103; the operational amplifier 101 is a common-phase operational amplifier. , by connecting a non-inverting operational amplifier And keep its output in phase with the input, which is convenient for phase adjustment. The feedback unit 102 is connected between the inverting connection end and the output end, and the input unit 103 is connected between the feedback unit 102 and the ground end; the feedback unit 102 is a feedback resistor , input unit 103 is an external resistor ; Circuit closed-loop gain of signal amplifier module 1 , where A is the closed-loop gain; is the feedback resistor; is an external resistor.

[0045] Preferably, a non-inverting operational amplifier The non-inverting input terminal is connected to a P-channel field effect transistor and an N-channel FET , Field Effect Transistor The source is connected to a high level , Field Effect Transistor The drain of the N-channel field effect transistor The drain connection of the N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The gate and P-channel field effect transistor The gate of the P-channel field effect transistor is connected in series. and N-channel FET When a high level is input at the gate connection point D, the P-channel field effect transistor The source and drain are cut off, and the N-channel field effect transistor The source and drain of the P-channel FET are turned on; when a low level is input at point D, The source and drain of the N-channel field effect transistor are turned on. The source and drain of the N-channel field effect transistor are cut off, so that the trip point tracking circuit 3 can receive the input signal when the high level or low level input is used, and can maintain the reflection speed of the jump voltage at the input point of the cycle detection control unit 4; The gate and P-channel field effect transistor The gate is connected to an input end of the trip point tracking circuit 3, which can ensure effective feedback of the input jump voltage of the period detection control unit 4.

[0046] like Figure 3 The circuit diagram of the difference elimination circuit of the present invention is shown. The trip point tracking circuit 3 includes an equal-proportional amplifier. , proportional amplifier The output end is connected to the N-channel field effect transistor Gate, N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The drain of the proportional amplifier The inverting terminal is electrically connected to the proportional amplifier , which can integrate, compare, correct and amplify electrical signals to eliminate noise and distortion and improve signal transmission quality.

[0047] Combination Figure 3 The period detection control unit 4 is a first-stage ring oscillator, and the period detection control unit 4 includes a first inverter , the second inverter , the third inverter , the fourth inverter and the equivalent circuit of the fifth inverter, the equivalent circuit of the fifth inverter is a P-channel field effect transistor ; First inverter The input end of the first inverter is electrically connected to the output end of the trip point tracking circuit 3 and the input end of the unit under test 2. The output terminal of the second inverter is electrically connected to The input of the second inverter The output terminal of the third inverter is electrically connected to The input terminal of the third inverter The output terminal of the fourth inverter is electrically connected to The input terminal of the fourth inverter The output end is electrically connected to the P-channel field effect transistor Gate, P-channel field effect transistor The source of the P-channel field effect transistor is connected to the high level input. The drain of the first inverter is connected The input terminal of the first inverter When the input level is 0, the first inverter The output terminal outputs level 1, which serves as the second inverter. The input signal at the input terminal, the second inverter The output terminal outputs level 0, which serves as the third inverter. The input signal of the third inverter The output terminal outputs level 1, which serves as the fourth inverter. The input signal of the fourth inverter The output terminal outputs 0 to the equivalent circuit of the fifth inverter P channel field effect transistor The gate of the P-channel field effect transistor receives a level signal of 0, which makes the The positive plate of capacitor C is turned on and powered, so that capacitor C enters a charging state.

[0048] Preferably, the period detection control unit 4 also includes an N-channel field effect transistor , N-channel field effect transistor The gate of the N-channel field effect transistor is connected to the output terminal of the trip point tracking circuit 3. The source of the N-channel field effect transistor is grounded. The drain of the first inverter The input terminal is connected to the N-channel field effect transistor The gate input level is greater than its turn-on voltage, which can turn on its drain-source, thus The positive plate of capacitor C is charged. When the voltage of the positive plate of capacitor C rises to saturation, capacitor C is discharged to the ground, completing a charge and discharge process.

[0049] Preferably, one connection terminal of the unit under test 2 is grounded, and the unit under test 2 is a variable capacitor.

[0050] Embodiment 2:

[0051] like Figure 1 The module circuit diagram of the present invention is shown, which provides a semiconductor design PVT difference elimination circuit, including a signal amplification module 1, a trip point tracking circuit 3, a cycle detection control unit 4 and a unit under test 2. The signal amplification module 1 filters and amplifies the electrical signal input to its input end, and can reduce noise interference and enhance the amplitude of the input electrical signal by amplifying weak electrical signals, making communication clearer and smoother, and ensuring that the next-level circuit can effectively receive the input signal.

[0052] like Figure 2 The figure shows the electrical connection diagram of the difference elimination circuit module of the present invention. The input end of the trip point tracking circuit 3 is coupled to the P-channel field effect transistor and N-channel FET The gates of the two can ensure that no matter which tube is turned on, its on resistance is very small, which helps to reduce the RC constant, speed up the current change, reduce power consumption and improve efficiency. At the same time, for the linear driver circuit, the P-channel field effect tube and N-channel FET It can ensure that the complementary output stage works in a linear state, reduce crossover distortion, and optimize the performance of the circuit by controlling the quiescent current; and when the load circuit is a differential circuit, the complementary output stage circuit can well support this circuit structure, improve the performance and stability of the circuit, and help maintain the circuit's high load capacity, fast switching, low power consumption and high efficiency; the trip point tracking circuit 3 acts as an electrical isolation element to provide a stable electrical signal for the next stage circuit, and the in-phase operational amplifier The non-inverting input terminal of the P-channel field effect transistor and N-channel FET A pull-up resistor R is connected between an input end of the trip point tracking circuit 3 and an output end of the signal amplifying module 1. By connecting the pull-up resistor R, it is possible to ensure that the P-channel field effect transistor and N-channel FET An input signal is always at a certain level, thereby ensuring the stable operation of the circuit. By setting the pull-up resistor R, the electromagnetic interference can be effectively reduced by reducing the rapid change of the signal line; the period detection control unit 4 outputs a periodic clock frequency signal; one end of the unit under test 2 is electrically connected to the output end of the period detection control unit 4, and the unit under test 2 receives the periodic electrical signal sent by the period detection control unit 4.

[0053] Preferably, the trip point tracking circuit 3 includes a proportional amplifier , proportional amplifier The output end is connected to the N-channel field effect transistor Gate, N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The drain of the proportional amplifier The inverting terminal is electrically connected to the proportional amplifier , which can integrate, compare, correct and amplify electrical signals to eliminate noise and distortion and improve signal transmission quality.

[0054] like Figure 4 The circuit diagram of the present invention with transmission delay difference elimination is shown. The signal amplification module 1 includes an operational amplifier 101, a feedback unit 102 and an input unit 103; the operational amplifier 101 is a common-phase operational amplifier. , by connecting a non-inverting operational amplifier And keep its output in phase with the input, which is convenient for phase adjustment. The feedback unit 102 is connected between the inverting connection end and the output end, and the input unit 103 is connected between the feedback unit 102 and the ground end; the feedback unit 102 is a feedback resistor , input unit 103 is an external resistor ; Circuit closed-loop gain of signal amplifier module 1 , where A is the closed-loop gain; is the feedback resistor; is an external resistor.

[0055] Combination Figure 4 , non-inverting operational amplifier The non-inverting input terminal is connected to a P-channel field effect transistor and an N-channel FET , Field Effect Transistor The source is connected to a high level , Field Effect Transistor The drain of the N-channel field effect transistor The drain connection of the N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The gate and P-channel field effect transistor The gate of the P-channel field effect transistor is connected in series. and N-channel FET When a high level is input at the gate connection point D, the P-channel field effect transistor The source and drain are cut off, and the N-channel field effect transistor The source and drain of the P-channel FET are turned on; when a low level is input at point D, The source and drain of the N-channel field effect transistor are turned on. The source and drain of the N-channel field effect transistor are cut off, so that the trip point tracking circuit 3 can receive the input signal when the high level or low level input is used, and can maintain the reflection speed of the jump voltage at the input point of the cycle detection control unit 4; The gate and P-channel field effect transistor The gate is connected to an input end of the trip point tracking circuit 3, which can ensure effective feedback of the input jump voltage of the period detection control unit 4.

[0056] Combination Figure 4The cycle detection control unit 4 includes a first-level ring oscillator and a transmission delay unit. The first-level ring oscillator and the transmission delay unit are connected in series. The transmission delay unit is an RC delay circuit. The first-level ring oscillator and the transmission delay unit are connected in series. The ring oscillator can generate a clock signal. By connecting the transmission delay unit, the cycle detection control unit 4 can obtain a larger transmission delay, which is convenient for adjusting the entire single frequency. By adding the RC delay circuit, the transmission delay time of the inverter is delayed through the RC charging and discharging process, and the speed of the cycle jump is enhanced. The cycle detection control unit 4 includes a first inverter , the second inverter , the third inverter and the fourth inverter and the equivalent circuit of the fifth inverter, the equivalent circuit of the fifth inverter is a P-channel field effect transistor ; First inverter The input end of the first inverter is electrically connected to the output end of the trip point tracking circuit 3 and the input end of the unit under test 2. The output terminal of the second inverter is electrically connected to The input of the second inverter The output terminal of the third inverter is electrically connected to The input terminal of the third inverter The output terminal of the fourth inverter is electrically connected to The input terminal of the fourth inverter The output end is electrically connected to the P-channel field effect transistor Gate, P-channel field effect transistor The source of the P-channel field effect transistor is connected to the high level input. The drain of the first inverter is connected The input terminal.

[0057] Preferably, the transmission delay unit is an RC oscillator delay circuit, and the RC oscillator delay circuit includes a capacitor ,capacitance One end of the first inverter is electrically connected to The output terminal of the capacitor The other end is electrically connected to the second inverter The output of the second inverter The output terminal and capacitor A resistor is connected between ,capacitance One end of the protection resistor is connected , protection resistor The other end is electrically connected to the third inverter Input terminal, protection resistor It can prevent the third inverter connected behind it from damage.

[0058] Preferably, the period detection control unit 4 also includes an N-channel field effect transistor , N-channel field effect transistor The gate of the N-channel field effect transistor is connected to the output terminal of the trip point tracking circuit 3. The source of the N-channel field effect transistor is grounded. The drain of the first inverter The input terminal is connected to the N-channel field effect transistor The gate input level is greater than its turn-on voltage, which can turn on its drain-source, thus The positive plate of capacitor C is charged. When the voltage of the positive plate of capacitor C rises to saturation, capacitor C is discharged to the ground, completing a charge and discharge process.

[0059] Preferably, one connection end of the measured unit 2 is grounded, the measured unit 2 is a capacitor C, and the capacitor C is any one of a fixed capacitor, a variable capacitor or a fine-tuning capacitor.

[0060] Combination Figure 3 The present invention further provides a semiconductor design PVT difference elimination method, including the semiconductor design PVT difference elimination circuit of the first aspect, the method comprising:

[0061] Connect a voltmeter in parallel to the non-inverting input of the operational amplifier to measure the input voltage. , and the voltage As an input electrical signal of the trip point tracking circuit 3;

[0062] The feedback signal of the trip point tracking circuit 3 is a voltage , so that the feedback voltage = ;

[0063] Use a certain method to get the current flowing through the resistor R ;

[0064] Differentiate the time period of unit 2 to obtain ;

[0065] calculate ;

[0066] , complete the PVT independent test of the time period, and obtain the differential period by differentiating the time period of the unit under test 2 using the differential idea. At the same time, on the basis of the differential voltage, the differential voltage is accurately calculated. By bringing it into the RC time constant calculation formula, the input point jump voltage of the control unit 4 can be detected by tracking the period, and the detection difference of the jump voltage on the RC circuit constant value can be eliminated, which greatly improves the accuracy of the calculation result of the unit under test 2.

[0067] Preferably, the current flowing through the resistor R is obtained The method is calculation method, , is the output voltage of the signal amplification module 1.

[0068] An integrated circuit is also provided, comprising the semiconductor design PVT difference elimination circuit in the above embodiment.

[0069] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0070] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A semiconductor design PVT difference elimination circuit, characterized in that: include: A signal amplification module, wherein the signal amplification module filters and amplifies the electrical signal inputted from its input end, and enhances the amplitude of the input electrical signal; A trip point tracking circuit, the trip point tracking circuit serving as an electrical isolation element to provide a stable electrical signal for a next-level circuit, a pull-up resistor R being connected between an input end of the trip point tracking circuit and an output end of the signal amplification module; A period detection control unit, the period detection control unit outputs a periodic clock frequency signal, and an input terminal of the period detection control unit is coupled to an input terminal of the trip point tracking circuit; A unit under test, one end of which is electrically connected to the output end of the period detection control unit, and the unit under test receives the periodic electrical signal sent by the period detection control unit; Wherein, the trip point tracking circuit includes a proportional amplifier , proportional amplifier The output end is connected to the N-channel field effect transistor Gate, N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The drain of the proportional amplifier The inverting connection terminal is electrically connected; The period detection control unit is any one of a primary ring oscillator, a secondary ring oscillator or a plurality of ring oscillators; when the period monitoring control unit is a primary ring oscillator, the period detection control unit includes a first inverter , the second inverter , the third inverter , the fourth inverter and the equivalent circuit of the fifth inverter, the equivalent circuit of the fifth inverter is a P-channel field effect transistor .

2. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: The signal amplification module includes an operational amplifier, a feedback unit and an input unit; The operational amplifier is a common-mode operational amplifier. , the non-inverting operational amplifier A feedback unit is connected between the inverting connection end and the output end, and an input unit is connected between the feedback unit and the ground end; The feedback unit is a feedback resistor , the input unit is an external resistor ; The circuit closed-loop gain of the signal amplification module , where A is the closed-loop gain; is the feedback resistor; is an external resistor.

3. The semiconductor design PVT difference elimination circuit according to claim 2, characterized in that: The non-inverting input of the operational amplifier is connected to a P-channel field effect transistor and an N-channel FET , Field Effect Transistor The source is connected to a high level , Field Effect Transistor The drain of the N-channel FET The drain connection of the N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The gate and P-channel field effect transistor The gates are connected in series; The N-channel field effect transistor The gate and P-channel field effect transistor The gate is connected to an input terminal of the trip point tracking circuit.

4. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: The period detection control unit includes a primary ring oscillator and a transmission delay unit, and the primary ring oscillator and the transmission delay unit are connected in series.

5. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: The first inverter The input end of the first inverter is electrically connected to the output end of the trip point tracking circuit and the input end of the unit under test. The output terminal of the second inverter is electrically connected to The input terminal of the second inverter The output terminal of the third inverter is electrically connected to The input terminal of the third inverter The output end of the fourth inverter is electrically connected to The input terminal of the fourth inverter The output end is electrically connected to the P-channel field effect transistor The gate of the P-channel FET The source of the P-channel FET is connected to the high level input. The drain of the first inverter is connected The input terminal.

6. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: The transmission delay unit is an RC oscillator delay circuit, which includes a capacitor ,capacitance One end of the first inverter is electrically connected to The output terminal of the capacitor The other end of the second inverter is electrically connected to The output terminal of the second inverter The output terminal and the capacitor A resistor is connected between , the capacitor One end of the protection resistor is connected , the protection resistor The other end is electrically connected to the third inverter The input terminal.

7. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: The period detection control unit also includes: N-channel field effect transistor , the N-channel FET The gate of the N-channel FET is connected to the output terminal of the trip point tracking circuit. The source of the N-channel FET is grounded. The drain of the first inverter The input terminal connection of 8. The semiconductor design PVT difference elimination circuit according to claim 1, characterized in that: One connection end of the unit under test is grounded, the unit under test is a capacitor C, and the capacitor C is any one of a fixed capacitor, a variable capacitor, or a fine-tuning capacitor; The negative plate of the capacitor C is grounded.

9. A method for eliminating PVT differences in semiconductor design, characterized by: The method comprises the semiconductor design PVT difference elimination circuit according to any one of claims 1 to 6, and the method comprises: Connect a voltmeter in parallel to the non-inverting input of the operational amplifier to measure the input voltage. , and the voltage As an input electrical signal to the trip point tracking circuit; Make the feedback signal of the trip point tracking circuit a voltage , so that the feedback voltage = ; Use a certain method to get the current flowing through the resistor R ; Differentiate the time period of the unit under test to obtain ; calculate ; , complete the PVT independent test of the time period.

10. The semiconductor design PVT difference elimination method according to claim 9, characterized in that: Get the current flowing through the resistor R The method is either calculation or measurement, or a combination of the two methods; The calculation method is , is the output voltage of the signal amplification module; The measurement method is to connect an ammeter in series on the branch where the resistor R is located.

11. An integrated circuit, characterized in that: The integrated circuit includes the semiconductor design PVT difference elimination circuit as described in any one of claims 1-8.

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