EAS test device and test method applied to silicon carbide MOS device

Abstract

The invention provides an EAS test device and test method applied to a silicon carbide MOS device, and the device comprises a drive circuit which comprises a gate drive module, an isolation power module, and a switch module. The test circuit comprises a silicon carbide MOS device to be tested; the gate driving module and the isolation power supply module are connected with the switch module, and the switch module is connected with a silicon carbide MOS device to be tested; the gate driving module controls the switch module to open the positive voltage provided by the isolation power supply module and is connected to the gate pole of the silicon carbide MOS device to be tested; or the gate driving module controls the switch module to turn on the negative voltage provided by the isolation power supply module, and is connected to the gate pole and the Kelvin pin of the silicon carbide MOS device to be tested. According to the invention, through the isolation power supply module, the turn-on voltage required by the silicon carbide MOS device to be tested in the EAS test can be realized at a low cost, the shutdown loss caused by the suspension of the Kelvin pin is reduced, the discharge of gate charge is accelerated, and the purpose of rapid turn-off is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection technology, and in particular to an EAS testing device and a testing method applied to a silicon carbide MOS device. Background Art

[0002] As a high-performance power semiconductor device, the existing silicon carbide MOS device has broad application prospects in many fields such as new energy vehicles, switching power modules, photovoltaic inverters, high-power OBCs, etc. At the same time, the performance test of silicon carbide MOS devices is crucial for their research and development, production and application.

[0003] At present, the performance tests of silicon carbide MOS devices are mostly conducted on double pulses, and the tests on EAS (Single Pulse Avalanche Breakdown Energy) capability are less common, and IGBT test circuits are usually used. Figure 1 As shown, the EAS test circuit of the silicon carbide MOS device based on the IGBT test circuit usually includes the following structure: a gate drive module, a silicon carbide MOS device and an inductor for storing current. After the gate drive module is started, a pulse signal is given to the gate of the silicon carbide MOS device. When the silicon carbide MOS device is turned on, the inductor is charged. When the silicon carbide MOS device is turned off, the inductor is discharged. The current flows through the silicon carbide MOS device. At this time, the maximum value of the current that the device can withstand without being damaged is the avalanche tolerance.

[0004] However, this structure was originally designed based on IGBT and MOS testing. Therefore, the gate drive module usually provides a gate voltage of 15V or 10V, which does not reach the full turn-on voltage of the SiC MOS device. In addition, the Kelvin pin of the SiC MOS device is not processed, resulting in a large deviation in the EAS test results of the SiC MOS device. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides an EAS testing device and a testing method for silicon carbide MOS devices, which solves the problem that the test circuit used in the prior art to test the EAS performance of silicon carbide MOS devices is not designed according to the characteristics of the silicon carbide MOS devices themselves, resulting in inaccurate test results.

[0006] According to an embodiment of the present invention, a first aspect provides an EAS testing device applied to a silicon carbide MOS device, comprising:

[0007] A driving circuit, the driving circuit comprising a gate driving module, an isolation power supply module, and a switch module;

[0008] A test circuit, wherein the test circuit includes a silicon carbide MOS device to be tested;

[0009] The gate driving module and the isolation power supply module are connected to the switch module, and the switch module is connected to the silicon carbide MOS device to be tested;

[0010] The gate driving module controls the switch module to turn on the positive voltage provided by the isolation power module and connects to the gate of the silicon carbide MOS device to be tested;

[0011] Alternatively, the gate driving module controls the switch module to turn on the negative voltage provided by the isolation power module and connect it to the gate and Kelvin pin of the silicon carbide MOS device to be tested.

[0012] Optionally, the test circuit further comprises an adjustable inductor and a power distribution module;

[0013] The gate driving module includes a level signal output terminal and a driving voltage input terminal; the isolated power supply module includes a power supply voltage input terminal, a positive voltage output terminal and a negative voltage output terminal; the switch module includes a level signal receiving terminal, a positive voltage receiving terminal, a negative voltage receiving terminal and a switch signal output terminal;

[0014] The driving voltage input end of the gate driving module, the power voltage input end of the isolated power module and one end of the power distribution module are connected to the bus voltage, and the other end of the power distribution module is connected to 0V voltage / ground; the level signal output end of the gate driving module is connected to the level signal receiving end of the switch module, the positive voltage receiving end of the switch module is connected to the positive voltage output end of the isolated power module, the negative voltage receiving end of the switch module is connected to the negative voltage output end of the isolated power module, the switch signal output end of the switch module is connected to the gate of the silicon carbide MOS device to be tested, the emitter of the silicon carbide MOS device to be tested is connected to 0V voltage / ground, the Kelvin pin of the silicon carbide MOS device to be tested is connected to the negative voltage output end, the collector of the silicon carbide MOS device to be tested is connected to one end of the adjustable inductor, and the other end of the adjustable inductor is connected to one end of the power distribution module.

[0015] Optionally, the gate driving module includes a gate driving chip, a first resistor, a second resistor and a first capacitor;

[0016] The second pin and the third pin of the gate drive chip are the level signal output terminals; the VCC pin of the gate drive chip is the drive voltage input terminal; the fifth pin and the sixth pin of the gate drive chip are externally connected to a signal generator;

[0017] The second pin of the gate drive chip is connected to one end of the first resistor, the third pin of the gate drive chip is connected to one end of the second resistor, the other end of the first resistor and the other end of the second resistor are both connected to the level signal receiving end of the switch module; the VCC pin of the gate drive chip and one end of the first capacitor are connected to the bus voltage, and the other end of the first capacitor is grounded.

[0018] Optionally, a circuit protection module is also included;

[0019] One end of the circuit protection module is connected to the switch signal output end of the switch module, and the other end of the circuit protection module is connected to the emitter of the silicon carbide MOS device to be tested.

[0020] Optionally, the circuit protection module includes a second capacitor and a third resistor;

[0021] One end of the second capacitor and the third resistor is connected to the switch signal output end of the switch module; the other end of the second capacitor and the third resistor is connected to the emitter of the silicon carbide MOS device to be tested.

[0022] Optionally, the power distribution module includes a key switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a fourth resistor and a fifth resistor;

[0023] The third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are connected in parallel, one end of the sixth capacitor is also connected to the emitter of the silicon carbide MOS device to be tested, and the other end of the sixth capacitor is also connected to the bus voltage;

[0024] One end of the third capacitor is also connected to one end of the fourth resistor, the other end of the third capacitor is also connected to one end of the fifth capacitor, and the key switch is connected between the other end of the fourth resistor and the other end of the fifth resistor.

[0025] Optionally, the switch module includes a first switch transistor, a second switch transistor, a first diode, a second diode, a sixth resistor and a seventh resistor;

[0026] The base of the first switch transistor and the base of the second switch transistor are the level signal receiving terminals;

[0027] The collector of the first switch transistor is the positive voltage input terminal, connected to the positive voltage output terminal of the isolation power supply, the emitter of the first switch transistor is connected to the input terminal of the second diode, and the output terminal of the second diode is connected to one end of the sixth resistor;

[0028] The collector of the second switch transistor is the negative voltage input terminal, connected to the negative voltage output terminal of the isolated power supply, the emitter of the second switch transistor is connected to the output terminal of the first diode, and the input terminal of the first diode is connected to one end of the seventh resistor;

[0029] The other end of the sixth resistor and the other end of the seventh resistor are both connected to the gate of the silicon carbide MOS device to be tested.

[0030] Optionally, the isolated power supply module includes an isolated power supply chip, a seventh capacitor and an eighth capacitor;

[0031] The seventh pin of the isolated power chip is the positive voltage output terminal, the eighth pin of the isolated power chip is the negative voltage output terminal, and the sixth pin of the isolated power chip provides a 0V voltage;

[0032] The seventh capacitor and the eighth capacitor are connected in parallel between the first pin of the isolation power chip and the second pin of the isolation power chip. The first pin of the isolation power chip, one end of the seventh capacitor, and one end of the eighth capacitor are the power supply voltage input terminals, and the other end of the seventh capacitor and the other end of the eighth capacitor are both grounded.

[0033] Optionally, the positive voltage output by the positive voltage output terminal is 17V, and the negative voltage output by the negative voltage output terminal is -8.7V.

[0034] A second aspect provides an EAS testing method applied to a silicon carbide MOS device, characterized in that, using the EAS testing device applied to a silicon carbide MOS device as shown above, the method comprises:

[0035] Installing the silicon carbide MOS device to be tested in the EAS testing device applied to the silicon carbide MOS device;

[0036] After the installation is completed, a pulse signal is output to the gate driving module, and the charging time of the pulse signal is sequentially extended according to the increase in the number of tests.

[0037] The technical principle of the present invention is as follows: the isolation power module outputs positive voltage and negative voltage when working, and the gate drive module outputs a high-level signal or a low-level signal. When a high-level signal is output, the control switch module turns on the positive voltage output by the isolation power module and connects it to the gate of the silicon carbide MOS device to be tested, so that the silicon carbide MOS device to be tested is turned on. When a low-level signal is output, the control switch module turns on the negative voltage output by the isolation power module and connects it to the gate and Kelvin pin of the silicon carbide MOS device to be tested, so that the silicon carbide MOS device to be tested is turned off. After being turned off, the current flowing through the silicon carbide MOS device to be tested in the test circuit again is the test current. This test current is used to test how much energy the silicon carbide MOS device to be tested can withstand without being damaged in the off state, thereby obtaining the EAS performance test result of the silicon carbide MOS device.

[0038] Compared with the prior art, the present invention has the following beneficial effects: by providing the gate voltage of the silicon carbide MOS device to be tested and the voltage value of the Kelvin pin through the isolation power supply module, the turn-on voltage required by the silicon carbide MOS device to be tested can be achieved at a lower cost compared with the gate drive module directly connected to the silicon carbide MOS device to be tested. At the same time, the isolation power supply module provides a negative voltage to the Kelvin pin, which not only reduces the stuck-off loss caused by the Kelvin pin being suspended, but also accelerates the discharge of the gate charge when the silicon carbide MOS device to be tested is turned off by turning on the negative voltage output by the isolation power supply module in the switch module, thereby achieving the purpose of rapid shutdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The circuit structure diagram of the EAS test circuit of silicon carbide MOS device based on IGBT and MOS test circuit;

[0040] Figure 2 This is a structural diagram of an EAS testing device applied to a silicon carbide MOS device according to an embodiment of the present invention;

[0041] Figure 3 This is a structural diagram of another EAS testing device applied to silicon carbide MOS devices according to an embodiment of the present invention;

[0042] Figure 4 A circuit structure diagram of an EAS testing device applied to a silicon carbide MOS device according to an embodiment of the present invention;

[0043] Figure 5 The present invention is a flowchart of an implementation of an EAS testing method applied to silicon carbide MOS devices according to an embodiment of the present invention.

[0044] In the above drawings: 100, driving circuit; 200, test circuit; 1, level signal output terminal; 2, driving voltage input terminal; 3, power supply voltage input terminal; 4, positive voltage output terminal; 5, negative voltage output terminal; 6, level signal receiving terminal; 8, negative voltage receiving terminal; 9, switch signal output terminal. DETAILED DESCRIPTION

[0045] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0046] like Figure 2 As shown, an embodiment of the present invention provides an EAS test device for silicon carbide MOS devices, including a drive circuit 100 and a test circuit 200. The drive circuit 100 includes a gate drive module U1, an isolation power module U2, and a switch module U4; the test circuit 200 includes a silicon carbide MOS device U3 to be tested.

[0047] The connection relationship of the above-mentioned parts is as follows: the gate driving module U1 and the isolation power supply module U2 are connected to the switch module U4, and the switch module U4 is connected to the silicon carbide MOS device U3 to be tested.

[0048] The detailed working process of the embodiment of the present invention is as follows:

[0049] The isolation power module U2 outputs positive voltage and negative voltage when working, and the gate drive module U1 outputs a high level signal or a low level signal. When a high level signal is output, the control switch module U4 turns on the positive voltage output by the isolation power module U2, and connects it to the gate of the silicon carbide MOS device U3 to be tested, so that the silicon carbide MOS device U3 to be tested is turned on. When a low level signal is output, the control switch module U4 turns on the negative voltage output by the isolation power module U2, and connects it to the gate and Kelvin pin of the silicon carbide MOS device U3 to be tested, so that the silicon carbide MOS device U3 to be tested is turned off. After being turned off, the current flowing through the silicon carbide MOS device U3 to be tested in the test circuit 200 again is the test current. This test current is used to test how much energy the silicon carbide MOS device U3 to be tested can withstand without being damaged in the off state, thereby obtaining the EAS performance test result of the silicon carbide MOS device U3.

[0050] Based on the EAS test circuit provided by the embodiment of the present invention, the gate voltage of the silicon carbide MOS device U3 to be tested and the voltage value of the Kelvin pin are provided by the isolation power supply module U2. Compared with the gate drive module U1 directly connecting to the silicon carbide MOS device U3 to be tested, the turn-on voltage required by the silicon carbide MOS device U3 to be tested can be achieved at a lower cost. At the same time, the isolation power supply module U2 provides a negative voltage to the Kelvin pin, which not only reduces the stuck-off loss caused by the Kelvin pin being suspended, but also opens the negative voltage output by the isolation power supply module U2 in the switch module U4, so that when the silicon carbide MOS device U3 to be tested is turned off, the discharge of the gate charge is accelerated to achieve the purpose of rapid shutdown.

[0051] In the embodiment of the present invention, an adjustable inductor L and a power distribution module U5 are provided in the test circuit, so that when the silicon carbide MOS device U3 to be tested is turned off, there is a current flowing through the silicon carbide MOS device U3 to be tested again in the test circuit 200. Figure 3 As shown, in Figure 2 On the basis of FIG. 1 , the flow of voltage signals in the driving circuit 100 and the testing circuit 200 is further explained.

[0052] First, the gate driving module U1 includes a level signal output terminal 1 and a driving voltage input terminal 2; the isolated power supply module U2 includes a power supply voltage input terminal 3, a positive voltage output terminal 4 and a negative voltage output terminal 5; the switch module U4 includes a level signal receiving terminal 6, a positive voltage receiving terminal 7, a negative voltage receiving terminal 8 and a switch signal output terminal 9. Secondly, the driving voltage input terminal 2 of the gate driving module U1, the power supply voltage input terminal 3 of the isolated power supply module U2 and one end of the distribution module U5 are connected to the bus voltage, and the other end of the distribution module U5 is connected to 0V voltage or ground; the level signal output terminal 1 of the gate driving module U1 is connected to the level signal receiving terminal 6 of the switch module U4, the positive voltage receiving terminal 7 of the switch module U4 is connected to the positive voltage output terminal 4 of the isolated power supply module U2, the negative voltage receiving terminal 8 of the switch module U4 is connected to the negative voltage output terminal 5 of the isolated power supply module U2, the switch signal output terminal 9 of the switch module U4 is connected to the gate of the silicon carbide MOS device U3 to be tested, the emitter of the silicon carbide MOS device U3 to be tested is connected to 0V voltage or ground, the Kelvin foot of the silicon carbide MOS device U3 to be tested is connected to the negative voltage output terminal 5, the collector of the silicon carbide MOS device U3 to be tested is connected to one end of the adjustable inductor L, and the other end of the adjustable inductor L is connected to one end of the distribution module U5.

[0053] based on Figure 3 In the embodiment of the present invention, the adjustable inductor L is used to provide a test current when the silicon carbide MOS device U3 to be tested is turned off, and the power distribution module U5 is used to supply power to the gate drive module and the isolation power supply module.

[0054] based on Figure 3, the test process of the EAS test circuit provided by the embodiment of the present invention is:

[0055] When the power distribution module U5 is working, the bus voltage supplies power to the gate drive module U1 and the isolated power supply module U2, and the gate drive module U1 and the isolated power supply module U2 work at the same time. Among them, when the isolated power supply module U2 is working, it outputs a positive voltage through the positive voltage output terminal 4 and outputs a negative voltage through the negative voltage output terminal 5. The driving signal of the gate drive module U1 comes from the signal generator RF. After receiving the pulse signal from the signal generator RF, the level signal output terminal 1 of the gate drive module U1 outputs a high level signal or a low level signal. When the high level signal is output, the control switch module U4 turns on the positive voltage output by the isolated power supply module U2, so that the silicon carbide MOS device U3 to be tested is turned on, and the adjustable inductor L is in a charging state. When the low level signal is output, the control switch module U4 turns on the negative voltage output by the isolated power supply module U2, so that the silicon carbide MOS device U3 to be tested is turned off. After shutdown, since the inductance characteristic current of the adjustable inductor L will not change suddenly, the test current provided by the adjustable inductor L will flow through the silicon carbide MOS device U3 to be tested. The test current is used to test how much energy the silicon carbide MOS device U3 to be tested can withstand without being damaged when it is in the shutdown state, thereby obtaining the EAS performance test result of the silicon carbide MOS device.

[0056] In a preferred implementation, the gate drive module U1 is mainly composed of a gate drive chip S1 and its peripheral circuits. The embodiment of the present invention only exemplarily shows a complete circuit structure that can be implemented. Figure 4 As shown, it includes a gate driver chip S1, a first resistor R1, a second resistor R2 and a first capacitor C1; wherein, the second pin OUT_SRC and the third pin OUT_SNK of the gate driver chip S1 are the level signal output terminal 1; the VDD pin of the gate driver chip S1 is the driving voltage input terminal 2; the fifth pin IN- and the sixth pin IN+ of the gate driver chip S1 are externally connected to the signal generator RF. The second pin OUT_SRC of the gate driver chip S1 is connected to one end of the first resistor R1, the third pin OUT_SNK of the gate driver chip S1 is connected to one end of the second resistor R2, and the other end of the first resistor R1 and the other end of the second resistor R2 are both connected to the level signal receiving terminal 6 of the switch module U4; the VDD pin of the gate driver chip S1 and one end of the first capacitor C1 are connected to the bus voltage, and the other end of the first capacitor C1 is grounded.

[0057] In one embodiment, a circuit protection module U6 is further included between the switch module U4 and the silicon carbide MOS device U3 to be tested, which is used to suppress the gate spike and surge current that the silicon carbide MOS device U3 to be tested may be subjected to after the switch module U4 is turned on. The detailed connection method is: one end of the circuit protection module U6 is connected to the switch signal output terminal 9 of the switch module U4, and the other end of the circuit protection module U6 is connected to the emitter of the silicon carbide MOS device U3 to be tested. In a preferred implementation, the circuit protection module U6 includes a second capacitor C2 and a third resistor R3; Figure 4 As shown, one end of the second capacitor C2 and the third resistor R3 is connected to the switch signal output terminal 9 of the switch module U4; the other end of the second capacitor C2 and the third resistor R3 is connected to the emitter of the silicon carbide MOS device U3 to be tested.

[0058] The embodiment of the present invention also provides a detailed structure of the power distribution module U5, such as Figure 4 As shown, the power distribution module U5 includes a key switch SW, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a fourth resistor R4 and a fifth resistor R5; the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, one end of the sixth capacitor C6 is also connected to the emitter of the silicon carbide MOS device U3 to be tested, and the other end of the sixth capacitor C6 is also connected to the bus voltage; one end of the third capacitor C3 is also connected to one end of the fourth resistor R4, the other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, and the key switch SW is connected between the other end of the fourth resistor R4 and the other end of the fifth resistor R5. In a specific application, the key switch SW should be disconnected at the beginning of the test, and the bus voltage should be powered on until the gate drive module U1 and the isolation power supply module U2 work when the 15V power supply is supplied.

[0059] In the embodiment of the present invention, the switch module U4 mainly includes two switch transistors, which respectively connect the positive voltage of the isolation power module U2 to the silicon carbide MOS device U3 to be tested when the high level signal of the gate drive module U1 is connected, and connect the negative voltage of the isolation power module U2 to the silicon carbide MOS device U3 to be tested when the low level signal of the gate drive module U1 is connected. In a better implementation, as Figure 4As shown, the switch module U4 includes a first switch transistor Q1, a second switch transistor Q2, a first diode D1, a second diode D2, a sixth resistor R6 and a seventh resistor R7. The above devices form a push-pull circuit, and the triode characteristics are used to make the current flowing through larger, so that the gate can be charged faster to accelerate the opening of the device; the base of the first switch transistor Q1 and the base of the second switch transistor Q2 are the level signal receiving end 6; the collector of the first switch transistor Q1 is the positive voltage receiving end 7, which is connected to the positive voltage output end 4 of the isolation power supply, the emitter of the first switch transistor Q1 is connected to the input end of the second diode D2, and the output end of the second diode D2 is connected to one end of the sixth resistor R6; the collector of the second switch transistor Q2 is the negative voltage receiving end 8, which is connected to the negative voltage output end 5 of the isolation power supply, the emitter of the second switch transistor Q2 is connected to the output end of the first diode D1, and the input end of the first diode D1 is connected to one end of the seventh resistor R7; the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are both connected to the gate of the silicon carbide MOS device U3 to be tested. To achieve the above switching characteristics, in the embodiment of the present invention, the first switch transistor Q1 is an NPN transistor, and the second switch transistor Q2 is a PNP transistor.

[0060] The embodiment of the present invention also provides a detailed structure of the isolated power supply module U2, such as Figure 4 As shown, the isolated power supply module U2 includes an isolated power supply chip, a seventh capacitor C7 and an eighth capacitor C8; the seventh pin of the isolated power supply chip is a positive voltage output terminal 4, the eighth pin of the isolated power supply chip is a negative voltage output terminal 5, and the sixth pin of the isolated power supply chip provides a 0V voltage; the seventh capacitor C7 and the eighth capacitor C8 are connected in parallel between the first pin of the isolated power supply chip and the second pin of the isolated power supply chip, the first pin of the isolated power supply chip, one end of the seventh capacitor C7, and one end of the eighth capacitor C8 are the power supply voltage input terminal 3, and the other end of the seventh capacitor C7 and the other end of the eighth capacitor C8 are both grounded.

[0061] In the embodiment of the present invention, the positive voltage outputted by the positive voltage output terminal 4 of the isolation power supply module U2 is 17V, and the negative voltage outputted by the negative voltage output terminal 5 is -8.7V. Thus, after the switch module U4 turns on the positive voltage outputted by the isolation power supply module U2, the positive voltage of 17V is inputted to the gate of the silicon carbide MOS device U3 to be tested, which is closer to the actual application scenario, making the test data more accurate and reducing the risk of pipe explosion during the test.

[0062] The embodiment of the present invention is also based on Figure 4 The EAS test device shown is applied to silicon carbide MOS devices, and its test process is explained again:

[0063] At the beginning of the test, the key switch SW in the power distribution module U5 is first disconnected, and the bus voltage is powered on. When the bus voltage is powered on to provide a 15V power supply, the gate drive module U1 and the isolation power module U2 work. At this time, the isolation power module U2 provides a 17V positive voltage and a -8.7V negative voltage, and the 17V positive voltage is connected to the collector of the first switch transistor Q1 of the switch module U4, and the -8.7V negative voltage is connected to the collector of the second switch transistor Q2 of the switch module U4. The gate drive module U1 is connected to the signal generator RF, and the signal generator RF provides a pulse signal. When the pulse signal is input to the gate drive module U1, the level signal output terminal 1 of the gate drive module U1 outputs a level signal to control the first switch transistor Q1 and the second switch transistor Q2 of the switch module U4. Assume that the level signal is a high level signal first. Since the first switch transistor Q1 is a PNP transistor and the second switch transistor Q2 is an NPN transistor, the first switch transistor Q1 is turned on and the second switch transistor Q2 is turned off. The first switch transistor Q1 turns on the 17V positive voltage provided by the isolation power supply module U2, that is, the collector of the first switch transistor Q1 is connected to the 17V positive voltage, so that the current passes through the second diode D2 and the sixth resistor R6 to reach the gate of the silicon carbide MOS device U3 to be tested, so that the silicon carbide MOS device U3 to be tested is turned on. Based on Figure 4 The isolated power supply module U2 provides a 0V voltage. Exemplarily, at this time, the bus voltage and the 0V voltage form a loop current that flows through the adjustable inductor L, thereby starting to charge the adjustable inductor L. After the level signal is switched to a low level signal, since the first switch transistor Q1 is a PNP transistor and the second switch transistor Q2 is an NPN transistor, the first switch transistor Q1 is turned off and the second switch transistor Q2 is turned on. The second switch transistor Q2 turns on the -8.7V negative voltage provided by the isolation power supply module U2, that is, the collector of the second switch transistor Q2 is connected to the -8.7V negative voltage, and at the same time, the Kelvin pin of the silicon carbide MOS device U3 to be tested is connected to the -8.7V negative voltage, which accelerates the shutdown of the silicon carbide MOS device U3 to be tested. Due to the inductance characteristics of the adjustable inductor L, the test current provided by the adjustable inductor L will not change suddenly, so the test current will flow through the silicon carbide MOS device U3 to be tested. The test current is used to test how much energy the silicon carbide MOS device U3 to be tested can withstand without being damaged when it is in the off state, thereby obtaining the EAS performance test result of the silicon carbide MOS device.

[0064] like Figure 5 As shown, according to another embodiment of the present invention, an EAS testing method applied to a silicon carbide MOS device is provided. Using the above-mentioned EAS testing device applied to a silicon carbide MOS device, the method includes:

[0065] S1, installing the silicon carbide MOS device to be tested in the EAS testing device applied to the silicon carbide MOS device;

[0066] S2. After the installation is completed, a pulse signal is output to the gate drive module, and the charging time of the pulse signal is extended in sequence according to the increase in the number of tests.

[0067] In a specific application, the charging time of the pulse signal affects the current magnitude of the current that flows through the silicon carbide MOS device U3 to be tested again after the silicon carbide MOS device U3 to be tested is turned off.

[0068] The embodiment of the present invention explains that the charging time of the pulse signal in the above step S2 is extended in sequence according to the increase in the number of tests: Assuming that in the first test, the charging time of the pulse signal in the control signal generator RF is A, when the pulse signal with a charging time of A is input to the gate drive module U1, the test ends until the current stored in the adjustable inductor L flows through the silicon carbide MOS device U3 to be tested again. In the second test, the charging time of the pulse signal in the control signal generator RF is A+B1, and in the third test, the charging time of the pulse signal in the control signal generator RF is A+B1+B2. Therefore, in the Nth test, the charging time of the pulse signal in the control signal generator RF is A+B1+B2+...+B (N-1) , N is greater than 2, where B (N-1) For each extended charging time.

[0069] It should be noted that the charging time extended each time may be the same, or may satisfy a linear relationship, which is not limited in the embodiment of the present invention.

[0070] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. An EAS test device for silicon carbide MOS devices, characterized in that: include: A driving circuit, the driving circuit comprising a gate driving module, an isolation power supply module, and a switch module; A test circuit, wherein the test circuit includes a silicon carbide MOS device to be tested; The gate driving module and the isolation power supply module are connected to the switch module, and the switch module is connected to the silicon carbide MOS device to be tested; The gate driving module controls the switch module to turn on the positive voltage provided by the isolation power module and connects to the gate of the silicon carbide MOS device to be tested; Alternatively, the gate driving module controls the switch module to turn on the negative voltage provided by the isolation power module and connect it to the gate and Kelvin pin of the silicon carbide MOS device to be tested.

2. The EAS testing device for silicon carbide MOS devices according to claim 1, characterized in that: The test circuit also includes an adjustable inductor and a power distribution module; The gate driving module includes a level signal output terminal and a driving voltage input terminal; the isolated power supply module includes a power supply voltage input terminal, a positive voltage output terminal and a negative voltage output terminal; the switch module includes a level signal receiving terminal, a positive voltage receiving terminal, a negative voltage receiving terminal and a switch signal output terminal; The driving voltage input end of the gate driving module, the power voltage input end of the isolated power module and one end of the power distribution module are connected to the bus voltage, and the other end of the power distribution module is connected to 0V voltage / ground; the level signal output end of the gate driving module is connected to the level signal receiving end of the switch module, the positive voltage receiving end of the switch module is connected to the positive voltage output end of the isolated power module, the negative voltage receiving end of the switch module is connected to the negative voltage output end of the isolated power module, the switch signal output end of the switch module is connected to the gate of the silicon carbide MOS device to be tested, the emitter of the silicon carbide MOS device to be tested is connected to 0V voltage / ground, the Kelvin pin of the silicon carbide MOS device to be tested is connected to the negative voltage output end, the collector of the silicon carbide MOS device to be tested is connected to one end of the adjustable inductor, and the other end of the adjustable inductor is connected to one end of the power distribution module.

3. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: The gate driving module includes a gate driving chip, a first resistor, a second resistor and a first capacitor; The second pin and the third pin of the gate drive chip are the level signal output terminals; the VCC pin of the gate drive chip is the drive voltage input terminal; the fifth pin and the sixth pin of the gate drive chip are externally connected to a signal generator; The second pin of the gate drive chip is connected to one end of the first resistor, the third pin of the gate drive chip is connected to one end of the second resistor, the other end of the first resistor and the other end of the second resistor are both connected to the level signal receiving end of the switch module; the VCC pin of the gate drive chip and one end of the first capacitor are connected to the bus voltage, and the other end of the first capacitor is grounded.

4. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: Also included is a circuit protection module; One end of the circuit protection module is connected to the switch signal output end of the switch module, and the other end of the circuit protection module is connected to the emitter of the silicon carbide MOS device to be tested.

5. The EAS testing device for silicon carbide MOS devices according to claim 4, characterized in that: The circuit protection module includes a second capacitor and a third resistor; One end of the second capacitor and the third resistor is connected to the switch signal output end of the switch module; the other end of the second capacitor and the third resistor is connected to the emitter of the silicon carbide MOS device to be tested.

6. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: The power distribution module includes a key switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a fourth resistor and a fifth resistor; The third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are connected in parallel, one end of the sixth capacitor is also connected to the emitter of the silicon carbide MOS device to be tested, and the other end of the sixth capacitor is also connected to the bus voltage; One end of the third capacitor is also connected to one end of the fourth resistor, the other end of the third capacitor is also connected to one end of the fifth capacitor, and the key switch is connected between the other end of the fourth resistor and the other end of the fifth resistor.

7. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: The switch module includes a first switch transistor, a second switch transistor, a first diode, a second diode, a sixth resistor and a seventh resistor; The base of the first switch transistor and the base of the second switch transistor are the level signal receiving terminals; The collector of the first switch transistor is the positive voltage input terminal, connected to the positive voltage output terminal of the isolation power supply, the emitter of the first switch transistor is connected to the input terminal of the second diode, and the output terminal of the second diode is connected to one end of the sixth resistor; The collector of the second switch transistor is the negative voltage input terminal, connected to the negative voltage output terminal of the isolated power supply, the emitter of the second switch transistor is connected to the output terminal of the first diode, and the input terminal of the first diode is connected to one end of the seventh resistor; The other end of the sixth resistor and the other end of the seventh resistor are both connected to the gate of the silicon carbide MOS device to be tested.

8. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: The isolated power supply module includes an isolated power supply chip, a seventh capacitor and an eighth capacitor; The seventh pin of the isolated power chip is the positive voltage output terminal, the eighth pin of the isolated power chip is the negative voltage output terminal, and the sixth pin of the isolated power chip provides a 0V voltage; The seventh capacitor and the eighth capacitor are connected in parallel between the first pin of the isolation power chip and the second pin of the isolation power chip. The first pin of the isolation power chip, one end of the seventh capacitor, and one end of the eighth capacitor are the power supply voltage input terminals, and the other end of the seventh capacitor and the other end of the eighth capacitor are both grounded.

9. The EAS testing device for silicon carbide MOS devices according to claim 2, characterized in that: The positive voltage outputted by the positive voltage output terminal is 17V, and the negative voltage outputted by the negative voltage output terminal is -8.7V.

10. An EAS testing method applied to silicon carbide MOS devices, characterized in that: Using the EAS testing device applied to silicon carbide MOS devices as claimed in any one of claims 1 to 9, the method comprises: Installing the silicon carbide MOS device to be tested in the EAS testing device applied to the silicon carbide MOS device; After the installation is completed, a pulse signal is output to the gate driving module, and the charging time of the pulse signal is sequentially extended according to the increase in the number of tests.

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