Verification system and method for GPIO (General Purpose Input / Output) module in vehicle gauge level chip
By designing a GPIO module verification system based on UVM verification method in automotive-grade chips, combining software, hardware and test modes, the problem of insufficient verification accuracy in traditional methods is solved, and the verification accuracy and security of GPIO modules is significantly improved. performance.
Patent Information
- Application Number
- CN202411374304.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2024-12-27
AI Technical Summary
The accuracy of GPIO module verification in traditional automotive-grade chips is insufficient, especially in the field of new energy vehicles, and the safety performance requirements are high. Traditional GPIO module verification relies on software control and lacks support for hardware and test modes.
Design a GPIO module verification system in automotive-grade chips, using a verification environment created by the test case base class based on UVM verification methodology, including reference models, scoreboards, hardware and software input/output agents and monitors, combined with Software, hardware and test modes are verified to ensure the independence of each pin and the mutual verification of multiple modes.
It significantly improves the accuracy and security performance of GPIO module verification. Through the introduction of hardware mode and test mode, the independence of input/output direction and verification of GPIO module are ensured, and the problem of insufficient verification accuracy in traditional methods is solved. .
Smart Images
Figure CN119201582A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of automotive chip verification, and relates to a GPIO module verification system and method in an automotive-grade chip. Background Art
[0002] With the rapid development of the automotive industry, car manufacturers and customers are paying more and more attention to automobile safety, which puts higher requirements on the functional safety of automotive chips. GPIO (general porpose input output) is a standard interface between chips and between chips and external pads (i.e., external connection points or pins, used to connect chips with external devices or circuits. These pads can be welding points, plugs or connectors, which help to achieve physical connection and signal transmission between chips and other hardware (such as sensors, displays or power supplies)). Its importance is self-evident. The GPIO of traditional NCU (Numenrical Control unit) mainly relies on software for input and output control and lacks other control methods. Obviously, ordinary GPIO needs to further expand its functions in the field of new energy vehicles with extremely high safety performance requirements. In the software mode of traditional GPIO module verification, the excitation in the input direction is controlled by peripherals, and the excitation in the output direction is configured by registers. In the current automotive-grade chips, the traditional GPIO module verification still has the technical problem of insufficient verification accuracy. Summary of the invention
[0003] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes a GPIO module verification system in an automotive-grade chip and a GPIO module verification method in an automotive-grade chip, which can effectively improve the accuracy of GPIO module verification in an automotive-grade chip.
[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:
[0005] On the one hand, a GPIO module verification system in an automotive-grade chip is provided, including a verification environment created based on a test case base class of UVM verification methodology, wherein the verification environment includes a reference model, a scoreboard, n input agents of hardware input modes, n input agents of hardware output modes, n monitors of hardware input modes, n monitors of hardware output modes, n input agents of software input modes, n monitors of software input modes, n monitors of software output modes, n monitors of test input modes, and n monitors of test output modes; n is the number of pins of the GPIO module;
[0006] The input ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively used to connect to the GPIO modules to be tested, and the output ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively connected to the reference model;
[0007] Input ends of the n monitors in hardware input mode, the n monitors in hardware output mode, the n monitors in software input mode, the n monitors in software output mode, the n monitors in test input mode, and the n monitors in test output mode are respectively used to connect to the GPIO modules to be tested, and output ends of the n monitors in hardware input mode, the n monitors in hardware output mode, the n monitors in software input mode, the n monitors in software output mode, the n monitors in test input mode, and the n monitors in test output mode are respectively connected to the scoreboard;
[0008] The reference model is connected to the scoreboard. The reference model is used to calculate and output the expected result according to the data packet stimulated by the verification environment to the GPIO module to be tested. The scoreboard is used to compare the expected result with the actual output result of the GPIO module to be tested and output the comparison result information.
[0009] On the other hand, a GPIO module verification method in an automotive-grade chip is also provided, which is applied to a GPIO module verification system in an automotive-grade chip, wherein the GPIO module verification system includes a verification environment created based on a test case base class of UVM verification methodology, wherein the verification environment includes a reference model, a scoreboard, n input agents of hardware input modes, n input agents of hardware output modes, n monitors of hardware input modes, n monitors of hardware output modes, n input agents of software input modes, n monitors of software input modes, n monitors of software output modes, n monitors of test input modes, and n monitors of test output modes; n is the number of pins of the GPIO module;
[0010] The input ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively used to connect to the GPIO modules to be tested, and the output ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively connected to the reference model;
[0011] Input ends of the n monitors in hardware input mode, the n monitors in hardware output mode, the n monitors in software input mode, the n monitors in software output mode, the n monitors in test input mode, and the n monitors in test output mode are respectively used to connect to the GPIO modules to be tested, and output ends of the n monitors in hardware input mode, the n monitors in hardware output mode, the n monitors in software input mode, the n monitors in software output mode, the n monitors in test input mode, and the n monitors in test output mode are respectively connected to the scoreboard;
[0012] The reference model is connected to the scoreboard. The reference model is used to calculate and output the expected results based on the data packets stimulated by the verification environment to the GPIO module to be tested. The scoreboard is used to compare the expected results with the actual output results of the GPIO module to be tested and output the comparison result information.
[0013] The GPIO module verification method in the automotive-grade chip includes the following steps:
[0014] Connect the GPIO module to be tested to the GPIO module verification system and start the system;
[0015] Perform random register configuration on the GPIO module verification system;
[0016] Send the register configuration to the reference model and write the register configuration to the GPIO module to be tested through the APB bus;
[0017] The reference model calculates the expected results of the GPIO module under test in the current working mode and working direction according to the register configuration;
[0018] The actual output result of the GPIO module to be tested is collected through the monitor corresponding to the current working mode;
[0019] After receiving the expected result and the actual output result, the scoreboard compares the expected result and the actual output result and outputs comparison result information; the comparison result information is used to indicate the verification result of the GPIO module to be tested under the current working mode and working direction;
[0020] When all stimuli are sent and the result comparison is completed, the verification of the GPIO module to be tested is completed.
[0021] One of the above technical solutions has the following advantages and beneficial effects:
[0022] The GPIO module verification system and method in the above-mentioned automotive-grade chip, by designing three working modes, namely software mode, hardware mode and test mode, and the corresponding input and output directions in each working mode in the verification system, and each pin of the GPIO module can be an independent function (channel), in the verification process of the GPIO module, each working mode, the corresponding input / output direction and the pin are independent, n input agents and monitors are instantiated, each input agent corresponds to a pin, and the monitor corresponds similarly, the channel is selected through the test case base class to execute the corresponding working mode, and the corresponding monitor collects output data, and then the correctness of the GPIO module verification can be ensured by comparing the scoreboard, the three working modes share the collection port and verify each other, which significantly improves the accuracy of the GPIO module verification, and well solves the GPIO module verification problem in automotive-grade chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1 A schematic diagram of the platform architecture of a GPIO module verification system in an automotive-grade chip in one embodiment;
[0025] Figure 2 A schematic diagram of an operation process of a GPIO module verification system in an automotive-grade chip in an embodiment;
[0026] Figure 3 The figure is a flowchart of a GPIO module verification method in an automotive-grade chip in one embodiment. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0028] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.
[0029] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.
[0030] In one embodiment, Figure 1 As shown, a GPIO module verification system in an automotive-grade chip is provided, including a verification environment created by a test case base class (Base_testcase) based on the UVM verification methodology, wherein the verification environment includes a reference model (RM), a scoreboard (SCB), n input agents of hardware input modes (i.e., hardware input mode agent*n), n input agents of hardware output modes (i.e., hardware output mode agent*n), n monitors of hardware input modes (i.e., hardware input mode monitor*n), n monitors of hardware output modes (i.e., hardware output mode monitor*n), n input agents of software input modes (i.e., software input mode agent*n), n monitors of software input modes (i.e., software input mode monitor*n), n monitors of software output modes (i.e., software output mode monitor*n), n monitors of test input modes (i.e., test input mode monitor*n) and n monitors of test output modes (i.e., test output mode monitor*n); n is the number of pins of the GPIO module to be tested.
[0031] The input terminals of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively used to connect to the GPIO module to be tested, and the output terminals of the n input agents of the hardware input mode, the n input agents of the hardware output mode, and the n input agents of the software input mode are respectively connected to the reference model. The GPIO module to be tested is the DUT of this embodiment, also called the GPIO design to be tested.
[0032] The input ends of the n monitors of hardware input mode, n monitors of hardware output mode, n monitors of software input mode, n monitors of software output mode, n monitors of test input mode and n monitors of test output mode are respectively used to connect the GPIO module to be tested, and the output ends of the n monitors of hardware input mode, n monitors of hardware output mode, n monitors of software input mode, n monitors of software output mode, n monitors of test input mode and n monitors of test output mode are respectively connected to the scoreboard. The reference model is connected to the scoreboard, and the reference model is used to calculate and output the expected result according to the data packet stimulated to the GPIO module to be tested by the verification environment, and the scoreboard is used to compare the expected result with the actual output result of the GPIO module to be tested, and output the comparison result information.
[0033] It can be understood that for the verification of GPIO modules in automotive-grade chips with high safety performance, the study has added control methods of test mode and hardware mode. Therefore, for the GPIO modules in automotive-grade chips, this application designs a new GPIO module verification system in automotive-grade chips, which has three control modes: hardware mode, software mode and test mode: In the traditional software mode, the excitation in its input direction is controlled by the peripherals, and the excitation in the output direction is configured by the register. The role of the hardware mode is to directly use the peripherals to perform control or data acquisition. Regardless of the input direction or the output direction, the excitation is controlled by the peripherals. The role of the test mode is to map the input and output of the hardware mode. Regardless of the input direction or the output direction, the excitation is configured by the register. These three modes share the acquisition port and verify each other, which significantly improves the accuracy of the verification of the GPIO module in the automotive-grade chip and further enhances the safety performance of the automotive-grade chip.
[0034] The GPIO module verification system in the above-mentioned automotive-grade chip designs three working modes, namely software mode, hardware mode and test mode, in the verification system, as well as the corresponding input and output directions in each working mode, and each pin of the GPIO module can be an independent function (channel). In the verification process of the GPIO module, each working mode, corresponding input / output direction and pin are independent, and n input agents and monitors are instantiated. Each input agent corresponds to a pin, and the monitor corresponds similarly. The channel is selected through the test case base class to execute the corresponding working mode, and the corresponding monitor collects output data. Then, the correctness of the GPIO module verification can be ensured by comparing the scoreboard. The three working modes share the collection port and verify each other, which significantly improves the accuracy of the GPIO module verification and well solves the GPIO module verification problem in automotive-grade chips.
[0035] Specifically, the GPIO module verification system in the above-mentioned automotive-grade chip has two more working modes, hardware mode and test mode, compared with the traditional GPIO module verification system. The descriptions of different working modes can be as follows:
[0036] Traditional software mode: divided into input direction and output direction, direction selection is controlled by register configuration; in software input mode, the external pad inputs the stimulus and the internal data register collects it; in software output mode, the internal data register sends the stimulus and the external port receives it to control the external pad. Among them, input direction and output direction refer to the direction of data flow, for example, input direction: the chip receives signals from the external pad or accesses data. In this software input mode, the stimulus of the external device (such as sensor signal) enters the internal data register through the external connection for collection. And output direction: the chip sends signals to the external pad or accesses data. In this software output mode, the stimulus signal in the internal data register is sent, and the external device (such as actuator or LED) receives and responds to these signals. By controlling the direction selection through register configuration, the chip can flexibly switch between these two software input / output modes.
[0037] In one embodiment, when the GPIO module verification system operates in hardware mode, the selection of the pin input direction and output direction of the GPIO module to be tested is controlled by an external pad, and verification data (including access data, enable and interrupt signals) is received by the external pad.
[0038] It can be understood that the hardware mode is divided into input direction and output direction. The direction selection is controlled by the external pad (rather than register configuration control). The verification data (including access data, enable and interrupt signals) output is still received by the external pad.
[0039] In one embodiment, when the GPIO module verification system operates in the test mode, the output of the hardware mode is tested by mapping the input of the hardware mode to the register in the configuration verification environment.
[0040] It can be understood that the test mode: the role of the test mode is to map the verification data of the output port of the hardware mode to see if it is correct. The verification data of these output ports may include access data, enable signals and interrupt signals. The output of the hardware mode is tested by mapping the input of the hardware mode through the configuration register.
[0041] The output directions of the above three working modes share the same type of ports, including data ports, enable ports and interrupt ports, and the above three working modes can verify each other. The GPIO pins of the GPIO module in the automotive-grade chip are independent, and the functions of different GPIO pins can be different. This results in that when sending stimuli in different working modes, the output data collected from the GPIO pins cannot know which working mode and input / output direction it is, which directly increases the difficulty of verifying the GPIO module in the automotive-grade chip.
[0042] To this end, the platform architecture of the GPIO module verification system in the automotive-grade chip is as follows Figure 1 As shown, the platform architecture of the GPIO module verification system separates the three working modes and the input / output directions of the corresponding working modes: n input agents for hardware input mode, n input agents for hardware output mode, n monitors for hardware input mode, n monitors for hardware output mode, n input agents for software input mode, n monitors for software input mode, n monitors for software output mode, n monitors for test input mode, and n monitors for test output mode. n represents the number of pins of the GPIO module (i.e., the physical pins or connection points on the GPIO module, which are used for input and output signals, and each pin can be configured as input or output mode). The parameters can be configured as needed. The input (stimulus) of the software output mode, test input mode, and test output mode are all configured by registers, and no agent component agent is required. When working, the corresponding input agent and the corresponding monitor are selected according to the configuration, so that the output of the same pin on the GPIO module will only have one working mode.
[0043] The specific verification workflow of the GPIO module verification system in the automotive-grade chip can be generally described as follows:
[0044] The GPIO module can configure the registers through the APB (Advanced Peripheral Bus) bus. In the sequence, you can select which pin of the GPIO module adopts which working mode according to needs or random constraints. Each input agent selects the corresponding pin through the sequence to send a data packet to the corresponding driver. The data packet can contain data (access data) and enable (en, which expresses the input direction or output direction under this working mode). The driver drives the GPIO module according to the data packet.
[0045] The APB bus configuration register is used to select the working mode and working direction (except the hardware mode, where the working direction is controlled by an external pad). The register is randomly configured each time, making the working mode and working direction random, and the functions and combinations of each pin of the GPIO module can be traversed.
[0046] The reference model of the platform architecture can obtain the configuration of the registers. When the drivers of different input modes send data packets (stimulus) to the GPIO module, the data packets will be sent to the reference model through the corresponding channels. The reference model will receive the same data packets as those received by the GPIO module, and then calculate the expected results such as the enable signal, access data, and interrupt signal to be output by the GPIO module according to different working modes and different working directions, and send these expected results to the scoreboard (SCB).
[0047] The output mode monitor of the GPIO module collects the actual output results of the GPIO module according to different mode configurations, including access data, enable signals and interrupt signals, and then sends them to the scoreboard.
[0048] The scoreboard receives the expected results from the reference model and the actual output results received by the monitor in different working modes and input directions (or output directions), and compares the results. When the expected results are inconsistent with the actual output results, the scoreboard outputs the comparison result information to indicate the problems in the GPIO module verification.
[0049] The test case base class (Base_testcase) of the platform architecture is used to implement random constraints on register configuration, the number of packets sent, and the content of the packets (including access data and enable randomness). At the same time, the test case base class can derive test cases with different constraints to verify the single function and combined functions of the GPIO module, such as Figure 2 The following is an example of the execution process of the GPIO module verification system in an automotive-grade chip, which may include the following steps:
[0050] The system starts, randomly configures registers (i.e., different GPIO pins randomly select working modes and working directions), sends register configurations to the reference model, and writes register configurations to the GPIO module to be tested through the APB bus. After the configuration is ready, randomly send the data packets to be sent to the reference model, and send stimulus to the GPIO module to be tested using the corresponding driver and register according to the configuration and the corresponding working mode and working direction. Then, the reference model calculates the expected results such as access data, enable signals, and interrupt signals of different working modes and working directions according to the configuration. The monitors of different working modes collect the actual output results (including access data, enable signals, and interrupt signals) of the corresponding bits of the GPIO module to be tested according to the configuration. After the scoreboard receives the expected results and actual output results of different working modes and working directions, it compares the expected results and actual output results of different working modes and working directions, and outputs the comparison result information. Finally, it is determined whether all stimuli have been sent. If so, the verification ends. If not, it jumps to the step of randomly sending the data packets to be sent to the reference model, and continues to perform verification until the verification ends.
[0051] It should be noted that each component of the platform architecture in the above system can be built using the SystemVerilog language commonly used in the art and follow the UVM verification methodology, and can be built using the components in the UVM verification methodology according to the test interaction functions required to be provided.
[0052] Each module in the GPIO module verification system in the above-mentioned automotive-grade chip can be fully or partially implemented by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the above-mentioned device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules. The above-mentioned device can be, but is not limited to, various types of verification computer devices already available in the art.
[0053] In one embodiment, Figure 3 As shown, a GPIO module verification method in an automotive-grade chip is provided, which is applied to the GPIO module verification system in the above-mentioned automotive-grade chip. The GPIO module verification system includes a verification environment created based on a test case base class of UVM verification methodology, and the verification environment includes a reference model, a scoreboard, n input agents of hardware input modes, n input agents of hardware output modes, n monitors of hardware input modes, n monitors of hardware output modes, n input agents of software input modes, n monitors of software input modes, n monitors of software output modes, n monitors of test input modes, and n monitors of test output modes; n is the number of pins of the GPIO module.
[0054] The input ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively used to connect to the GPIO modules to be tested, and the output ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively connected to the reference model.
[0055] The input ends of the n monitors of hardware input mode, n monitors of hardware output mode, n monitors of software input mode, n monitors of software output mode, n monitors of test input mode and n monitors of test output mode are respectively used to connect the GPIO module to be tested, and the output ends of the n monitors of hardware input mode, n monitors of hardware output mode, n monitors of software input mode, n monitors of software output mode, n monitors of test input mode and n monitors of test output mode are respectively connected to the scoreboard. The reference model is connected to the scoreboard, and the reference model is used to calculate and output the expected result according to the data packet stimulated to the GPIO module to be tested by the verification environment, and the scoreboard is used to compare the expected result with the actual output result of the GPIO module to be tested, and output the comparison result information.
[0056] The GPIO module verification method in the automotive-grade chip may include the following processing steps S10 to S22:
[0057] S10, connecting the GPIO module to be tested to the GPIO module verification system and then starting the system;
[0058] S12, performing random register configuration on the GPIO module verification system;
[0059] S14, sending the register configuration to the reference model and writing the register configuration to the GPIO module to be tested through the APB bus;
[0060] S16, the reference model calculates the expected result of the GPIO module to be tested in the current working mode and working direction according to the register configuration;
[0061] S18, collecting the actual output result of the GPIO module to be tested through the monitor corresponding to the current working mode;
[0062] S20, after receiving the expected result and the actual output result, the scoreboard compares the expected result and the actual output result and outputs comparison result information; the comparison result information is used to indicate the verification result of the GPIO module to be tested under the current working mode and working direction;
[0063] S22, when all stimuli are sent and the result comparison is completed, the verification of the GPIO module to be tested is completed.
[0064] The GPIO module verification method in the above-mentioned automotive-grade chip designs three working modes, namely software mode, hardware mode and test mode, in the verification system, as well as the corresponding input and output directions in each working mode, and each pin of the GPIO module can be an independent function (channel). In the verification process of the GPIO module, each working mode, the corresponding input / output direction and the pin are independent, and n input agents and monitors are instantiated. Each input agent corresponds to a pin, and the monitor corresponds similarly. The channel is selected through the test case base class to execute the corresponding working mode, and the corresponding monitor collects the output data, and then the correctness of the GPIO module verification can be ensured by comparing the scoreboard. The three working modes share the collection port and verify each other, which significantly improves the accuracy of the GPIO module verification and well solves the GPIO module verification problem in automotive-grade chips.
[0065] In one embodiment, after the scoreboard receives the expected result and the actual output result, and after the step of comparing the expected result and the actual output result and outputting the comparison result information, the step further includes:
[0066] When all stimuli have not been sent, jump to the step of sending the register configuration to the reference model and writing the register configuration to the GPIO module to be tested through the APB bus, and continue to perform verification until the verification is completed.
[0067] In one embodiment, when the GPIO module verification system works in hardware mode, the selection of the pin input direction and output direction of the GPIO module to be tested is controlled by an external pad, and the verification data is received by the external pad.
[0068] In one embodiment, when the GPIO module verification system operates in the test mode, the output of the hardware mode is tested by mapping the input of the hardware mode to the register in the configuration verification environment.
[0069] It can be understood that for the specific limitations of the GPIO module verification method in automotive-grade chips, please refer to the corresponding limitations of the GPIO module verification system in automotive-grade chips in the above text, and will not be repeated here.
[0070] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0071] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).
[0072] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0073] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.
Claims
1. A GPIO module verification system in an automotive-grade chip, characterized in that: A verification environment is provided, comprising a test case base class based on UVM verification methodology, wherein the verification environment comprises a reference model, a scoreboard, input agents of n hardware input modes, input agents of n hardware output modes, monitors of n hardware input modes, monitors of n hardware output modes, input agents of n software input modes, monitors of n software input modes, monitors of n software output modes, monitors of n test input modes, and monitors of n test output modes; n is the number of pins of the GPIO module; The input ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively used to connect to the GPIO module to be tested, and the output ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively connected to the reference model; The input ends of the n monitors of the hardware input mode, the n monitors of the hardware output mode, the n monitors of the software input mode, the n monitors of the software output mode, the n monitors of the test input mode and the n monitors of the test output mode are respectively used to connect to the GPIO module to be tested, and the output ends of the n monitors of the hardware input mode, the n monitors of the hardware output mode, the n monitors of the software input mode, the n monitors of the software output mode, the n monitors of the test input mode and the n monitors of the test output mode are respectively connected to the scoreboard; The reference model is connected to the scoreboard, and the reference model is used to calculate and output expected results based on the data packets stimulated by the verification environment to the GPIO module to be tested, and the scoreboard is used to compare the expected results with the actual output results of the GPIO module to be tested, and output comparison result information.
2. The GPIO module verification system in the automotive-grade chip according to claim 1 is characterized in that: When the GPIO module verification system works in hardware mode, the selection of the pin input direction and output direction of the GPIO module to be tested is controlled by an external pad, and the verification data is received by the external pad.
3. The GPIO module verification system in the automotive-grade chip according to claim 1 or 2, characterized in that: When the GPIO module verification system operates in the test mode, the output of the hardware mode is tested by configuring the registers in the verification environment to map the input of the hardware mode.
4. A GPIO module verification method in an automotive-grade chip, characterized in that: A GPIO module verification system is applied to a car-grade chip, the GPIO module verification system includes a verification environment created based on a test case base class of UVM verification methodology, the verification environment includes a reference model, a scoreboard, n input agents of hardware input modes, n input agents of hardware output modes, n monitors of hardware input modes, n monitors of hardware output modes, n input agents of software input modes, n monitors of software input modes, n monitors of software output modes, n monitors of test input modes, and n monitors of test output modes; n is the number of pins of the GPIO module; The input ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively used to connect to the GPIO module to be tested, and the output ends of the n input agents of the hardware input mode, the n input agents of the hardware output mode and the n input agents of the software input mode are respectively connected to the reference model; The input ends of the n monitors of the hardware input mode, the n monitors of the hardware output mode, the n monitors of the software input mode, the n monitors of the software output mode, the n monitors of the test input mode and the n monitors of the test output mode are respectively used to connect to the GPIO module to be tested, and the output ends of the n monitors of the hardware input mode, the n monitors of the hardware output mode, the n monitors of the software input mode, the n monitors of the software output mode, the n monitors of the test input mode and the n monitors of the test output mode are respectively connected to the scoreboard; The reference model is connected to the scoreboard, and the reference model is used to calculate and output an expected result according to the data packet stimulated by the verification environment to the GPIO module to be tested, and the scoreboard is used to compare the expected result with the actual output result of the GPIO module to be tested, and output the comparison result information. The GPIO module verification method in the automotive-grade chip includes the steps of: Connecting the GPIO module to be tested to the GPIO module verification system and then starting the system; Performing random register configuration on the GPIO module verification system; Sending the register configuration to the reference model and writing the register configuration to the GPIO module to be tested via the APB bus; The reference model calculates the expected result of the GPIO module to be tested under the current working mode and working direction according to the register configuration; Collecting the actual output result of the GPIO module to be tested through a monitor corresponding to the current working mode; After receiving the expected result and the actual output result, the scoreboard compares the expected result and the actual output result and outputs comparison result information; The comparison result information is used to indicate the verification result of the GPIO module to be tested under the current working mode and working direction; When all stimuli are sent and the result comparison is completed, the verification of the GPIO module to be tested is completed.
5. The GPIO module verification method in the automotive-grade chip according to claim 4 is characterized in that: After the scoreboard receives the expected result and the actual output result, and compares the expected result and the actual output result and outputs comparison result information, the scoreboard further includes the following steps: When all stimuli have not been sent, jump to the step of sending the register configuration to the reference model and writing the register configuration to the GPIO module to be tested through the APB bus, and continue to perform verification until the verification is completed.
6. The GPIO module verification method in the automotive-grade chip according to claim 4 is characterized in that: When the GPIO module verification system works in hardware mode, the selection of the pin input direction and output direction of the GPIO module to be tested is controlled by an external pad, and the verification data is received by the external pad.
7. The GPIO module verification method in the automotive-grade chip according to claim 4 or 6, characterized in that: When the GPIO module verification system operates in the test mode, the output of the hardware mode is tested by configuring the registers in the verification environment to map the input of the hardware mode.