Coded disc speed measurement fixed-point calculation improvement method

Abstract

The invention relates to a coded disc speed measurement fixed-point calculation improvement method, which comprises the following steps of: calculating a speed measurement required amount in a process of calculating in a DSP (Digital Signal Processor) initialization stage, calculating by an upper computer and then sending to the DSP, or other modes which do not influence the CPU (Central Processing Unit) utilization rate of the DSP; the method comprises the following steps: sampling A / B phase signals of a coded disc by adopting first frequency multiplication, second frequency multiplication or quadruplicated frequency according to actual conditions, generating pulse signals, and calculating the number of pulses and the number of clocks corresponding to the pulses in each sampling period; the rotating speed compensation coefficient is calculated by the DSP or the upper computer and then is sent to the DSP; and the rotating speed is calculated by integrating obtained results. The code disc speed measurement calculation method is improved, the method for reducing the relative error is provided especially for the problem that the calculation error of a fixed-point system is slightly large, the calculation error of the fixed-point system can be reduced, the method is more obvious especially in a low-speed area, the calculated rotating speed of the motor is high in accuracy and small in error, and meanwhile the implementation scheme of the method is simple and easy to implement. The relative calculation amount is small, the improvement effect is obvious, and the application effect is good.

Description

Technical Field

[0001] The invention belongs to the technical field of motor control, and in particular to an improved method for fixed-point calculation of code disk speed measurement. Background Art

[0002] Motors are widely used in automation control, industrial machinery, aerospace, automobiles, etc. In industrial motor control, motor speed measurement is crucial, and its accuracy determines the performance of the entire control system.

[0003] The AC motor speed vector control system generally uses an encoder mounted on the motor shaft to measure the motor speed feedback, where the encoder is also called a "code disc". Code discs are divided into absolute, incremental and hybrid types according to the output signal. Incremental code discs are widely used in AC motor speed control systems due to their high reliability, strong anti-interference, high resolution, low cost and easy maintenance. The incremental code disc directly uses the principle of photoelectric conversion to output three sets of square waves A, B and Z phases. Its speed measurement principle is based on pulse counting and timing. The main speed measurement methods include M method, T method and M / T method.

[0004] AC motors generally use DSP chips to achieve system control. Due to factors such as chip model, software version, and engineering habits, the control system will use fixed-point calculation. Fixed-point calculation is suitable for control systems with high response speed requirements, but it will cause data calculation accuracy loss, and the relative error is slightly larger than floating-point calculation, especially in the low-speed area.

[0005] At present, there are some improved methods for the speed calculation of motor control systems in low-speed areas. The use of methods such as high-frequency injection and interpolation estimation can greatly improve the accuracy of motor speed measurement in low-speed areas, but it is difficult to meet the requirements of speed measurement accuracy and dynamic response at the same time. The response speed of fixed-point system calculation is relatively high. The fixed-point number expansion method needs to take into account both high-speed and low-speed calculations. After the fixed-point number is expanded, the speed calculation will occupy relatively more computing resources. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and propose an improved method for fixed-point calculation of code disk speed measurement, which improves the code disk speed measurement calculation method. In particular, for the problem that the calculation error of the fixed-point system is slightly large, a method for reducing the relative error is proposed, which can reduce the calculation error of the fixed-point system, especially in the low-speed zone. The calculated motor speed is accurate, the error is small, and the application effect is good.

[0007] The present invention solves the technical problem by adopting the following technical solutions:

[0008] An improved method for calculating the fixed point of code disk speed measurement includes the following steps:

[0009] Step 1: Calculate the amount required for speed measurement during the DSP initialization phase, or send it to the DSP after calculation by the host computer, or in other ways that do not affect the CPU usage of the DSP;

[0010] Step 2: Sample the A / B phase signal of the code disk by single frequency, double frequency or quadruple frequency to generate a pulse signal, and calculate the number of pulses in each sampling period and the number of clocks corresponding to the pulses;

[0011] Step 3, the DSP calculates or the host computer calculates and sends it to the DSP to calculate the speed compensation coefficient;

[0012] Step 4: Calculate the rotation speed according to the results obtained from steps 1 to 3.

[0013] Moreover, the specific implementation method of step 1 is:

[0014] M 2(0) =T A f c

[0015]

[0016] K2=[log2([K1 / 2]×2)]

[0017]

[0018] Among them, M 2(0) is the number of clock pulses in the sampling period, T A is the DSP sampling period of the control system, f c is the control system DSP clock frequency, K1, K2, K3 and K4 are coefficients, α is the multiplication sampling coefficient, P A is the number of lines on the code disk, n b is the rated speed of the motor, C1 is the total number of data bits, and C2 is the number of decimal places.

[0019] Moreover, the specific implementation method of step 2 is: using two counters, one counter records T A The number of pulses in a cycle is M1, at T A The output value is cleared after the end time; another counter records the number of clocks M2 between every two pulses. A The output value at the end time is cleared at the rising edge of the pulse. At the end of the k-1th cycle, M is taken from the counter. 2(k-1) ; At the end of the kth cycle, take M from the counter 1(k) 、M 2(k) , and define process quantities p1 and p2, where p2 is the number of clocks corresponding to p1 pulses:

[0020]

[0021] Moreover, the specific implementation method of step 3 is:

[0022]

[0023] Furthermore, the step 4 comprises the following steps:

[0024] Step 4.1, calculate the process quantity p1': shift p1 left by (K2+A2) bits to get p1';

[0025] Step 4.2: Calculate process quantity n' k :n' k =p1'×K3 / p2;

[0026] Step 4.3, calculate the speed n k :n' k Shift right by A2 to get the code disk speed n k .

[0027] The advantages and positive effects of the present invention are:

[0028] 1. The present invention calculates the required amount of speed measurement by calculating in the DSP initialization stage, or sending it to the DSP after calculation by the host computer, or other methods that do not affect the CPU usage rate of the DSP; according to the actual situation, the A / B phase signal of the code disk is sampled by one-fold, two-fold or four-fold frequency to generate a pulse signal, and the number of pulses in each sampling period and the number of clocks corresponding to the pulse are calculated; the speed compensation coefficient is calculated by the DSP, or the host computer calculates and sends it to the DSP, or other real-time calculation methods; the speed is calculated based on the comprehensive results. The present invention improves the code disk speed measurement calculation method, especially for the problem of slightly large calculation error of the fixed-point system, and proposes a method to reduce the relative error, which can reduce the calculation error of the fixed-point system, especially in the low-speed area. The calculated motor speed is accurate and has a small error. At the same time, the implementation scheme of the present invention is simple, the relative amount of calculation is small, the improvement effect is obvious, and the application effect is good.

[0029] 2. The present invention adopts the calculation method of "left shift first and then multiplication" in the process of speed calculation to reduce the load of DSP when calculating multiplication. A compensation coefficient scheme is proposed. The compensation coefficient is adaptive and decreases with the increase of motor speed, and in practice, only the left shift amount is increased. In the low speed area, the compensation coefficient can amplify the multiplier to reduce the calculation error; in the medium and high speed area, the coefficient gradually decreases until the amplification factor is 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of pulse signal frequency doubling sampling detection;

[0031] Figure 2This is a schematic diagram of the speed measurement principle of the M / T method;

[0032] Figure 3 This is a relative error result diagram of the speed calculation result before improvement in the embodiment of the present invention;

[0033] Figure 4 This is a diagram showing the relative error of the rotational speed calculation result after improvement according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described in detail below with reference to the accompanying drawings.

[0035] An improved method for calculating the fixed point of code disk speed measurement includes the following steps:

[0036] Step 1: Calculate the amount required for speed measurement during the DSP initialization phase, or after the host computer calculates and sends it to the DSP, or in other ways that do not affect the CPU usage of the DSP.

[0037] M 2(0) =T A f c

[0038]

[0039] K2=[log2([K1 / 2]×2)]

[0040]

[0041] Among them, M 2(0) is the number of clock pulses in the sampling period, T A is the DSP sampling period of the control system, f c is the control system DSP clock frequency, K1, K2, K3 and K4 are coefficients, α is the multiplication sampling coefficient, P A is the number of lines on the code disk, n b is the rated speed of the motor, C1 is the total number of data bits, and C2 is the number of decimal places.

[0042] Step 2: According to the actual situation, use single frequency, double frequency or quadruple frequency to sample the A / B phase signal of the code disk and generate a pulse signal.

[0043] Two counters are used, one counter records T A The number of pulses in a cycle is M1, at T A The output value is cleared after the end time; another counter records the number of clocks M2 between every two pulses. A The output value at the end time is cleared at the rising edge of the pulse. At the end of the k-1th cycle, M is taken from the counter. 2(k-1) ; At the end of the kth cycle, take M from the counter1(k) 、M 2(k) , and define process quantities p1 and p2, where p2 is the number of clocks corresponding to p1 pulses:

[0044]

[0045] Step 3: Calculate the speed compensation coefficient during the DSP calculation or the process in which the host computer calculates and sends it to the DSP.

[0046]

[0047] Step 4: Calculate the rotation speed according to the results obtained from steps 1 to 3.

[0048] Step 4.1, calculate the process quantity p1': shift p1 left by (K2+A2) bits to get p1';

[0049] Step 4.2: Calculate process quantity n' k :n' k =p1'×K3 / p2;

[0050] Step 4.3, calculate the speed n l :n' k Shift right by A2 to get the code disk speed n k .

[0051] According to the above-mentioned improved method for calculating the fixed point of code disk speed measurement, the effect of the present invention is verified by analyzing the principle and calculating the motor speed.

[0052] The speed measurement principle of the code disc:

[0053] The code disk uses A square wave, B square wave and Z square wave output forms, where A and B square waves are two square waves with a phase difference of 90° and a duty cycle of 0.5, and Z square wave emits one narrow pulse per mechanical cycle.

[0054] The encoder speed measurement adopts the frequency multiplication sampling technology, and the common methods include single frequency, double frequency and quadruple frequency. It is defined that single frequency samples the rising edge of A phase or B phase pulse, double frequency samples the rising edge and falling edge of A phase or B phase pulse, and quadruple frequency samples the rising edge and falling edge of A phase and B phase. Figure 1 As shown in Figure 1. Pulses are generated based on the frequency multiplication sampling results, and the motor speed is calculated based on the number of pulses and time.

[0055] Assume the clock frequency of the control system DSP is f c [Hz], the sampling period is T A [s], the rated speed of the motor is n b [rpm], the number of encoder lines (i.e. the number of A / B phase pulses per mechanical cycle) is P A[ppr], the frequency multiplication sampling factor is α (α=1,2,4).

[0056] Generate pulses based on the frequency multiplication sampling results. Use a counter to record T A The number of pulses in a cycle is M1, M1 at T A The end time is reset. Use another counter to record the number of clocks between each two pulses, M2. The time between each two pulses is M2 / f. c , M2 is cleared at the rising edge of the pulse. Among them, T d is the actual time of M1 pulses, T d Approximately T A And it is an integer multiple of M1.

[0057] like Figure 2 As shown, at the end of the k-1th cycle, M is taken from the counter 2(k-1) ; At the end of the kth cycle, take M from the counter 1(k) 、M 2(k) . Then calculate the approximate period T of the kth period d(k) for:

[0058] T d(k) =T A +ΔT k-1 -ΔT k =(T A f c +M 2(k-1) -M 2(k) / f c

[0059] Let M 2(0) =T A f c , code disk speed value n k The calculation is as shown in formula (1). The coefficient "60" is used to convert the speed from [rps] to [rpm].

[0060]

[0061] Fixed-point calculation error calculation:

[0062] The definition of the data structure in the computing system includes the sign bit, the integer part and the decimal part. Fixed-point numbers refer to numbers in which the position of the decimal point is fixed. Once the decimal position is determined, the Q value is calibrated. The data format in the computing system is defined as C1QC2, where C1 is the total number of data bits and C2 is the number of decimal places. Common data formats include 32Q22, 16Q14, etc. Taking the 16Q14 data format as an example, its representative data range is -2 to 1.9999; in the per-unit value calculation, the data range is -200% to 199.99%.

[0063] Fixed-point calculation is relatively faster and suitable for control systems with high response speed requirements. However, fixed-point calculation will cause a certain degree of data precision loss. The equivalent result of fixed-point multiplication is actually the result of multiplying the integer multiplicand by the integer multiplier and then shifting it to the right. When the result is discarded during the right shift, it causes multiplication calculation errors; the equivalent result of fixed-point division is actually the integer dividend divided by the integer divisor and then shifted to the left. The error mainly occurs when the dividend is small.

[0064] For example, in a fixed-point computing system, using the 16Q14 data format, calculate 1% × 10%. Then: 1% = 0.01 × 2 14 =163, 10% = 0.1 × 2 14 =1638, then 163×1638=266994, that is, 266994 / (2 14 ×2 14 )=0.099%. It can be seen that although the fixed-point calculation has a fast response speed, the calculation error is relatively large, especially when the multiplier or multiplicand is small, the calculation accuracy is obviously lost.

[0065] The calculation process of speed:

[0066] Define the data format in the computing system as C1QC2, where C1 is the total number of data bits and C2 is the number of decimal places. Define the control system DSP clock frequency as f c [Hz], the control system DSP sampling period is T A [s], the rated speed of the motor is n b [rpm], the number of lines on the encoder is P A [ppr], the frequency multiplication sampling factor is α (α=1,2,4).

[0067] Multiplier breakdown:

[0068] According to the principle of code disk speed measurement,

[0069]

[0070] In the control system, K1 is determined by the control parameters, motor parameters, etc. It remains unchanged during the operation of the motor and can be considered as a constant. Then equation (1) can be rewritten as:

[0071]

[0072] The main reasons for the large relative error in the fixed-point speed calculation are: ① There is an error in the fixed-point multiplication calculation of K1M1, especially when M1 is small; ② There is an error in the fixed-point division calculation (K1M1) / M2. Usually, the divisor M2 is large and the division calculation error is small. Therefore, only the calculation error of M1M1 needs to be considered.

[0073] In order to reduce the DSP computing load, and the K1 value is generally greater than 2, the multiplication of K1 adopts the step-by-step calculation method of "first left shift and then multiplication" in fixed-point calculation, that is, The number of left shifts is K2 and is an integer, and the multiplier is K3. Then we have formula (4), where “[]” is for rounding calculation:

[0074]

[0075] It should be noted that when calculating, "left shift first, then multiplication" should be performed. If the order is reversed, the average error of the calculation result will increase.

[0076] For example: motor rated speed n b =1500rpm, encoder line number P A =1024ppr, clock frequency f c =1MHz, 4x sampling mode, 16Q14 data format. According to formula (3), we can get: K1 = 9.77. According to formula (5), we can get: K2 = 3, K3 = 122.07%. Therefore, multiplying by K1 is decomposed into two steps of shifting M1 left by 3 bits and then multiplying by the coefficient 122.07%, which is equivalent to a one-step calculation of multiplying M1 by 9.77 in floating point calculation.

[0077] Supplementary coefficient calculation:

[0078] In order to solve the error caused by the rotation speed calculation, the present invention adopts a method of appropriately amplifying the input M1 and then reducing it by the same multiple after multiplication and division.

[0079] Define the amplification factor of M1 as A1. Since the smaller M1 is, the larger the error of K1M1 is, then the appropriate selection of A1 can reduce the error of A1K1M1. A1 should amplify M1 as much as possible on the basis of avoiding result overflow. As the motor speed increases, M1 becomes larger, and obviously A1 should be reduced; until the motor reaches the rated speed n b When A1=1, A1 should change with the speed and be inversely proportional to the speed (i.e. M1).

[0080] Design A1 to be an exponential factor of 2, that is, Where A2 is a natural number, which can avoid generating new multiplication and division errors and increasing the amount of calculation. According to the design idea of ​​A1, A1 should be ≥ 1, and If A is enlarged by one more time, there will be no overflow. in is the maximum value of C1 bit data. So:

[0081]

[0082] Due to T A With Td Close to, and according to formula (1), it can be derived:

[0083]

[0084] Within this range, A2 takes the maximum integer value.

[0085] make

[0086]

[0087] Similar to K1, K4 is determined by control parameters, motor parameters, etc. It remains unchanged during the operation of the motor and can be considered a constant. Then the integer A2 is:

[0088]

[0089] For example: Sampling period T A =400us, rated motor speed n b =1500rpm, encoder line number P A =1024ppr, clock frequency f c =1MHz, using 4 times sampling method, using 16Q14 data format. Then 1≤A1≤(32767 / (n k ×2 14 )). According to formula (5), we can get: K4 = 81.9175, and then according to formula (6), we can get A2, and then we can calculate the current encoder speed value n k .

[0090] Speed ​​calculation:

[0091] After completing the multiplier decomposition and coefficient calculation, the motor speed can be calculated. Define process quantities p1 and p2, where p2 is the number of clocks corresponding to p1 pulses:

[0092]

[0093] Substituting p1 and p2 into equation (3), and from the relationship between K1 and A1, we can obtain:

[0094]

[0095] According to formula (7), the steps for calculating the motor speed are as follows:

[0096] Calculate the process quantity p1': shift p1 left by (K2+A2) bits to get p1';

[0097] Calculate process quantity n' k :n' k =p1'×K3 / p2;

[0098] Calculate the speed n k:n' k Shift right by A2 bits to get the code disk speed n k .

[0099] According to the principle of encoder speed measurement, a table is used for comparative analysis. The encoder speed measurement error of the motor at different speeds is calculated under different rated speeds, encoder line numbers, clock frequencies, and sampling periods. The calculation results before improvement are as follows: Figure 3 As shown, after improvement Figure 4 shown.

[0100] The relative error of the speed calculated by this scheme is significantly reduced. min For example, after improving the algorithm, n min The average relative error of point speed calculation is reduced from -6.1% to -0.2%. Compared with before improvement, the relative error of speed calculation is significantly reduced after improvement, especially in low speed area. The improved method of fixed-point calculation of code disk speed measurement proposed by the present invention is simple to implement in software, does not increase the amount of additional calculation, and can reduce the calculation error of fixed-point system, especially in low speed area. This method has good effect in field application.

[0101] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. An improved method for fixed-point calculation of code disc speed measurement, characterized in that: The following steps are involved: Step 1: Calculate the amount required for speed measurement during the DSP initialization phase, or send it to the DSP after calculation by the host computer, or in other ways that do not affect the CPU usage of the DSP; Step 2: Sample the A / B phase signal of the code disk by single frequency, double frequency or quadruple frequency to generate a pulse signal, and calculate the number of pulses in each sampling period and the number of clocks corresponding to the pulses; Step 3: The DSP calculates or the host computer calculates and sends it to the DSP to calculate the speed compensation coefficient; Step 4: Calculate the encoder rotation speed based on the results obtained from steps 1 to 3.

2. The improved method for fixed-point calculation of code disc speed measurement according to claim 1 is characterized in that: The specific implementation method of step 1 is: M 2(0) =T A f c K2=[log2([K1 / 2]×2)] Among them, M 2(0) is the number of clock pulses in the sampling period, T A is the control system DSP sampling period, f c is the control system DSP clock frequency, K1, K2, K3 and K4 are coefficients, α is the multiplication sampling coefficient, P A is the number of lines on the code disk, n b is the rated speed of the motor, C1 is the total number of data bits, and C2 is the number of decimal places.

3. The improved method for fixed-point calculation of code disc speed measurement according to claim 2 is characterized in that: The specific implementation method of step 2 is: using two counters, one counter records T A The number of pulses in a cycle is M1, at T A The output value is cleared after the end time; another counter records the number of clocks M2 between every two pulses. A The output value at the end time is cleared at the rising edge of the pulse. At the end of the k-1th cycle, M is taken from the counter. 2(k-1) ; At the end of the kth cycle, take M from the counter 1(k) 、M 2(k) , and define process quantities p1 and p2, where p2 is the number of clocks corresponding to p1 pulses:

4. The improved method for calculating the fixed point of code disc speed measurement according to claim 3 is characterized in that: The specific implementation method of step 3 is:

5. The improved method for fixed-point calculation of code disc speed measurement according to claim 1 is characterized in that: The step 4 comprises the following steps: Step 4.1, calculate the process quantity p1': shift p1 left by (K2+A2) bits to get p1'; Step 4.2: Calculate process quantity n' k :n' k =p1'×K3 / p2; Step 4.3, calculate the speed n k :n' k Shift right by A2 to get the code disk speed n k .

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