Test structure and test method of phase change memory

Abstract

The embodiment of the invention discloses a test structure and a test method of a phase change memory. The test structure comprises a multi-layer stacked structure. Each layer of stacked structure comprises an array region and a redundant region; wherein the redundant region surrounds a part of the array region. The multiple layers of stacked structures are stacked in a staggered mode in the first direction. The projections of the array areas of each layer of stacked structure in the first direction coincide with each other.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a test structure and a test method for a phase change memory. Background Art

[0002] 3D PCM (three-dimensional phase change memory) is a memory with a three-dimensional structure based on stacking technology; in which the storage unit is composed of phase change material, and the conductivity difference exhibited by the phase change material when it transforms between crystalline and amorphous states is used to store data.

[0003] During the process development of 3D PCM, it is necessary to design a corresponding testkey (test structure) for testing (such as WAT or bench testing) to monitor the process and electrical properties, or to study the intrinsic characteristics of the memory (such as threshold voltage Vt).

[0004] However, as the number and density of stack layers of 3D PCM increase, the area occupied by a complete test structure gradually increases. For example, when designing TSK, if a complete multi-layer stack structure is directly designed and placed, it will occupy a larger area, thus affecting the space utilization of the wafer and the overall array efficiency. It can be seen that the test structure of 3D PCM needs to be further optimized to improve the space utilization of the wafer and the overall array efficiency. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a test structure and a test method for a phase change memory, which can improve the space utilization of the wafer and the overall array area efficiency.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] An embodiment of the present application provides a test structure of a phase change memory, comprising: a multi-layer stacking structure stacked in an offset manner along a first direction; each layer of the stacking structure comprises: an array area and a redundant area; wherein the redundant area surrounds part of the array area; and projections of the array area of ​​each layer of the stacking structure along the first direction overlap with each other.

[0008] In some embodiments of the present application, the projection of the array area along the first direction is a rectangle; and the projection of the redundant area along the first direction is an L-shape surrounding two adjacent sides of the rectangle.

[0009] In some embodiments of the present application, the projections of two adjacent layers of the stacked structure along the first direction are at a rotation angle of 90° or 180°.

[0010] In some embodiments of the present application, each layer of the stacked structure includes: a bit line layer and a word line layer; the bit line layer and the word line layer are respectively located on two opposite sides of each layer of the stacked structure along the first direction; wherein the bit line layer includes: a plurality of bit line regions; the word line layer includes: a plurality of word line regions; the plurality of word line regions all extend along the second direction, and two adjacent word line regions are staggered; the plurality of bit line regions all extend along the third direction, and two adjacent bit line regions are staggered; in each of the word line regions, a plurality of word lines extending along the second direction are arranged; in each of the bit line regions, a plurality of bit lines extending along the third direction are arranged; wherein the second direction and the third direction intersect; the second direction and the third direction are both perpendicular to the first direction.

[0011] In some embodiments of the present application, at least a portion of each of the bit line regions and at least a portion of each of the word line regions belong to the redundant region.

[0012] In some embodiments of the present application, the two bit lines respectively located in two adjacent layers of the stacked structure are connected in parallel to each other; or, the two word lines respectively located in two adjacent layers of the stacked structure are connected in parallel to each other.

[0013] In some embodiments of the present application, the two bit lines or the two word lines connected in parallel are in contact with each other along the first direction.

[0014] An embodiment of the present application also provides a phase change memory testing method for testing the test structure described in the above scheme; the testing method comprises: dividing the array area of ​​the test structure into a plurality of test areas; selecting a plurality of target test areas with different resistance values ​​in the plurality of test areas; in each of the target test areas, selecting at least one target bit line and target word line for testing to obtain the test result of the target device.

[0015] In some embodiments of the present application, the method of selecting at least one target bit line and at least one target word line for testing to obtain a test result of a target device includes: applying a constant voltage to the target bit line; applying an increasing voltage pulse to the target word line and testing the current on the target bit line; and determining a threshold voltage of the target device based on the current on the target bit line.

[0016] In some embodiments of the present application, the selecting of a plurality of target test areas with different resistance values ​​includes: selecting a test area located at a corner position of the array area as the target test area.

[0017] It is understandable that in the embodiment of the present application, the test structure is constructed by staggered stacking; in this way, the size of the array area is guaranteed and the size of the test structure as a whole is reduced. Furthermore, since the test structure is usually set in the cutting path on the wafer, reducing the size of the test structure can reduce the area ratio of the cutting path on the wafer; thus, the area ratio of the chip on the wafer can be increased, that is, the space utilization rate of the wafer and the overall array area efficiency are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A Schematic diagram 1 of a test structure of a phase change memory provided in an embodiment of the present application;

[0019] Figure 1B Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 2 ;

[0020] Figure 1C Schematic diagram 3 of the test structure of the phase change memory provided in the embodiment of the present application;

[0021] Figure 2 Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 4 ;

[0022] Figure 3A Schematic diagram 5 of the test structure of the phase change memory provided in the embodiment of the present application;

[0023] Figure 3B Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 6 ;

[0024] Figure 3C Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 7 ;

[0025] Figure 3D Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 8 ;

[0026] Figure 4 Schematic diagram of the test structure of the phase change memory provided in the embodiment of the present application Figure 9 ;

[0027] Figure 5A is a schematic diagram 10 of a test structure of a phase change memory provided in an embodiment of the present application;

[0028] Figure 5B 11 is a schematic diagram of a test structure of a phase change memory provided in an embodiment of the present application;

[0029] Figure 61 is a schematic diagram of an implementation flow of a phase change memory testing method provided in an embodiment of the present application;

[0030] Figure 7 The following is a schematic diagram of the implementation process of the phase change memory testing method provided in the embodiment of the present application. Figure 2 ;

[0031] Figure 8 1 is a schematic diagram of the effect of the phase change memory testing method provided in an embodiment of the present application;

[0032] Fig. 9 The effect of the phase change memory testing method provided by the embodiment of the present application is shown in FIG. Figure 2 . DETAILED DESCRIPTION

[0033] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0037] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. The units "root", "bar" or "individual" for transmission lines all represent the same meaning.

[0039] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0040] Figure 1A , Figure 1B and Figure 1C is an optional structural diagram of the test structure of the phase change memory in the embodiment of the present application. Figure 1A is a top view, Figure 1B is a side view, Figure 1C It is a three-dimensional stereogram.

[0041] refer to Figure 1A , Figure 1B and Figure 1C The test structure of the phase change memory includes: a multi-layer stacking structure S1-S4. Each layer of the stacking structure includes: an array area and a redundant area. The array area is Figure 1A and Figure 1C The area shown by the dotted box in the middle; the redundant area is the area outside the array area in each layer of the stacking structure.

[0042] In the present application, continue to refer to Figure 1A , Figure 1B and Figure 1C , the multi-layer stacked structures S1-S4 are stacked in a staggered manner along the first direction Z; at the same time, the projections of the array areas of each layer of the stacked structures along the first direction Z overlap with each other. In other words, the projections of the multi-layer stacked structures S1-S4 along the first direction Z do not completely overlap, and only the projections of the stacked multi-layer array areas along the first direction Z overlap with each other. Thus, the stacked multi-layer array areas can form an area for testing to measure the performance of the phase change memory.

[0043] In the present application examples, reference Figure 1A and Figure 1C In each stacked structure, the redundant area surrounds part of the array area, so that the redundant area can protect the array area. For example, in the cutting process in integrated circuit manufacturing, the redundant area can protect the array area and prevent the array area from being damaged by cutting, thereby ensuring that the test can be carried out smoothly.

[0044] It is understandable that a test structure of a phase change memory is proposed in the embodiment of the present application, the test structure is optimized, and the test structure is constructed by staggered stacking; in this way, the size of the array area is guaranteed and the size of the test structure as a whole is reduced. Compared with the existing test structure, in the embodiment of the present application, the length and width of the test structure can be reduced from 500-600um to 100-300um.

[0045] Furthermore, since the test structure is usually set on the cutting path on the wafer or in an independent special test area on the wafer, reducing the size of the test structure can reduce the area ratio of the cutting path or the special test area on the wafer; thereby, the area ratio of the chip on the wafer can be increased, that is, the space utilization rate of the wafer and the overall array area efficiency are improved.

[0046] In some embodiments of the present application, reference Figure 1A and Figure 1C , the projection of each stacked structure along the first direction Z is a rectangle. The projection of the array area along the first direction Z is a rectangle; the projection of the redundant area along the first direction Z is an L-shape surrounding two adjacent sides of the rectangle.

[0047] It should be noted that in Figure 1A and Figure 1C In the figure, due to the blocking relationship, only the array area of ​​the stacking structure S4 located on the uppermost layer is shown; correspondingly, the array areas of the stacking structures S1 to S3 are located directly below the array area of ​​the stacking structure S4 and are blocked and not shown.

[0048] It can be understood that in each stacking structure, a rectangular array area and an L-shaped redundant area are divided, so that the redundant area surrounds part of the array area. In this way, in a multi-layer stacking structure using staggered stacking, the area occupied by the projection of all redundant areas can be reduced as much as possible, thereby reducing the overall size of the test structure as much as possible while ensuring the size of the array area.

[0049] In some embodiments of the present application, reference Figure 1C , the projections of two adjacent stacked structures along the first direction Z are rotated at an angle of 90° or 180°. For example, taking the center point of the projections of the array area of ​​the stacked structures S1 to S4 as the rotation center, the projection of the stacked structure S1 can be rotated 90° clockwise to obtain the projection of the stacked structure S2, the projection of the stacked structure S2 can be rotated 180° clockwise to obtain the projection of the stacked structure S3, and the projection of the stacked structure S3 can be rotated 90° counterclockwise to obtain the projection of the stacked structure S4.

[0050] It can be understood that in each stacking structure, the redundant area surrounds part of the array area, and then, when constructing a multi-layer stacking structure, two adjacent stacking structures are rotated at a certain angle. In this way, on the one hand, the stability of the multi-layer stacking structure with misaligned stacking is ensured, and the collapse of the multi-layer stacking structure is avoided; on the other hand, a circle of redundant area is formed around the array area of ​​the multi-layer stacking structure, so that the redundant area can fully protect the array area, thereby ensuring that the test can be carried out smoothly.

[0051] In some embodiments of the present application, each stacked structure includes: a bit line layer and a word line layer. The bit line layer and the word line layer are respectively located on two opposite sides of each stacked structure along a first direction.

[0052] Figure 2 The bit lines BL, word lines WL and phase change memory PCM in each stacked structure are shown. Figure 2 In a phase change memory, the bit line BL and the word line WL are located in two layers (bit line layer and word line layer). Furthermore, the bit line BL and the word line WL extend in two directions respectively; the phase change memory PCM is set at the intersection of the bit line BL and the word line WL. By changing the voltage of the bit line BL and the word line WL, the phase change material of the phase change memory PCM can be switched between the crystalline state and the amorphous state, thereby storing data "1" or "0".

[0053] In some embodiments of the present application, the bit line layer includes: a plurality of bit line regions; and the word line layer includes: a plurality of word line regions.

[0054] Figure 3A , Figure 3B , Figure 3C and Figure 3D The stacking structures S1 to S4 are shown respectively. Figure 3A Take this as an example to illustrate: Figure 3B , Figure 3C and Figure 3D You can refer to Figure 3A To understand.

[0055] refer to Figure 3A , multiple word line regions extend along the second direction X, and two adjacent word line regions are staggered; multiple bit line regions extend along the third direction Y, and two adjacent bit line regions are staggered. The second direction X and the third direction Y intersect; and the second direction X and the third direction Y are both perpendicular to the first direction Z.

[0056] Furthermore, in each word line region, a plurality of word lines WL extending along the second direction X are provided; and in each bit line region, a plurality of bit lines BL extending along the third direction Y are provided. Figure 3A In the embodiment, two word lines WL are exemplarily provided in each word line region, and two bit lines BL are exemplarily provided in each bit line region, which is not a limitation to the present application.

[0057] It can be understood that two adjacent word line regions are arranged in a staggered manner, and two adjacent bit line regions are arranged in a staggered manner. In this way, on the one hand, sufficient storage arrays are ensured to be formed in the array area; on the other hand, contact structures can be formed in the gaps of the staggered arrangement. Thus, the overall size of the test structure is reduced as much as possible while ensuring the performance of the test structure.

[0058] In some embodiments of the present application, reference Figure 3A At least part of each bit line region and at least part of each word line region belong to the redundant region. That is, at least part of each bit line region and each word line region is located outside the array region. In this way, the partial region outside the array region can form a contact structure, thereby ensuring electrical connection between word lines and bit lines in different stacking structures.

[0059] Figure 3A , Figure 3B , Figure 3C and Figure 3D After the stacking structures S1 to S4 are stacked in a staggered manner along the first direction Z, the structure formed is as follows Figure 4 shown.

[0060] refer to Figure 4 , the projections of the array area of ​​each stacked structure along the first direction Z overlap with each other. A circle of redundant area is formed around the array area of ​​the multi-layer stacked structure.

[0061] In some embodiments of the present application, the bit line regions of two adjacent stacked structures are close to each other, and at the same time, the two bit lines respectively located in the two adjacent stacked structures are connected in parallel. Alternatively, the word line regions of two adjacent stacked structures are close to each other, and at the same time, the two word lines respectively located in the two adjacent stacked structures are connected in parallel. Among them, the two bit lines or two word lines connected in parallel will have the same voltage and transmit the same electrical signal.

[0062] In some embodiments of the present application, two bit lines connected in parallel contact with each other along a first direction Z. Two word lines connected in parallel contact with each other along the first direction Z.

[0063] refer to Figure 5A , the word lines WL1 and WL2 are respectively located in two adjacent stacked structures, and the word lines WL1 and WL2 are in contact with each other and thus connected in parallel.

[0064] Accordingly, reference Figure 5B The bit lines BL1 and BL2 are respectively located in two adjacent stacked structures, and the bit lines BL1 and BL2 are in contact with each other and thus connected in parallel.

[0065] Figure 6 FIG. 1 is an optional flow chart of a method for testing a phase change memory provided in an embodiment of the present application, and the method can be used to test the test structure of the above-mentioned embodiment. Figure 6 As shown, the testing method includes steps S101 to S103, which will be described in conjunction with each step.

[0066] S101, dividing an array area of ​​a test structure into a plurality of test areas.

[0067] In the present application examples, reference Figure 8 The array area of ​​the test structure is divided into a plurality of test areas, each of which is marked with a resistance value. The resistance value can be obtained by measuring the resistance of a bit line or a word line.

[0068] S102 . Selecting a plurality of target test areas with different resistance values ​​from among the multiple test areas.

[0069] In the embodiment of the present application, a plurality of target test areas with different resistance values ​​may be selected from the divided test areas. For example, 3 to 8 target test areas may be selected for testing. Figure 8 The five test areas circled by dotted lines are selected as target test areas.

[0070] S103 . In each target test area, select at least one target bit line and at least one target word line for testing to obtain a test result of the target device.

[0071] In the embodiment of the present application, after selecting a plurality of target test areas, each target test area can be tested, wherein the test can be performed through leads (including bit lines and word lines) or through PADs (pads).

[0072] like Fig. 9 In the example shown, in each target test area, two target WLs (word lines) and two target BLs (bit lines) are selected for testing, so there are 4 target devices at the intersection of the two target WLs and the two target BLs. Furthermore, if 5 target test areas are selected, then for each layer of the test structure, test results of 20 target devices can be obtained.

[0073] It should be noted that for a multi-layer stacked structure, when testing one layer of the stacked structure, the remaining layers of the stacked structure can be used as auxiliary layers (dummy). The auxiliary layers do not affect the test results. For example, when testing the stacked structure S1, the stacked structures S2 to S4 are used as auxiliary layers, and so on.

[0074] In some embodiments of the present application, Figure 7 Steps S201 to S203 are shown to achieve Figure 6 Step S103 shown will be described in conjunction with each step.

[0075] S201 , applying a constant voltage to a target bit line.

[0076] S202, applying an increasing voltage pulse on the target word line, and testing the current on the target bit line.

[0077] S203 : Determine a threshold voltage of a target device based on the current on the target bit line.

[0078] In the embodiment of the present application, each target device can be tested in turn by selecting different target WL / target BL. For each target device, a constant voltage (e.g. -2 to -3V) can be applied to the target BL; then, an increasing voltage pulse is applied to the target WL, for example, the starting voltage is 0V, the ending voltage is 4 to 5V, the increasing step is 0.1V, and the current limit is 1e-4 to 1.5e-4A; at the same time, the current on the target BL is measured. If the voltage pulse on the target WL increases by one level, resulting in the current on the corresponding target BL increasing by 10 times and greater than 1e-5, it can be judged that the voltage before the increase is the threshold voltage Vt.

[0079] It should be noted that after the threshold voltage Vt_Forming is tested, the phase change memory device will be placed in the Set state, and the threshold voltage Vt_Set can be tested using the same method as steps S201 to S203.

[0080] It should also be noted that applying a reset voltage pulse can operate the phase change memory device to the Reset state. In order to ensure that different devices can be fully placed in the Reset state, a pulse operation of 8-9V and 50-60ns can be used several times (such as five times), and then the threshold voltage Vt_Reset can be tested using the same method as steps S201-S203.

[0081] In some embodiments of the present application, step S301 can be used to implement Figure 6 The step S102 shown will be explained in conjunction with each step.

[0082] S301 , selecting a test area located at a corner of an array area as a target test area.

[0083] In the present application examples, reference Figure 8 , four test areas located at the corners of the array area can be selected as target test areas, and their resistance values ​​are 13, 21, 34 and 42 respectively.

[0084] It can be understood that by selecting the test area located at the corner of the array area as the target test area, it can be ensured that the test can cover a larger range, thereby making the test result more comprehensive.

[0085] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0086] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0087] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A test structure of a phase change memory, characterized in that: include: A multi-layer stacked structure staggered along a first direction; Each layer of the stacked structure includes: an array area and a redundant area; wherein the redundant area surrounds part of the array area; Projections of the array areas of each layer of the stacked structure along the first direction overlap with each other.

2. The phase change memory test structure according to claim 1, characterized in that: The projection of the array area along the first direction is a rectangle; the projection of the redundant area along the first direction is an L-shape surrounding two adjacent sides of the rectangle.

3. The phase change memory test structure according to claim 1, characterized in that: The projections of two adjacent layers of the stacked structure along the first direction are at a rotation angle of 90° or 180°.

4. The phase change memory test structure according to claim 1, characterized in that: Each layer of the stacked structure comprises: a bit line layer and a word line layer; the bit line layer and the word line layer are respectively located on two opposite sides of each layer of the stacked structure along the first direction; Wherein, the bit line layer includes: a plurality of bit line regions; the word line layer includes: a plurality of word line regions; The plurality of word line regions extend along the second direction, and two adjacent word line regions are arranged in a staggered manner; the plurality of bit line regions extend along the third direction, and two adjacent bit line regions are arranged in a staggered manner; In each of the word line regions, a plurality of word lines extending along the second direction are arranged; in each of the bit line regions, a plurality of bit lines extending along the third direction are arranged; The second direction and the third direction intersect; the second direction and the third direction are both perpendicular to the first direction.

5. The test structure of the phase change memory according to claim 4, characterized in that: At least a portion of each of the bit line regions and at least a portion of each of the word line regions belong to the redundant region.

6. The test structure of the phase change memory according to claim 4, characterized in that: The two bit lines respectively located in two adjacent layers of the stacked structure are connected in parallel to each other; or the two word lines respectively located in two adjacent layers of the stacked structure are connected in parallel to each other.

7. The test structure of the phase change memory according to claim 6, characterized in that: The two bit lines or the two word lines connected in parallel are in contact with each other along the first direction.

8. A method for testing a phase change memory, characterized in that: Used to test the test structure according to any one of claims 1 to 7; the test method comprises: dividing the array area of ​​the test structure into a plurality of test areas; Among the plurality of test areas, selecting a plurality of target test areas with different resistance values; In each of the target test areas, at least one target bit line and at least one target word line are selected for testing to obtain a test result of the target device.

9. The method for testing a phase change memory according to claim 8, characterized in that: The step of selecting at least one target bit line and target word line for testing to obtain a test result of the target device includes: applying a constant voltage to the target bit line; applying an increasing voltage pulse on the target word line and testing the current on the target bit line; Based on the current on the target bit line, a threshold voltage of the target device is determined.

10. The method for testing a phase change memory according to claim 8, characterized in that: The method of selecting a plurality of target test areas with different resistance values ​​includes: A test area located at a corner of the array area is selected as the target test area.

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