Field effect transistor and preparation method thereof

Abstract

The invention provides a field effect transistor and a preparation method thereof. In the preparation method, batch deposition of the gate electrode material layer is carried out by using a furnace tube process, so that the production efficiency of a product is improved; and for a gate electrode material layer formed on the second surface of the substrate due to a furnace tube process, the substrate structure can be placed in an oxygen-containing gas atmosphere for annealing treatment in a subsequent annealing process, so that the exposed surface of the gate electrode material layer is oxidized to form an oxidation barrier layer; therefore, ions in the gate electrode material layer can be prevented from being separated out by using the oxidation barrier layer, the influence of the separated ions on the quality of a product is avoided, the pollution to processing equipment can be reduced, and the maintenance frequency of the equipment is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field effect transistor and a preparation method thereof. Background Art

[0002] With the continuous development of modern microelectronics technology, field effect transistors have been widely used in most digital circuits and analog circuits. At present, field effect transistors mainly include planar field effect transistors and trench field effect transistors. Among them, trench field effect transistors are widely used in many fields due to their high integration, low on-resistance, fast switching speed and other characteristics.

[0003] With the continuous changes and development and innovation in the application environment of field effect transistors, higher requirements are placed on their preparation process and device performance. Therefore, improving product production efficiency and achieving better device performance has become a common pursuit in the industry. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a field effect transistor so as to optimize the device performance on the basis of improving the production efficiency of the product.

[0005] To this end, the present invention provides a method for preparing a field effect transistor, comprising: providing a substrate, the substrate having a first surface and a second surface relative to each other; depositing a doped gate electrode material layer using a furnace tube process, the gate electrode material layer being formed on the first surface and the second surface of the substrate; performing an etching process to remove a portion of the gate electrode material layer located on the first surface of the substrate, and retaining a portion of the gate electrode material layer to form a gate electrode; and performing an ion implantation process and an annealing process to form an ion doping region in the substrate on the side of the gate electrode, wherein the annealing process comprises performing an annealing treatment in an oxygen-containing gas atmosphere to oxidize the exposed surface of the gate electrode material layer located on the second surface of the substrate.

[0006] Optionally, before depositing the doped gate electrode material layer, the first surface of the substrate is also etched to form a gate trench in the substrate; and when depositing the doped gate electrode material layer, the gate electrode material layer fills the gate trench, and after performing the etching process, the gate electrode material layer located in the gate trench is retained to form the gate electrode.

[0007] Optionally, the method for preparing the gate trench includes: forming a mask layer on the first surface of the substrate, and etching the first surface of the substrate using the mask layer as a mask to form the gate trench; and, removing the mask layer and modifying the top angle morphology of the gate trench using an etching process to modify the top angle of the gate trench into an arc-shaped top angle.

[0008] Optionally, after forming the gate trench and before depositing the gate electrode material layer, the method further includes: forming a gate dielectric layer on the substrate, wherein the gate dielectric layer is formed on the inner wall of the gate trench and on the first surface of the substrate.

[0009] Optionally, after performing the etching process to form the gate electrode and before performing the ion implantation process, the method further includes: thinning the gate dielectric layer on the first surface of the substrate, wherein the thickness of the gate dielectric layer may be thinned to less than or equal to 250 angstroms.

[0010] Optionally, after performing an etching process to form the gate electrode, the gate dielectric layer outside the gate trench is exposed; and during the annealing process, the exposed gate dielectric layer is also oxidized and repaired.

[0011] Optionally, performing an ion implantation process and an annealing process to form an ion doped region includes: performing a first ion implantation process and a first thermal annealing process to form a well region in the substrate on the side of the gate electrode, and performing the first thermal annealing process in an oxygen-containing gas atmosphere.

[0012] Optionally, performing an ion implantation process and an annealing process to form an ion doped region includes: performing a second ion implantation process and a second thermal annealing process to form a source doped region in the substrate on the side of the gate electrode, and performing the second thermal annealing process in an oxygen-containing gas atmosphere.

[0013] Optionally, the methods for performing the first thermal annealing process and the second thermal annealing process include: placing the substrate structure in a thermal annealing process chamber; entering a temperature rise phase to increase the temperature in the process chamber, and introducing oxygen during the temperature rise phase to oxidize the exposed surface of the gate electrode material layer located on the second surface of the substrate; and entering a constant temperature phase to complete the thermal annealing treatment.

[0014] Optionally, the method of performing the first thermal annealing process and the second thermal annealing process further includes: after introducing oxygen for a predetermined time, introducing nitrogen into the process chamber.

[0015] The present invention also provides a field effect transistor, comprising: a substrate having a first surface and a second surface relative to each other; a gate electrode formed on the first surface of the substrate; an ion doping region formed in the substrate on the side of the gate electrode; and a gate electrode material layer formed on the second surface of the substrate, and the surface of the gate electrode material layer is also oxidized to form an oxidation blocking layer.

[0016] Optionally, a gate trench is formed in the substrate, the gate trench is recessed inward from the first surface of the substrate, and the gate electrode is formed in the gate trench; and the top angle of the gate channel is an arc-shaped top angle.

[0017] Optionally, a gate dielectric layer is further included, wherein the gate dielectric layer is formed on the inner wall of the gate trench and covers the arc-shaped top corner of the gate channel.

[0018] In the method for preparing the field effect transistor provided by the present invention, batch film layer deposition (including batch deposition of gate electrode material layer) can be realized by using the furnace tube process, which greatly improves the production efficiency of the product; and, for the gate electrode material layer formed on the second surface of the substrate due to the furnace tube process, the substrate structure can be placed in an oxygen-containing gas atmosphere for annealing in the subsequent annealing process, so that the exposed surface of the gate electrode material layer on the second surface of the substrate is oxidized to form an oxidation barrier layer, so that the oxidation barrier layer can be used to block the ion precipitation (for example, phosphorus precipitation) in the gate electrode material layer. In this way, not only can the precipitated ions be prevented from affecting the quality of the product, but also the pollution to the processing equipment can be reduced, the maintenance frequency of the equipment can be reduced, and at the same time, it can prevent the impact on other processed substrates and improve the yield of the product.

[0019] Furthermore, by placing the substrate structure in an oxygen-containing gas atmosphere for annealing, it is also helpful to repair the damage to the gate dielectric layer caused by processes such as ion implantation, improve the film quality of the gate dielectric layer (for example, the film density of the gate dielectric layer can be improved), ensure effective isolation between the gate electrode and the ion-doped region on its side, and reduce leakage current between the gate and the source. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic flow chart of a method for manufacturing a field effect transistor in one embodiment of the present invention.

[0021] Figure 2-Figure 10 FIG. 1 is a schematic diagram of the structure of a field effect transistor in an embodiment of the present invention during its preparation process.

[0022] The reference numerals are as follows:

[0023] 100-substrate;

[0024] 110 - base;

[0025] 120-epitaxial layer;

[0026] 200-mask layer;

[0027] 310-gate trench;

[0028] 311 - top angle of the gate trench;

[0029] 320-gate dielectric layer;

[0030] 330-gate electrode;

[0031] 330a / 330b-gate electrode material layer;

[0032] 410-well region;

[0033] 420-source doping region;

[0034] 500-Oxidation barrier layer. DETAILED DESCRIPTION

[0035] As described in the background art, in the semiconductor field, it is generally desired to improve the production efficiency of semiconductor devices and achieve better device performance. For example, the preparation process of a field effect transistor generally includes forming a gate electrode and a source doping region and a drain doping region located on both sides of the gate electrode, wherein a gate electrode material layer for forming the gate electrode can be deposited by a furnace tube process, so that the gate electrode material layer can be deposited on multiple substrates at the same time in the same deposition process, thereby greatly improving the production efficiency of the product.

[0036] However, when the furnace tube process is used, a gate electrode material layer will be deposited on both the front and back sides of the substrate. The gate electrode material layer is specifically a doped gate electrode material layer, wherein the gate electrode material layer located on the front side of the substrate can be etched to form a gate electrode, while the gate electrode material layer located on the back side of the substrate will at least be retained in several consecutive preparation processes. As for the gate electrode material layer on the back side, it is prone to the risk of ion precipitation in subsequent processes (for example, the doped ions in the gate electrode material layer are prone to diffuse and precipitate in the subsequent high-temperature process), and ion precipitation will not only affect the yield of the device, but may even cause the precipitated ions to contaminate the processing equipment, increase the number of machine maintenance times, and affect the production efficiency of the product.

[0037] To this end, an embodiment of the present invention provides a method for preparing a field effect transistor, which can be specifically referred to Figure 1 As shown, it specifically includes the following steps.

[0038] In step S100 , a substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other.

[0039] Step S200: depositing a doped gate electrode material layer on the substrate by using a furnace tube process, wherein the gate electrode material layer is formed on a first surface and a second surface of the substrate.

[0040] Step S300 , performing an etching process to remove a portion of the gate electrode material layer located on the first surface of the substrate, and retaining a portion of the gate electrode material layer to form a gate electrode.

[0041] Step S400, performing an ion implantation process and an annealing process to form an ion doped region in the substrate on the side of the gate electrode, wherein the annealing process includes performing an annealing treatment in an oxygen-containing gas atmosphere to oxidize the exposed surface of the gate electrode material layer on the second surface of the substrate.

[0042] That is, in the method for preparing a field effect transistor provided in one embodiment of the present invention, oxygen-containing gas is also introduced during the annealing process of the ion-doped region, so that the substrate structure is annealed in an oxygen-containing gas atmosphere. On the one hand, the activation and uniform diffusion of the doped ions in the ion-doped region can be achieved; on the other hand, the exposed surface of the gate electrode material layer located on the second surface of the substrate can be oxidized, thereby forming an oxidation barrier layer on the surface of the exposed gate electrode material layer, effectively blocking the precipitation of ions in the gate electrode material layer, avoiding the precipitated ions from affecting the yield of the product, and preventing the precipitated ions from contaminating the processing equipment.

[0043] The field effect transistor and the method for preparing the same proposed by the present invention are further described in detail below in combination with the specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as "above" another element will now be below the element.

[0044] Combine the following Figure 1 as well as Figure 2-Figure 10 , a method for preparing a field effect transistor in an embodiment of the present invention is described, wherein Figure 2-Figure 10 FIG. 1 is a schematic diagram of the structure of a field effect transistor in an embodiment of the present invention during its preparation process.

[0045] In step S100, refer to Figure 2 As shown, a substrate 100 is provided, and the substrate 100 has a first surface and a second surface opposite to each other, wherein the first surface is, for example, the front side of the substrate 100, and the second surface is, for example, the back side of the substrate 100. Further, the substrate 100 may specifically include a base 110 and an epitaxial layer 120 epitaxially grown on the base 110, wherein the surface of the base 110 facing away from the epitaxial layer 120 is the second surface, and the surface of the epitaxial layer 120 facing away from the base 110 is the first surface. In the subsequent process, components such as gate electrodes will be prepared on the epitaxial layer 120 of the substrate 100.

[0046] In this embodiment, the prepared field effect transistor is a trench field effect transistor (Trench MOSFET) as an example for description, while in other examples, the field effect transistor may also be a planar field effect transistor.

[0047] Continue to refer Figure 2 As shown, for the trench field effect transistor, its preparation method also includes: forming a gate trench 310 in the substrate 100, the gate trench 310 is used to accommodate the gate electrode formed subsequently, and in this embodiment, the gate trench 310 is specifically formed in the epitaxial layer 120. Among them, the method for forming the gate trench 310, for example, includes: forming a mask layer 200 on the first surface of the substrate 100 (the mask layer 200 is specifically formed on the surface of the epitaxial layer 120), and the mask layer 200 defines the pattern of the gate trench; then, etching the first surface of the substrate 100 with the mask layer 200 as a mask to form a gate trench 310 recessed inward from the first surface of the substrate 100. In a specific example, the mask layer 200 can be a mask stack, which includes at least two film layers stacked from bottom to top, for example, including a silicon oxide layer formed on the epitaxial layer 120 and a silicon nitride layer or a polysilicon layer formed on the silicon oxide layer.

[0048] Next reference Figure 3 and Figure 4 As shown, in a further solution, after etching the epitaxial layer 120 to form the gate trench 310, the mask layer 200 is removed to expose the substrate portion around the gate trench 310. Afterwards, the top angle morphology of the gate trench 310 can be modified by an etching process to modify the top angle 311 of the gate trench 310 into a curved top angle.

[0049] It should be noted that, for trench field effect transistors, when the top angle of the trench presents a sharp angle morphology, it is easy to cause various risks, for example: when performing the etching process, the sharp angle position at the top of the trench is more susceptible to etching attack, which leads to the film layer formed at the sharp angle position being easily consumed; and, in the ion implantation process, the sharp angle position at the top of the trench is also susceptible to ion bombardment, so that the film layer at the sharp angle position is damaged. In this regard, an existing improvement scheme is: widening the opening of the mask layer to expose the top angle of the trench, and then etching the top angle of the trench, at which time the top angle of the trench will be etched into a step shape, thereby removing the sharp angle morphology. Different from the existing improvement scheme, in this embodiment, the mask layer 200 is preferentially removed, so that the surrounding substrate of the gate trench 310 is completely exposed, and at this time, the top angle 310 of the gate trench 310 can be modified into an arc-shaped top angle by using an etching process (for example, a dry etching process) to achieve the purpose of morphology modification. Compared with the prior art of etching the top corner of the trench into a step shape, in the present embodiment, the top corner 311 of the gate trench 310 is modified into an arc-shaped top corner, which is more conducive to adjusting the morphology of the film layer formed on the arc-shaped top corner, so that the formed film layer is smoother, and the formed film layer will not form a step structure because it conforms to the step-shaped top corner, thereby better mitigating the attack on the film layer at the top corner of the trench in the subsequent process. For example, for the gate dielectric layer formed subsequently, the quality of the gate dielectric layer at the top corner of the trench can be improved, which can play a better isolation role and improve the problem of gate-source leakage current of the device.

[0050] In an optional solution, after etching the substrate 100 to form the gate trench 310, it also includes: performing a thermal oxidation process to form a sacrificial oxide layer (not shown in the figure) on the inner wall of the gate trench 310; then, performing an etching process (for example, a wet etching process) to remove the sacrificial oxide layer. Specifically, when the etching process is performed on the substrate 100, etching damage is often caused on the exposed surface (including: etching damage is easily generated on the inner wall of the gate trench 310). Based on this, by forming a sacrificial oxide layer and removing the sacrificial oxide layer, the etching damage on the inner surface of the gate trench 310 is repaired, thereby improving the performance of the prepared device.

[0051] Next reference Figure 5 As shown, after modifying the top angle 311 of the gate trench 310, the method further includes: forming a gate dielectric layer 320 on the substrate 100, and the gate dielectric layer 320 can be formed by, for example, an oxidation process or a deposition process. In this embodiment, the gate dielectric layer 320 is formed on the inner wall of the gate trench 310 and on the first surface of the substrate 100, and in this step, the thickness of the gate dielectric layer 320 on the inner wall of the gate trench 310 is consistent with or nearly consistent with the thickness of the gate dielectric layer 320 on the first surface of the substrate 100.

[0052] In step S200, refer to Figure 6 As shown, a doped gate electrode material layer is deposited on the substrate 100 using a furnace process, and the gate electrode material layer is formed on the first surface and the second surface of the substrate 100. That is, the formed gate electrode material layer includes: a gate electrode material layer 330a located on the first surface of the substrate and a gate electrode material layer 330b located on the second surface of the substrate.

[0053] In a specific example, the material of the gate electrode material layer includes, for example, polysilicon; and the in-situ doped gate electrode material layer can be deposited using a furnace tube process. The doping type of the gate electrode material layer can be adjusted accordingly according to the type of transistor to be formed. For example, when an N-type transistor needs to be formed, an N-doped gate electrode material layer (for example, an N-doped polysilicon layer) can be formed; conversely, when a P-type transistor needs to be formed, a P-doped gate electrode material layer (for example, a P-doped polysilicon layer) can be formed. In this embodiment, the formation of an N-type field effect transistor is used as an example for explanation. At this time, the gate electrode material layer formed is doped with N-type ions, wherein the N-type ions may specifically include phosphorus ions, nitrogen ions, or arsenic ions.

[0054] Furthermore, the furnace tube process can also be used to deposit gate electrode material layers on multiple substrates at the same time, greatly improving the production efficiency of the product. Specifically, the furnace tube device can be provided with a carrying device (such as a wafer boat for carrying wafers), which can carry multiple substrate structures at the same time, so that thin film deposition can be performed on multiple substrates at the same time in one deposition process, achieving the purpose of batch thin film deposition.

[0055] In addition, when the gate electrode material layer is deposited by the furnace process, the gate material layer is deposited on the first surface of the substrate 100 and the second surface of the substrate 100 at the same time. In this embodiment, an N-doped gate electrode material layer 330a is formed on the first surface of the substrate 100, and an N-doped gate electrode material layer 330b is formed on the second surface of the substrate 100. The gate electrode material layer 330a on the first surface of the substrate will be processed to form a gate electrode in a subsequent process, while the gate electrode material layer 330b on the second surface of the substrate will be retained at least in several consecutive preparation processes.

[0056] Continue to refer Figure 6 As shown, for the trench field effect transistor, the gate electrode material layer also fills the gate trench 310, and the gate electrode material layer located in the gate trench 310 will continue to be retained in the subsequent process to form the gate electrode, and the details can be referred to step S300.

[0057] In step S300, refer to Figure 7As shown, the gate electrode material layer 330a located on the first surface of the substrate 100 is etched to remove a portion of the gate electrode material layer located on the first surface of the substrate, and a portion of the gate electrode material layer is retained to form the gate electrode 330. In a specific example, the gate electrode material layer 330a can be etched by a dry etching process to improve the etching accuracy of the gate electrode 330.

[0058] In this embodiment, the gate electrode material layer 330a is etched to remove the gate electrode material layer outside the gate trench 310, and the gate electrode material layer inside the gate trench 310 is retained to form the gate electrode 330. In addition, as described above, the top corner 311 of the gate trench 310 is modified to be an arc-shaped top corner, which correspondingly makes the morphology of the gate dielectric layer 320 located at the top corner 311 more gentle, so that in the etching process for the gate electrode material layer 330a, it is helpful to reduce the etching attack on the gate dielectric layer 320 at the top corner 311, and avoid the gate dielectric layer 320 at the top corner 311 from being consumed in large quantities.

[0059] For further details, please refer to Figure 8 As shown, after etching the gate electrode material layer 330a, the gate dielectric layer 320 located on the first surface of the substrate outside the gate trench 310 is exposed. And, after exposing the gate dielectric layer 320 on the first surface of the substrate, it also includes: thinning the thickness of the exposed gate dielectric layer 320 located on the first surface of the substrate to facilitate the subsequent ion implantation process. In this embodiment, the thickness of the gate dielectric layer 320 can be thinned by the back etching process, and the thinning amount of the gate dielectric layer 320 can be minimized while satisfying the process conditions of the subsequent ion implantation. For example, the thinning thickness of the gate dielectric layer 320 can be controlled to be 200 angstroms-300 angstroms, and even the thinning thickness of the gate dielectric layer 320 can be made less than or equal to 250 angstroms (for example, 250 angstroms-200 angstroms). That is, by reducing the etching amount of the gate dielectric layer 320 (i.e., reducing the thinning thickness), the drilling amount of the gate dielectric layer 320 at the top corner of the gate trench 310 can be reduced, further ensuring the thickness of the gate dielectric layer 320 at the top corner of the trench, thereby improving the gate-source leakage problem of the device.

[0060] In step S400, refer to Fig. 9 As shown, an ion implantation process and an annealing process are performed to form an ion doped region in the substrate 100 on the side of the gate electrode 330. The annealing process includes performing an annealing process in an oxygen-containing gas atmosphere to oxidize the exposed surface of the gate electrode material layer 330b located on the second surface of the substrate, thereby forming an oxidation blocking layer 500 on the exposed surface of the gate electrode material layer 330b.

[0061] Among them, performing an ion implantation process and an annealing process to form an ion doped region may specifically include: performing a first ion implantation process and a first thermal annealing process to form a well region 410 in the substrate 100 on the side of the gate electrode, and the doping type of the well region 410 is opposite to the doping type of the gate electrode 330. For example, the gate electrode 330 in this embodiment is N-type doped, and the well region 410 is specifically P-type doped, so the first ion implantation process is P-type ion implantation. And, through the first thermal annealing process, the implanted ions are uniformly diffused to a predetermined range, and the implanted doped ions are activated, thereby forming the well region 410.

[0062] Furthermore, a first thermal annealing process can be performed in an oxygen-containing gas atmosphere. In this way, on the one hand, ion activation and uniform diffusion in the well region 410 can be achieved; on the other hand, the exposed surface of the gate electrode material layer 330b located on the second surface of the substrate can be oxidized during the annealing process, thereby forming an oxidation blocking layer 500 on the exposed surface of the gate electrode material layer 330b, and the oxidation blocking layer 500 can effectively block the precipitation of ions in the gate electrode material layer 330b. In addition, when performing the first ion implantation process, the ions bombard the gate dielectric layer 320 on the first surface of the substrate, causing the gate dielectric layer 320 to be damaged (for example, the thickness of the gate dielectric layer 320 may be reduced, the density of the film layer may be reduced, etc., especially the gate dielectric layer 320 at the top corner of the gate trench 310 may be easily damaged and cause problems such as gate-source leakage current). The first thermal annealing process can also be used to oxidize the first surface of the substrate 100, thereby repairing the film quality of the gate dielectric layer 320, improving the density of the gate dielectric layer 320, and further improving problems such as gate-source leakage current.

[0063] It should be noted that, when performing the high temperature process of the first thermal annealing process, the doped ions in the gate electrode material layer 330b on the second surface of the substrate are easily diffused and there is a risk of precipitation. In this regard, in this embodiment, oxygen is also introduced when performing the first thermal annealing process to oxidize the exposed surface of the gate electrode material layer 330b to form an oxidation blocking layer 500, thereby effectively blocking the ions in the gate electrode material layer 330b from precipitating. In addition, in this high temperature process of the first thermal annealing process, if the thickness of the gate dielectric layer 320 at the top corner of the gate trench is insufficient or the film density is poor, this will cause the ions in the gate electrode 330 and the ions in the well region 410 to diffuse through the top corner of the trench. In this embodiment, oxygen is also introduced when performing the first thermal annealing process, thereby repairing the thickness and film density of the gate dielectric layer 320, ensuring the isolation between the gate electrode 330 and the well region 410, and effectively improving the problem of ion mutual diffusion between the gate electrode 330 and the well region 410.

[0064] In a specific example, the method for performing the first thermal annealing process may include: first placing the substrate structure in a thermal annealing process chamber; then entering a temperature rise stage to increase the temperature in the process chamber, and starting to introduce oxygen into the process chamber during the temperature rise stage, so that the oxidation process can begin during the temperature rise stage, so that the oxidation barrier layer 500 can be formed faster on the surface of the gate electrode material layer 330b, and the gate dielectric layer 320 can be repaired earlier; thereafter, entering a constant temperature stage to complete the thermal annealing treatment, and oxygen can continue to be introduced during this stage.

[0065] It should be noted that in this embodiment, oxygen is introduced at the heating stage at a relatively low temperature, so that the gate electrode material layer 330b can be oxidized and the gate dielectric layer 320 can be repaired in a low temperature environment, thereby avoiding the problem of ion precipitation due to excessive temperature during the oxidation process. In particular, in the heating stage, the temperature in the process chamber rises, for example, in a slope trend, and oxygen can start the oxidation process at the initial stage of heating, so that before the completion of the heating stage, an oxide layer of a certain thickness can be oxidized on the surface of the gate electrode material layer 330b and the gate dielectric layer 320 can be repaired, and as the oxidation continues, the oxide layer can be further thickened to form an oxidation barrier layer 500, so as to ensure that there will be no problem of ion precipitation during the oxidation process, and when entering the high temperature constant temperature stage, ion precipitation can also be prevented under the blocking of the oxidation barrier layer 500 and the repaired gate dielectric layer 320. For example, the temperature in the heating stage can be set to be no higher than 950°C, so as to achieve the purpose of low-temperature oxidation and low-temperature repair, and prevent the problem of ion precipitation during the oxidation process.

[0066] Furthermore, nitrogen may be introduced during the first thermal annealing process. Specifically, nitrogen may be introduced after a predetermined time of introducing oxygen. For example, nitrogen may be introduced after entering the constant temperature stage until the annealing process is completed.

[0067] Next reference Fig.10 As shown, in a further solution, performing an ion implantation process and an annealing process to form an ion doped region may also include: performing a second ion implantation process and a second thermal annealing process to form a source doped region 420 in the well region 410, and the doping type of the source doped region 420 is the same as the doping type of the gate electrode 330. For example, the gate electrode 330 in this embodiment is N-type doped, and the source doped region 420 is specifically N-type doped, so the second ion implantation process is N-type ion implantation. And, through the second thermal annealing process, the implanted ions are uniformly diffused and the implanted doped ions are activated, thereby forming the source doped region 420.

[0068] In this embodiment, the second thermal annealing process can also be performed in an oxygen-containing gas atmosphere, so that, on the one hand, the ion activation and uniform diffusion in the source doping region 420 can be achieved; on the other hand, oxygen can be used to repair the damage of the gate dielectric layer 320 in the second ion implantation process, improve the film quality of the gate dielectric layer 320, especially for the gate dielectric layer 320 at the top corner position of the gate trench, the gate-source leakage current and other problems can be effectively improved after the repair. Specifically, when the second ion implantation process is performed, the ions will also bombard the gate dielectric layer 320 on the first surface of the substrate, causing the gate dielectric layer 320 to be damaged (for example, the gate dielectric layer 320 will be thinned, the film density will be reduced, etc., especially the gate dielectric layer 320 at the top corner position of the gate trench 310 will be easily damaged and cause problems such as gate-source leakage current), and the first surface of the substrate 100 can be oxidized by the second thermal annealing process, thereby repairing the film quality of the gate dielectric layer 320, improving the density of the gate dielectric layer 320, and effectively improving problems such as gate-source leakage current. In addition, through the second thermal annealing process, the gate electrode material layer 330b on the second surface of the substrate may continue to be oxidized, thereby increasing the thickness of the formed oxidation blocking layer 500 to improve its blocking ability and better prevent the gate electrode material layer 330b on the second surface of the substrate from having ion precipitation problems.

[0069] Similar to the first thermal annealing process, when performing the high temperature process of the second thermal annealing process, the doped ions in the gate electrode material layer 330b are easily diffused. At this time, since the oxidation blocking layer 500 is formed on the surface of the gate electrode material layer 330b, the ion precipitation in the gate electrode material layer 330b can be effectively blocked. In addition, in the second thermal annealing process, the thickness and film density of the gate dielectric layer 320 are repaired by oxidation, and the effective isolation between the gate electrode 330 and the side doped regions (including the well region 410 and the source doped region 420) can be ensured, further improving the problem of ion mutual diffusion between the gate electrode 330 and the side doped regions.

[0070] In a specific example, the method for performing the second thermal annealing process may include: placing the substrate structure in a thermal annealing process chamber; then, entering a temperature rise stage to increase the temperature in the process chamber, and starting to introduce oxygen during the temperature rise stage, so that oxidation can begin during the temperature rise stage, so that the gate dielectric layer 320 can be repaired earlier; thereafter, entering a constant temperature stage to complete the thermal annealing treatment, and oxygen can continue to be introduced during this stage.

[0071] For the second thermal annealing process, oxygen is also introduced during the relatively low temperature heating stage, so that the gate dielectric layer 320 can be repaired in a low temperature environment, avoiding the problem of ion precipitation caused by oxidation repair in a high temperature environment. In particular, during the heating stage, the temperature in the process chamber rises, for example, in a slope trend, and oxygen can start the oxidation process at the initial stage of heating, so the gate dielectric layer 320 can be repaired before the heating stage is completed, so as to ensure that there will be no problem of ion precipitation during the repair process, and when entering the high temperature constant temperature stage, ion precipitation can also be prevented under the blocking of the repaired gate dielectric layer 320. Among them, the temperature of the heating stage can be set to no higher than 950°C, so as to achieve the purpose of low-temperature oxidation repair and prevent the problem of ion precipitation during the oxidation repair process.

[0072] Furthermore, nitrogen may be introduced in the second thermal annealing process. Specifically, nitrogen may be introduced after a predetermined time of introducing oxygen. For example, nitrogen may be introduced after entering the constant temperature stage until the annealing process is completed.

[0073] In summary, with the development of semiconductor technology, people have put forward higher requirements for the preparation process and device performance of field effect transistors. A key parameter for measuring the performance of field effect transistors is the gate-source leakage current (IGSS), which is generally required to be less than 100nA (i.e., IGSS < 100nA).

[0074] Among them, the furnace tube process is used to achieve batch film deposition (including batch deposition of gate electrode material layers), which greatly improves the production efficiency of the product; and for the gate electrode material layer 330b on the second surface of the substrate, oxygen is used to oxidize it in the subsequent annealing process to form an oxidation barrier layer 500 on the exposed surface of the gate electrode material layer 330b, so as to avoid ion precipitation in the gate electrode material layer 330b and prevent contamination of semiconductor processing equipment. Specifically, when processing the substrate 100, part of the process needs to place the second surface of the substrate 100 toward the carrier (for example, in the dry etching process). At this time, if there is ion precipitation in the gate electrode material layer 330b on the second surface of the substrate 100, the precipitated ions will adhere to the carrier of the processing equipment to pollute the equipment, and will also pollute the next processed substrate. In this embodiment, the oxidation blocking layer 500 is used to prevent ion precipitation (for example, phosphorus precipitation) in the gate electrode material layer 330b, which can not only avoid contamination of semiconductor processing equipment and reduce the maintenance frequency of equipment, but also prevent the impact on the next processing substrate, thereby improving product quality and yield.

[0075] Furthermore, in order to reduce the gate-source leakage current, in the preparation method of the field effect transistor provided in the present embodiment, on the one hand, after the gate trench 310 is formed, the mask layer 200 is removed, so that the top angle morphology of the gate trench 310 can be optimized (that is, modified to an arc-shaped top angle). Compared with the prior art in which the mask layer is still retained and the top angle of the trench is directly etched to form a step-shaped top angle, in the present embodiment, the order in which the mask layer 200 is removed is changed, thereby changing the substrate conditions, so that the top angle of the gate trench 310 can be overall modified by etching and become smoother, which is conducive to reducing the attack on the gate dielectric layer 320 located at the top angle of the trench in the subsequent process, and ensuring that the gate electrode 330 and the ion doping on its side are On the other hand, before ion implantation, the thinning amount of the gate dielectric layer 320 is reduced as much as possible to slow down the degree of drilling of the gate dielectric layer 320 at the top corner of the trench, and correspondingly improve the effective isolation between the gate electrode 330 and the ion-doped region on its side; in addition, oxygen is introduced during the subsequent thermal annealing process to further oxidize and repair the film thickness and density of the gate dielectric layer 320, improve the film quality of the gate dielectric layer 320, and effectively improve the problem of gate-source leakage current. Specifically, oxygen can be introduced during the heating stage at a relatively low temperature, so that the gate dielectric layer 320 can be oxidized and repaired in a low temperature environment, avoiding the problem of ion precipitation caused by oxidation repair in a high temperature environment.

[0076] Based on the above-mentioned preparation method, the field effect transistor formed is described below, and specific reference is made to Fig.10 As shown, the field effect transistor includes a substrate 100, a gate electrode 330 and an ion doping region formed on the substrate 100, etc.

[0077] Specifically, the substrate 100 has a first surface and a second surface opposite to each other, and the gate electrode 330 is formed on the first surface of the substrate 100. In addition, an ion doping region is formed in the substrate 100 on the side of the gate electrode. In this embodiment, the ion doping region may include a well region 410 and a source doping region 420. The well region 410 is formed in the substrate 100 on the side of the gate electrode, and the source doping region 420 is formed in the well region 410.

[0078] Continue to refer Fig.10 As shown, the field effect transistor also includes a gate electrode material layer 330b formed on the second surface of the substrate 100. The gate electrode material layer 330b and the gate electrode 330 are made of the same material, and both are doped material layers. For example, the gate electrode material layer 330b and the gate electrode 330 are both doped polysilicon layers. In a specific example, the gate electrode material layer 330b and the gate electrode 330 may both be phosphorus-doped polysilicon layers.

[0079] Furthermore, the surface of the gate electrode material layer 330b is oxidized to form an oxidation blocking layer 500, which can effectively block the precipitation of ions in the gate electrode material layer 330b, not only to avoid the precipitated ions from affecting the quality of the product, but also to reduce the pollution to the processing equipment and the maintenance frequency of the equipment, while preventing the impact on other processing substrates and improving the yield of the product.

[0080] Continue to refer Fig.10 As shown, in this embodiment, a trench field effect transistor is used as an example for explanation. At this time, a gate trench is also formed in the substrate 100. The gate trench is specifically recessed from the first surface of the substrate 100 inward, and a gate electrode 330 is formed in the gate trench. In addition, the top angle of the gate channel is further an arc-shaped top angle, so that the gate dielectric layer 320 formed on the arc-shaped top angle can be correspondingly flatter, ensuring the film thickness and density of the gate dielectric layer 320, ensuring effective isolation between the gate electrode 330 and the ion-doped region on its side, and reducing the gate-source leakage current.

[0081] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0082] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc. It should also be recognized that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one" and "a kind" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or" definition, unless the context clearly indicates the opposite meaning.

Claims

1. A method for preparing a field effect transistor, characterized in that: include: providing a substrate having a first surface and a second surface opposite to each other; Depositing a doped gate electrode material layer using a furnace process, wherein the gate electrode material layer is formed on a first surface and a second surface of the substrate; Performing an etching process to remove a portion of the gate electrode material layer located on the first surface of the substrate and retaining a portion of the gate electrode material layer to form a gate electrode; as well as, An ion implantation process and an annealing process are performed to form an ion doped region in the substrate on the side of the gate electrode, wherein the annealing process includes performing an annealing process in an oxygen-containing gas atmosphere to oxidize the exposed surface of the gate electrode material layer on the second surface of the substrate.

2. The method for preparing a field effect transistor according to claim 1, characterized in that: Before depositing the doped gate electrode material layer, the method further includes: etching the first surface of the substrate to form a gate trench in the substrate; Furthermore, when depositing the doped gate electrode material layer, the gate electrode material layer fills the gate trench, and after performing the etching process, the gate electrode material layer located in the gate trench is retained to form the gate electrode.

3. The method for preparing a field effect transistor according to claim 2, characterized in that: The method for preparing the gate trench comprises: forming a mask layer on the first surface of the substrate, and etching the first surface of the substrate using the mask layer as a mask to form the gate trench; and, The mask layer is removed, and an etching process is used to modify the top angle morphology of the gate trench, so as to modify the top angle of the gate trench into an arc-shaped top angle.

4. The method for preparing a field effect transistor according to claim 2, wherein: After forming the gate trench and before depositing the gate electrode material layer, the method further includes: A gate dielectric layer is formed on the substrate, wherein the gate dielectric layer is formed on the inner wall of the gate trench and on the first surface of the substrate.

5. The method for preparing a field effect transistor according to claim 4, characterized in that: After performing an etching process to form the gate electrode and before performing an ion implantation process, the method further includes: reducing the thickness of the gate dielectric layer located on the first surface of the substrate.

6. The method for preparing a field effect transistor according to claim 5, characterized in that: The gate dielectric layer is thinned to a thickness less than or equal to 250 angstroms.

7. The method for preparing a field effect transistor according to claim 4, characterized in that: After performing an etching process to form the gate electrode, the gate dielectric layer outside the gate trench is exposed; and during the annealing process, the exposed gate dielectric layer is also oxidized and repaired.

8. The method for preparing a field effect transistor according to claim 1, characterized in that: Performing an ion implantation process and an annealing process to form an ion doped region includes: A first ion implantation process and a first thermal annealing process are performed to form a well region in the substrate at a side of the gate electrode, and the first thermal annealing process is performed in an oxygen-containing gas atmosphere.

9. The method for preparing a field effect transistor according to claim 1, characterized in that: Performing an ion implantation process and an annealing process to form an ion doped region includes: A second ion implantation process and a second thermal annealing process are performed to form a source doping region in the substrate at the side of the gate electrode, and the second thermal annealing process is performed in an oxygen-containing gas atmosphere.

10. The method for preparing a field effect transistor according to claim 8 or 9, characterized in that: The method of performing the first thermal annealing process and the second thermal annealing process both include: placing the substrate structure in a thermal annealing process chamber; Entering a temperature rise phase to increase the temperature in the process chamber, and introducing oxygen during the temperature rise phase to oxidize the exposed surface of the gate electrode material layer on the second surface of the substrate; and, Enter the constant temperature stage to complete the thermal annealing treatment.

11. The method for preparing a field effect transistor according to claim 10, characterized in that: The method for performing the first thermal annealing process and the second thermal annealing process further includes: after introducing oxygen for a predetermined time, introducing nitrogen into the process chamber.

12. A field effect transistor, characterized in that: include: a substrate having opposing first and second surfaces; A gate electrode formed on the first surface of the substrate; an ion-doped region formed in the substrate on the side of the gate electrode; as well as, A gate electrode material layer is formed on the second surface of the substrate, and a surface of the gate electrode material layer is oxidized to form an oxidation blocking layer.

13. The field effect transistor according to claim 12, characterized in that A gate trench is formed in the substrate, the gate trench is recessed inward from the first surface of the substrate, the gate electrode is formed in the gate trench; and the top angle of the gate trench is an arc-shaped top angle.

14. The field effect transistor according to claim 13, characterized in that It also includes a gate dielectric layer, which is formed on the inner wall of the gate trench and covers the arc-shaped top corner of the gate channel.

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