Wafer bonding alignment method and device

Abstract

The invention provides a wafer bonding alignment method and device. The wafer bonding alignment method comprises the following steps of: moving an upper wafer carrying disc and / or a lower wafer carrying disc to enable an upper wafer and a lower wafer on the upper wafer carrying disc and / or the lower wafer carrying disc to be approximately overlapped in the vertical direction; aligning an alignment module positioned above the upper wafer loading disc or below the lower wafer loading disc to the V-shaped notches and the edge alignment points which are arranged on the upper wafer and the lower wafer at intervals respectively, and acquiring coordinates of the V-shaped notches and the edge alignment points which correspond up and down through avoiding holes in the upper wafer loading disc or the lower wafer loading disc respectively; according to the vertically corresponding groups of coordinate data, moving the upper wafer and / or the lower wafer, so that the coordinate errors of the vertically corresponding groups of V-shaped gaps and edge alignment points are reduced to be within a first preset range, and the alignment of the upper wafer and the lower wafer is realized; and bonding the upper wafer and the lower wafer. According to the invention, the problem of low wafer bonding alignment efficiency in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer bonding alignment method and device. Background Art

[0002] In the existing wafer bonding alignment process, generally, a marking pattern is made on the bonding surface of the upper and lower wafers carried by the upper and lower wafer carriers, and then the marking pattern is respectively identified and the alignment information is obtained through the upper and lower lenses, and then the wafer carrier is moved according to the alignment information to achieve the alignment of the upper and lower wafers. However, during the bonding alignment process, the wafer carrier needs to be moved multiple times, which makes it easy for errors to occur between multiple movements, and it is impossible to obtain the alignment information of the two marking patterns at the same time, affecting the final alignment accuracy. In addition, the production process of the marking pattern includes more complex lithography and etching processes, which makes the entire wafer bonding alignment process complicated, resulting in low wafer bonding alignment efficiency and increased production costs.

[0003] As can be seen from the above, the prior art has the problem of low wafer bonding alignment efficiency. Summary of the invention

[0004] The main purpose of the present invention is to provide a wafer bonding alignment method and device to solve the problem of low wafer bonding alignment efficiency in the prior art.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present invention, a wafer bonding alignment method is provided, comprising: moving an upper wafer carrier and / or a lower wafer carrier so that the upper wafer and the lower wafer thereon roughly overlap in the vertical direction; aligning an alignment module located above the upper wafer carrier or below the lower wafer carrier with the V-shaped notches and edge alignment points spaced apart on the upper wafer and the lower wafer, respectively, and obtaining the coordinates of the upper and lower corresponding V-shaped notches and edge alignment points through avoidance holes on the upper wafer carrier or the lower wafer carrier, respectively; moving the upper wafer and / or the lower wafer according to the upper and lower corresponding groups of coordinate data so that the coordinate errors of the upper and lower corresponding groups of V-shaped notches and edge alignment points are reduced to within a first preset range, thereby realizing the alignment of the upper wafer and the lower wafer; and bonding the upper wafer and the lower wafer.

[0006] Furthermore, before the alignment module is respectively aligned with the V-shaped notch and the edge alignment point, the wafer bonding alignment method also includes: aligning the pre-alignment module located above the upper wafer carrier or below the lower wafer carrier with the avoidance hole corresponding to the V-shaped notch and / or at least one edge alignment point and emitting a light beam, and when the light beam passes through two corresponding upper and lower V-shaped notches and / or two edge alignment points at the same time, the pre-alignment operation is completed.

[0007] Furthermore, the wafer bonding alignment method also includes: when the light beam cannot simultaneously pass through the two corresponding upper and lower V-shaped notches and / or two edge alignment points, moving the upper wafer and / or the lower wafer until the light beam can simultaneously pass through the two corresponding upper and lower V-shaped notches and / or two edge alignment points.

[0008] Furthermore, after the upper wafer and the lower wafer are aligned, the wafer bonding alignment method also includes: measuring the distance between the calibration module and the edge of the upper wafer and the edge of the lower wafer in the horizontal direction by calibration modules respectively arranged on the upper wafer carrier and the lower wafer carrier, and when the difference between the two distances is within a second preset range, the calibration operation is completed.

[0009] Furthermore, the wafer bonding alignment method further includes: when the difference between the two distances is greater than a second preset range, moving the upper wafer and / or the lower wafer until the difference between the two distances is reduced to within the second preset range.

[0010] According to another aspect of the present invention, a wafer bonding alignment device is also provided, and the wafer bonding alignment device is used to perform the above-mentioned wafer bonding alignment method, and the wafer bonding alignment device includes: an upper wafer carrier and a lower wafer carrier; an upper wafer and a lower wafer, the upper wafer and the lower wafer are respectively arranged on the upper wafer carrier and the lower wafer carrier, and the upper wafer and the lower wafer respectively correspond to V-shaped notches and edge alignment points arranged at intervals, and there are multiple edge alignment points; an alignment module, there is at least one alignment module, and at least one alignment module is located above the upper wafer carrier or below the lower wafer carrier; avoidance holes are opened at the positions of the upper wafer carrier or the lower wafer carrier corresponding to the V-shaped notches and the edge alignment points, so that the alignment module obtains the coordinates of each V-shaped notch and the edge alignment point through the avoidance holes.

[0011] Furthermore, there are two edge alignment points, which are two intersection points of the extended lines of both side edges of the V-shaped notch and the edge of the wafer.

[0012] Furthermore, there are three edge alignment points, and the three edge alignment points and the V-shaped notch are arranged at equal intervals along the circumference of the upper wafer and the lower wafer.

[0013] Further, there is one alignment module, which is movably arranged; or there are multiple alignment modules, which are arranged one-to-one corresponding to the V-shaped notch and the edge alignment point respectively.

[0014] Furthermore, the diameter of the avoidance hole is larger than the diameter of the circle where the V-shaped notch is located and the outer diameter of the edge alignment point.

[0015] Furthermore, the wafer bonding alignment device also includes a pre-alignment module, there is at least one pre-alignment module, the pre-alignment module is located above the upper wafer carrier or below the lower wafer carrier, and is used to pre-align the upper wafer and the lower wafer before the alignment module performs the alignment operation.

[0016] Further, there is one pre-alignment module, which is movably arranged; or there is one pre-alignment module, which is arranged corresponding to the V-shaped notch; or there are multiple pre-alignment modules, which are respectively arranged corresponding to the V-shaped notch and at least one edge alignment point.

[0017] Furthermore, the alignment module includes a lens, which captures the image coordinates of the V-shaped notch and the edge alignment point; and / or the pre-alignment module is at least one of an infrared module, a laser module or a colored light module, and the light beam emitted by the pre-alignment module simultaneously passes through the avoidance hole, two corresponding upper and lower V-shaped notches and / or two edge alignment points to complete the pre-alignment operation.

[0018] Furthermore, the wafer bonding alignment device also includes a calibration module. At least one calibration module is respectively arranged on the upper wafer carrier and the lower wafer carrier. The calibration module is spaced apart from the upper wafer and the lower wafer and is used to measure the distance from the edge of the wafer in the horizontal direction.

[0019] Furthermore, the calibration module is at least one of a lens, a ranging radar or an infrared ranging module.

[0020] Applying the technical solution of the present invention, the wafer bonding alignment method includes: moving the upper wafer carrier and / or the lower wafer carrier so that the upper wafer and the lower wafer thereon roughly overlap in the vertical direction; aligning the alignment modules located above the upper wafer carrier or below the lower wafer carrier with the V-shaped notches and edge alignment points arranged at intervals on the upper wafer and the lower wafer respectively, and obtaining the coordinates of the upper and lower corresponding V-shaped notches and edge alignment points respectively through the avoidance holes on the upper wafer carrier or the lower wafer carrier; and moving the upper wafer and / or the lower wafer according to the upper and lower corresponding groups of coordinate data so that the coordinate errors of the upper and lower corresponding groups of V-shaped notches and edge alignment points are reduced to the first The upper wafer and the lower wafer are aligned within a preset range; the upper wafer and the lower wafer are bonded, and the coordinates of the corresponding V-notch and edge alignment point of the upper and lower wafers can be obtained simultaneously by using the above alignment method, thereby avoiding the errors caused by multiple wafer movements, improving the alignment accuracy, and simplifying the alignment steps. The V-notch of the wafer itself is utilized without the need for additional marking patterns, which makes it easy to identify and eliminates the production process required for the marking patterns, thereby greatly reducing the overall wafer bonding alignment process, improving the wafer bonding alignment efficiency, and reducing the production cost, thereby solving the problem of low wafer bonding alignment efficiency in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 A flow chart of a wafer bonding alignment method in a specific embodiment of the present invention is shown;

[0023] Figure 2 A schematic structural diagram of a wafer bonding alignment device in a specific embodiment of the present invention is shown;

[0024] Figure 3 A schematic diagram showing the structure of an upper wafer carrier and an upper wafer in a specific embodiment of the present invention is shown;

[0025] Figure 4 A schematic diagram showing the distribution of edge alignment points in a specific embodiment of the present invention is shown;

[0026] Figure 5 A schematic diagram showing the distribution of edge alignment points in another specific embodiment of the present invention is shown;

[0027] Figure 6 A schematic structural diagram of a wafer bonding alignment device in another specific embodiment of the present invention is shown;

[0028] Figure 7 A schematic structural diagram of a wafer bonding alignment device in another specific embodiment of the present invention is shown.

[0029] The above drawings include the following reference numerals:

[0030] 10. Upper wafer carrier; 11. Avoidance hole; 20. Lower wafer carrier; 30. Upper wafer; 40. Lower wafer; 50. V-shaped notch; 60. Edge alignment point; 70. Alignment module; 80. Pre-alignment module; 90. Calibration module. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In order to solve the problem of low wafer bonding alignment efficiency in the prior art, the present invention provides a wafer bonding alignment method and device.

[0033] like Figure 1 As shown, the present application provides a wafer bonding alignment method, including: moving an upper wafer carrier 10 and / or a lower wafer carrier 20 so that the upper wafer 30 and the lower wafer 40 thereon roughly overlap in the vertical direction; aligning an alignment module 70 located above the upper wafer carrier 10 or below the lower wafer carrier 20 with the V-shaped notches 50 and the edge alignment points 60 arranged at intervals on the upper wafer 30 and the lower wafer 40, respectively, and obtaining the coordinates of the upper and lower corresponding V-shaped notches 50 and the edge alignment points 60 through the avoidance holes 11 on the upper wafer carrier 10 or the lower wafer carrier 20; moving the upper wafer 30 and / or the lower wafer 40 according to the upper and lower corresponding groups of coordinate data so that the coordinate errors of the upper and lower corresponding groups of V-shaped notches 50 and the edge alignment points 60 are reduced to a first preset range, thereby realizing the alignment of the upper wafer 30 and the lower wafer 40; and bonding the upper wafer 30 and the lower wafer 40.

[0034] It is understandable that the first step of roughly overlapping the upper wafer 30 and the lower wafer 40 is only a rough alignment step or a preliminary alignment step. At this time, there is a position error between the upper and lower wafers, and the edges of the upper and lower wafers cannot completely overlap. After the rough alignment step, the alignment module 70 is used to perform a fine alignment step.

[0035] In addition, it should be noted that the above-mentioned groups of V-shaped notches 50 and edge alignment points 60 refer to two upper and lower corresponding V-shaped notches 50 or two edge alignment points 60 as a group. That is, this embodiment includes a group of V-shaped notches 50 and at least one group of edge alignment points 60.

[0036] The above alignment method can simultaneously obtain the coordinates of the corresponding V-notch 50 and edge alignment point 60 of the upper and lower wafers, avoiding the errors caused by multiple wafer movements, improving the alignment accuracy, and simplifying the alignment steps. The V-notch 50 of the wafer itself is utilized without the need for additional marking patterns, which makes it easy to identify and eliminates the production process required for the marking pattern, thereby greatly reducing the overall wafer bonding alignment process, improving the wafer bonding alignment efficiency, and reducing production costs.

[0037] Furthermore, before the alignment module 70 is respectively aligned with the V-shaped notch 50 and the edge alignment point 60, the wafer bonding alignment method also includes: aligning the pre-alignment module 80 located above the upper wafer carrier 10 or below the lower wafer carrier 20 with the avoidance hole 11 corresponding to the V-shaped notch 50 and / or at least one edge alignment point 60 and emitting a light beam, and when the light beam passes through the two corresponding upper and lower V-shaped notches 50 and / or two edge alignment points 60 at the same time, the pre-alignment operation is completed.

[0038] That is to say, between the coarse alignment step and the fine alignment step, the wafer bonding alignment method of the present application may further include a pre-alignment step, thereby further improving the wafer alignment accuracy.

[0039] Furthermore, the wafer bonding alignment method also includes: when the light beam cannot simultaneously pass through the two corresponding upper and lower V-shaped notches 50 and / or the two edge alignment points 60, moving the upper wafer 30 and / or the lower wafer 40 until the light beam can simultaneously pass through the two corresponding upper and lower V-shaped notches 50 and / or the two edge alignment points 60.

[0040] Specifically, the pre-alignment module 80 in this embodiment aligns the avoidance hole 11 corresponding to the V-shaped notch 50 and emits a light beam. When the light beam passes through the two corresponding V-shaped notches 50 at the same time, the pre-alignment operation is completed. When the light beam cannot pass through the two corresponding V-shaped notches 50 at the same time, the upper wafer 30 and / or the lower wafer 40 are moved until the light beam can pass through the two corresponding V-shaped notches 50 at the same time.

[0041] In an optional embodiment, in order to further improve the alignment effect of the pre-alignment operation, pre-alignment of edge alignment points 60 can be added on the basis of the V-shaped notch 50. The number of edge alignment points 60 can be one or more and can be selected according to actual needs.

[0042] Furthermore, after the upper wafer 30 and the lower wafer 40 are aligned, the wafer bonding alignment method also includes: measuring the distance between the calibration module 90 and the edge of the upper wafer 30 and the edge of the lower wafer 40 in the horizontal direction by means of the calibration modules 90 respectively arranged on the upper wafer carrier 10 and the lower wafer carrier 20, and when the difference between the two distances is within a second preset range, the calibration operation is completed.

[0043] Furthermore, the wafer bonding alignment method further includes: when the difference between the two distances is greater than a second preset range, moving the upper wafer 30 and / or the lower wafer 40 until the difference between the two distances is reduced to within the second preset range.

[0044] That is to say, after completing the fine alignment step, the wafer bonding alignment method of the present application may further include a calibration step to further improve the wafer alignment accuracy.

[0045] It should be noted that the specific values ​​of the first preset range and the second preset range need to be determined according to actual needs and are not limited here.

[0046] like Figures 2 to 7As shown, the present application also provides a wafer bonding alignment device, which is used to perform the above-mentioned wafer bonding alignment method. The wafer bonding alignment device includes an upper wafer carrier 10 and a lower wafer carrier 20, an upper wafer 30 and a lower wafer 40, and an alignment module 70. The upper wafer 30 and the lower wafer 40 are respectively arranged on the upper wafer carrier 10 and the lower wafer carrier 20. The upper wafer 30 and the lower wafer 40 correspond to V-shaped notches 50 and edge alignment points 60 arranged at intervals, respectively, and there are multiple edge alignment points 60. There is at least one alignment module 70, and at least one alignment module 70 is located above the upper wafer carrier 10. The upper wafer carrier 10 is provided with an avoidance hole 11 at the position corresponding to the V-shaped notch 50 and the edge alignment point 60, so that the alignment module 70 obtains the coordinates of each V-shaped notch 50 and the edge alignment point 60 through the avoidance hole 11.

[0047] It should be noted that the V-shaped notch 50 in this embodiment is the V-shaped notch that comes with the wafer when it leaves the factory, so it can be directly used in wafer bonding alignment without any processing and can be easily identified during alignment.

[0048] In an optional embodiment, the alignment module 70 may also be located below the lower wafer carrier 20, and the avoidance hole 11 is correspondingly opened on the lower wafer carrier 20. That is to say, the alignment module 70 in the present application is arranged on the upper side or the lower side of the entire wafer bonding alignment device, and it is not necessary to arrange it on both the upper and lower sides while being able to simultaneously obtain the coordinate information of the alignment components, thereby avoiding the error caused by moving the wafer multiple times, improving the alignment accuracy, and simplifying the alignment steps.

[0049] In this embodiment, if Figure 3 to Figure 4 As shown, there are two edge alignment points 60, and the two edge alignment points 60 and the V-shaped notch 50 are arranged at intervals along the circumference of the wafer. In other words, the two edge alignment points 60 and the V-shaped notch 50 form a similar triangular vertex layout, which is conducive to obtaining edge coordinates and improving alignment accuracy. Specifically, the two edge alignment points 60 are two intersections of the extended lines of the two sides of the V-shaped notch 50 and the edge of the wafer, thereby forming an isosceles triangle vertex layout, which is conducive to further improving alignment accuracy.

[0050] In an alternative embodiment, if Figure 5As shown, there are three edge alignment points 60, which are arranged at equal intervals along the circumference of the upper wafer 30 and the lower wafer 40. That is to say, the angle between each edge alignment point 60 and between the edge alignment point 60 and the V-shaped notch 50 is 90°. Specifically, an edge alignment point 60 is set on the extension line passing through the V-shaped notch 50 and the center of the wafer, and two edge alignment points 60 are set on the edge of the wafer of another extension line perpendicular to the aforementioned extension line and passing through the center of the wafer. Through the above-mentioned arrangement, it is possible to ensure that there are alignment points in all four directions of the wafer, prevent the situation where only part of the edge of the wafer is aligned, and improve the coordinate acquisition accuracy and alignment accuracy. Of course, the number of edge alignment points 60 can also be more, which can be selected according to actual needs.

[0051] In this embodiment, there is one alignment module 70, and the alignment module 70 is movably arranged. Specifically, when performing the fine alignment step, the mobile alignment module 70 is aligned with a V-shaped notch 50 and two edge alignment points 60 of the upper and lower wafers respectively, and the coordinates of a V-shaped notch 50 and the coordinates of the two edge alignment points 60 corresponding to the upper and lower wafers 30 and the lower wafer 40 are obtained. Among them, the coordinates of the three alignment positions are acquired and recorded in sequence, and the movement order of the alignment module 70 can be interchanged without restriction.

[0052] In an optional embodiment, there are multiple alignment modules 70, and the multiple alignment modules 70 are respectively arranged in one-to-one correspondence with the V-shaped notch 50 and the edge alignment point 60. That is to say, the alignment modules 70 in this embodiment are relatively fixedly arranged, corresponding to one V-shaped notch 50 and two edge alignment points 60, there are three alignment modules 70, and the three alignment modules 70 are respectively located above or below one V-shaped notch 50 and two edge alignment points 60.

[0053] In this embodiment, the alignment module 70 includes a lens, which captures the image coordinates of the V-shaped notch 50 and the edge alignment point 60 .

[0054] In this embodiment, the diameter of the avoidance hole 11 is larger than the diameter of the circle where the V-shaped notch 50 is located and the outer diameter of the edge alignment point 60. Through the above configuration, it is possible to ensure that the alignment module 70 fully obtains the position coordinates of the V-shaped notch 50 and the edge alignment point 60, avoiding interference caused by the avoidance hole 11.

[0055] like Figure 6As shown, the wafer bonding alignment device further includes a pre-alignment module 80, at least one of which is located above the upper wafer carrier 10 or below the lower wafer carrier 20, and is used to perform a pre-alignment operation on the upper wafer 30 and the lower wafer 40 before the alignment module 70 performs the alignment operation. Of course, the pre-alignment module 80 can also be located below the lower wafer carrier 20, in which case the avoidance hole 11 is correspondingly opened on the lower wafer carrier 20, which can be selected according to actual needs.

[0056] In this embodiment, there is one pre-alignment module 80, and the pre-alignment module 80 is arranged corresponding to the V-shaped notch 50. That is, in this embodiment, only the V-shaped notch 50 is used for pre-alignment. Specifically, the pre-alignment module 80 and the alignment module 70 are located on the same side, and the pre-alignment module 80 is arranged close to the alignment module 70 or is located on the alignment module 70.

[0057] In an optional embodiment, in order to improve the pre-alignment effect, the V-shaped notch 50 and at least one edge alignment point are used for pre-alignment. Accordingly, there can be one pre-alignment module 80, which is movably arranged, or there can be multiple pre-alignment modules 80, which are relatively fixedly arranged and respectively arranged in one-to-one correspondence with the V-shaped notch 50 and at least one edge alignment point 60.

[0058] In this embodiment, the pre-alignment module 80 is at least one of an infrared module, a laser module or a colored light module. The light beam emitted by the pre-alignment module 80 simultaneously passes through the avoidance hole 11, two corresponding upper and lower V-shaped notches 50 and / or two edge alignment points 60 to complete the pre-alignment operation.

[0059] like Figure 7 As shown, the wafer bonding alignment device also includes a calibration module 90, and at least one calibration module 90 is respectively arranged on the upper wafer carrier 10 and the lower wafer carrier 20, and the calibration module 90 is arranged at intervals with the upper wafer 30 and the lower wafer 40, and is used to measure the distance from the edge of the wafer in the horizontal direction. Specifically, the calibration modules 90 are arranged in pairs up and down, so as to become the same reference point. By setting the calibration module 90, the distance between the calibration module 90 and the edge of the upper wafer 30 and the edge of the lower wafer 40 in the horizontal direction can be measured respectively, and then the difference between the two distances is limited to a second preset range, thereby further improving the wafer alignment accuracy.

[0060] In this embodiment, the calibration module 90 is at least one of a lens, a ranging radar or an infrared ranging module.

[0061] From the above description, it can be seen that the above-mentioned embodiments of the present invention achieve the following technical effects: the above-mentioned alignment method can simultaneously obtain the coordinates of the corresponding V-shaped notches 50 and edge alignment points 60 of the upper and lower wafers, avoiding the errors caused by multiple movements of the wafers, improving the alignment accuracy, and simplifying the alignment steps. The V-shaped notch 50 of the wafer is utilized without the need for additional marking patterns, which makes it easy to identify and eliminates the production process required for the marking pattern, thereby greatly reducing the overall wafer bonding alignment process, improving the wafer bonding alignment efficiency, and reducing production costs.

[0062] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0063] Unless otherwise specifically stated, the relative arrangement of the parts and steps described in these embodiments, numerical expressions and numerical values ​​do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be regarded as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0064] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0065] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways, rotated 90 degrees or in other orientations, and the spatially relative descriptions used herein are interpreted accordingly.

[0066] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0067] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0068] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0069] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wafer bonding alignment method, characterized in that: include: Moving the upper wafer carrier (10) and / or the lower wafer carrier (20) so that the upper wafer (30) and the lower wafer (40) thereon substantially overlap in the vertical direction; Aligning an alignment module (70) located above the upper wafer carrier (10) or below the lower wafer carrier (20) with the V-shaped notches (50) and edge alignment points (60) arranged at intervals on the upper wafer (30) and the lower wafer (40), respectively, and obtaining the coordinates of the V-shaped notches (50) and the edge alignment points (60) corresponding to the upper and lower portions through the avoidance holes (11) on the upper wafer carrier (10) or the lower wafer carrier (20); According to each group of upper and lower corresponding coordinate data, the upper wafer (30) and / or the lower wafer (40) are moved so that the coordinate errors of each group of upper and lower corresponding V-shaped notches (50) and edge alignment points (60) are reduced to within a first preset range, thereby achieving alignment of the upper wafer (30) and the lower wafer (40); The upper wafer (30) and the lower wafer (40) are bonded.

2. The wafer bonding alignment method according to claim 1, characterized in that: Before the alignment module (70) aligns the V-shaped notch (50) and the edge alignment point (60) respectively, the wafer bonding alignment method further comprises: A pre-alignment module (80) located above the upper wafer carrier (10) or below the lower wafer carrier (20) is aligned with the avoidance hole (11) corresponding to the V-shaped notch (50) and / or at least one of the edge alignment points (60) and emits a light beam. When the light beam simultaneously passes through two corresponding upper and lower V-shaped notches (50) and / or two edge alignment points (60), the pre-alignment operation is completed.

3. The wafer bonding alignment method according to claim 2, characterized in that: The wafer bonding alignment method further comprises: When the light beam cannot simultaneously pass through the two upper and lower corresponding V-shaped notches (50) and / or the two edge alignment points (60), the upper wafer (30) and / or the lower wafer (40) are moved until the light beam can simultaneously pass through the two upper and lower corresponding V-shaped notches (50) and / or the two edge alignment points (60).

4. The wafer bonding alignment method according to claim 1, characterized in that: After the upper wafer (30) and the lower wafer (40) are aligned, the wafer bonding alignment method further comprises: The distances between the calibration module (90) and the edge of the upper wafer (30) and the edge of the lower wafer (40) in the horizontal direction are measured respectively by calibration modules (90) respectively arranged on the upper wafer carrier (10) and the lower wafer carrier (20); when the difference between the two distances is within a second preset range, the calibration operation is completed.

5. The wafer bonding alignment method according to claim 4, characterized in that: The wafer bonding alignment method further comprises: When the difference between the two distances is greater than the second preset range, the upper wafer (30) and / or the lower wafer (40) is moved until the difference between the two distances is reduced to within the second preset range.

6. A wafer bonding alignment device, characterized in that: The wafer bonding alignment device is used to perform the wafer bonding alignment method according to any one of claims 1 to 5, and the wafer bonding alignment device comprises: An upper wafer carrier (10) and a lower wafer carrier (20); An upper wafer (30) and a lower wafer (40), wherein the upper wafer (30) and the lower wafer (40) are respectively arranged on the upper wafer carrier (10) and the lower wafer carrier (20), and the upper wafer (30) and the lower wafer (40) respectively correspond to V-shaped notches (50) and edge alignment points (60) arranged at intervals, and the edge alignment points (60) are multiple; an alignment module (70), wherein there is at least one alignment module (70), and the at least one alignment module (70) is located above the upper wafer carrier (10) or below the lower wafer carrier (20); The upper wafer carrier (10) or the lower wafer carrier (20) is provided with avoidance holes (11) at positions corresponding to the V-shaped notches (50) and the edge alignment points (60), so that the alignment module (70) can obtain the coordinates of each of the V-shaped notches (50) and the edge alignment points (60) through the avoidance holes (11).

7. The wafer bonding alignment device according to claim 6, characterized in that: There are two edge alignment points (60), which are two intersection points of the extended lines of the two side edges of the V-shaped notch (50) and the edge of the wafer.

8. The wafer bonding alignment device according to claim 6, characterized in that: There are three edge alignment points (60), and the three edge alignment points (60) and the V-shaped notches (50) are arranged at equal intervals along the circumference of the upper wafer (30) and the lower wafer (40).

9. The wafer bonding alignment device according to claim 6, characterized in that: The alignment module (70) is one, and the alignment module (70) is movably arranged; or There are a plurality of alignment modules (70), and the plurality of alignment modules (70) are respectively arranged in one-to-one correspondence with the V-shaped notches (50) and the edge alignment points (60).

10. The wafer bonding alignment device according to claim 6, characterized in that: The diameter of the avoidance hole (11) is larger than the diameter of the circle where the V-shaped notch (50) is located and the outer diameter of the edge alignment point (60).

11. The wafer bonding alignment device according to claim 6, characterized in that: The wafer bonding alignment device also includes a pre-alignment module (80), and there is at least one pre-alignment module (80). The pre-alignment module (80) is located above the upper wafer carrier (10) or below the lower wafer carrier (20), and is used to perform a pre-alignment operation on the upper wafer (30) and the lower wafer (40) before the alignment module (70) performs an alignment operation.

12. The wafer bonding alignment device according to claim 11, characterized in that: The pre-alignment module (80) is one, and the pre-alignment module (80) is movably arranged; or The number of the pre-alignment module (80) is one, and the pre-alignment module (80) is arranged corresponding to the V-shaped notch (50); or There are a plurality of pre-alignment modules (80), and the plurality of pre-alignment modules (80) are respectively arranged in one-to-one correspondence with the V-shaped notch (50) and at least one edge alignment point (60).

13. The wafer bonding alignment device according to claim 11, characterized in that: The alignment module (70) comprises a lens, which captures the image coordinates of the V-shaped notch (50) and the edge alignment point (60); and / or The pre-alignment module (80) is at least one of an infrared module, a laser module or a colored light module, and the light beam emitted by the pre-alignment module (80) simultaneously passes through the avoidance hole (11), the two upper and lower corresponding V-shaped notches (50) and / or the two edge alignment points (60) to complete the pre-alignment operation.

14. The wafer bonding alignment device according to claim 6, characterized in that: The wafer bonding alignment device further comprises a calibration module (90), at least one calibration module (90) being respectively arranged on the upper wafer carrier (10) and the lower wafer carrier (20), and the calibration module (90) being arranged at intervals from the upper wafer (30) and the lower wafer (40) for measuring the distance from the edge of the wafer in the horizontal direction.

15. The wafer bonding alignment device according to claim 14, characterized in that: The calibration module (90) is at least one of a lens, a ranging radar or an infrared ranging module.

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