Negative capacitance tunneling phototransistor and preparation method and application thereof

Abstract

The invention relates to the technical field of photoelectric devices, in particular to a negative capacitance tunneling phototransistor and a preparation method and application thereof. The negative capacitance tunneling phototransistor is of a structure combining a ferroelectric material and a low-dimensional semiconductor heterojunction material, the characteristics of the ferroelectric material are combined with the tunneling effect and the photoelectric characteristic of a low-dimensional semiconductor heterojunction, and a hafnium oxide-based ferroelectric gate dielectric is used for replacing a gate dielectric layer of a traditional phototransistor. A negative capacitance effect is provided in the grid structure of the negative capacitance tunneling phototransistor so as to improve the performance of the device; through the negative capacitance effect of the ferroelectric material, the electrical performance of the tunneling field effect transistor is enhanced, the switching ratio and the on-state current of the device are improved, the sub-threshold swing of the device is further reduced, and the photoelectric responsivity and the response speed of the device are improved at the same time. Due to the arrangement of the grid electrode and the low-dimensional semiconductor heterojunction, the purposes of ultralow subthreshold swing and no hysteresis are achieved. In addition, the device has the characteristics of good stability, simple structure, easy preparation and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of photoelectric devices, and in particular to a negative capacitance tunneling phototransistor and a preparation method and application thereof. Background Art

[0002] Reducing power consumption and minimizing device size are key goals in developing integrated circuit microelectronic devices. In order to meet the evolving needs of circuits and electronic components, the field of optoelectronics has also begun to emphasize the need for low power consumption and small size for photodetectors and other optoelectronic devices. This requires that the device maintain good performance in terms of on-state current, switching ratio, and current hysteresis while having low operating voltage and low subthreshold swing. In recent years, some new electronic devices have been proposed to overcome the performance limitations of the Boltzmann limit on traditional metal oxide semiconductor field effect transistors, such as tunnel field effect transistors, negative capacitance field effect transistors, impact ionization field effect transistors, and Dirac source field effect transistors. Among them, tunnel field effect transistors and negative capacitance field effect transistors are considered to be the most effective low-power transistor devices. Tunnel field effect transistors achieve a breakthrough in the subthreshold swing limit through the principle of carrier band-to-band tunneling, while negative capacitance field effect transistors achieve a breakthrough in the subthreshold swing limit through the negative capacitance effect of the material. This makes tunnel field effect transistors and negative capacitance field effect transistors have great development potential in low-power and ultra-low-power electronic applications.

[0003] However, conventional tunnel field-effect transistors have problems such as dangling bonds between the semiconductor and the gate oxide layer, which affects the gate control efficiency and carrier transport, thereby limiting the device performance. In addition, the switching process in the tunnel field-effect transistor is mainly band-to-band tunneling, which means that it needs to operate at a lower bias voltage. This leads to relatively low on-state current and switching ratio of the tunnel field-effect transistor. Similarly, negative capacitance field-effect transistors face performance limitations due to the poor interface between the gate dielectric and the semiconductor channel. The ferroelectric in the negative capacitance field-effect transistor is easily polarized in the electric field, resulting in instability and hysteresis in its current-voltage curve. Summary of the invention

[0004] The purpose of the present invention is to provide a negative capacitance tunneling phototransistor and a preparation method and application thereof. The negative capacitance tunneling phototransistor has excellent photoelectric performance, good stability and simple structure.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, an oxide gate dielectric layer and a low-dimensional semiconductor material heterojunction layer which are sequentially stacked;

[0007] The low-dimensional semiconductor material heterojunction layer comprises a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same level;

[0008] The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer;

[0009] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0010] It also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0011] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface.

[0012] Preferably, the substrate is a P-type doped silicon substrate.

[0013] Preferably, the material of the oxide layer is silicon dioxide.

[0014] Preferably, the material of the gate electrode layer is titanium nitride.

[0015] Preferably, the material of the hafnium oxide-based ferroelectric gate dielectric layer having a negative capacitance effect is a doped hafnium oxide-based ferroelectric material;

[0016] The doping element of the hafnium oxide-doped ferroelectric material is one or more of zirconium, silicon, yttrium and aluminum.

[0017] Preferably, the material of the oxide gate dielectric layer is hafnium oxide and / or aluminum oxide.

[0018] Preferably, the first low-dimensional semiconductor material is a transition metal chalcogenide;

[0019] The second low-dimensional semiconductor material is a two-dimensional black phosphorus material.

[0020] Preferably, the metal source electrode and the metal drain electrode are both a chromium electrode and a gold electrode that are stacked.

[0021] The present invention also provides a method for preparing the negative capacitance tunneling phototransistor described in the above technical solution, comprising the following steps:

[0022] An oxide layer is prepared on the surface of the substrate by thermal oxidation;

[0023] Depositing a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer having a negative capacitance effect, and an oxide gate dielectric layer in sequence on the surface of the oxide layer;

[0024] Using a mechanical lift-off transfer method, a low-dimensional semiconductor heterojunction layer is prepared on the second surface and the third surface of the oxide gate dielectric layer;

[0025] A metal drain electrode is prepared on the first surface of the oxide gate dielectric layer, and a metal source electrode is prepared on the fourth surface of the oxide gate dielectric layer, and both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

[0026] The present invention also provides the application of the negative capacitance tunneling phototransistor described in the above technical solution or the negative capacitance tunneling phototransistor prepared by the preparation method described in the above technical solution in the photoelectric field.

[0027] The present invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, an oxide gate dielectric layer and a low-dimensional semiconductor material heterojunction layer which are sequentially stacked; the low-dimensional semiconductor material heterojunction layer comprises a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same horizontal height; the surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface and a fourth surface, and the first surface and the fourth surface are located at the oxide gate dielectric layer. The lower surface of the first low-dimensional semiconductor material contacts the second surface, and the lower surface of the second low-dimensional semiconductor material contacts the third surface; it also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode contacts the fourth surface; the first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface. The negative capacitance tunneling phototransistor of the present invention is a negative capacitance tunneling phototransistor structure combining a ferroelectric material with a low-dimensional semiconductor heterojunction material, and proposes a new type of phototransistor structure that combines the characteristics of ferroelectric materials with the tunneling effect and photoelectric characteristics of a low-dimensional semiconductor heterojunction, and uses a hafnium oxide-based ferroelectric gate dielectric to replace the traditional phototransistor gate dielectric layer to provide a negative capacitance effect in the negative capacitance tunneling phototransistor gate structure to improve device performance. The negative capacitance effect of ferroelectric materials is used to enhance the electrical performance of tunneling field effect transistors, improve the switching ratio and on-state current of the device, and further reduce the subthreshold swing of the device, while improving the photoelectric responsivity and response speed of the device. At the same time, the present invention realizes a negative capacitance tunneling phototransistor with ultra-low subthreshold swing and no hysteresis by setting a gate and a low-dimensional semiconductor heterojunction. A gap-type energy band structure is formed by a low-dimensional semiconductor heterojunction, which promotes effective carrier tunneling between the valence band and the conduction band. In addition, the negative capacitance tunneling phototransistor also has the characteristics of good stability, simple structure and easy preparation. It has been tested that the negative capacitance tunneling phototransistor of the present invention achieves an ultra-low subthreshold swing of 13.4mV / dec and a maximum switching ratio of 10 6, and almost no hysteresis in the subthreshold region. Under the action of 520nm laser, the negative capacitance tunneling phototransistor can achieve a maximum responsivity of 42A / W and a fastest response time of 8μs. The negative capacitance tunneling phototransistor combines the negative capacitance effect of ferroelectric materials with the tunneling effect and photoelectric properties of low-dimensional semiconductor heterojunctions, significantly improving the electrical and photoelectric performance of the negative capacitance tunneling phototransistor, and has great development potential in the field of low-power, small-size optoelectronic devices in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of the cross-sectional structure of the negative capacitance tunneling phototransistor of the present invention;

[0029] Figure 2 is a schematic diagram of the operation of the negative capacitance tunneling phototransistor under ferroelectric control, wherein V G is the gate voltage, V SD is the source-drain bias voltage;

[0030] Figure 3 Schematic diagram of the equivalent capacitance of the negative capacitance tunneling phototransistor under ferroelectric control, where Ψ S Low-dimensional semiconductor channel surface potential, C S Low-dimensional semiconductor channel capacitance, C ox Gate hafnium oxide dielectric capacitance, C Fe Ferroelectric gate dielectric capacitor with negative capacitance effect;

[0031] Figure 4 The electrical characteristic diagram of the negative capacitance tunneling phototransistor described in Example 1, the source-drain bias voltage is 0.2V, wherein a is the electrical transfer characteristic curve, and b is the calculated value of the subthreshold swing of the electrical transfer characteristic curve;

[0032] Figure 5 : is a photoelectric response characteristic diagram of the negative capacitance tunneling phototransistor under different incident light powers of Example 1 (the incident light wavelength is 520nm), wherein a is the output characteristic curve of the negative capacitance tunneling phototransistor under different incident light powers, b is the responsivity of the negative capacitance tunneling phototransistor under different incident light powers, and c is the response time of the negative capacitance tunneling phototransistor under the action of a 520nm laser;

[0033] Among them, 1-substrate, 2-oxide layer, 3-gate electrode layer, 4-hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, 5-oxide gate dielectric layer, 6-first low-dimensional semiconductor material, 7-second low-dimensional semiconductor material, 8-metal source electrode, 9-metal drain electrode. DETAILED DESCRIPTION

[0034] The present invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, an oxide gate dielectric layer and a low-dimensional semiconductor material heterojunction layer which are sequentially stacked;

[0035] The low-dimensional semiconductor material heterojunction layer comprises a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same level;

[0036] The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer;

[0037] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0038] It also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0039] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface.

[0040] In the present invention, the substrate is preferably a P-type doped silicon substrate, and the P-type doping concentration of the P-type doped silicon substrate is preferably 4 to 9×10 19 cm -3 , more preferably 4 to 6×10 19 cm -3 , the most preferred is 4×10 19 cm -3 In the present invention, the thickness of the substrate is preferably 270-550 nm, more preferably 280-290 nm, and most preferably 285 nm. In the present invention, the role of selecting P-type doping in the substrate is to control the carrier type of the substrate and adjust the conductivity of the substrate.

[0041] In the present invention, the material of the oxide layer is preferably silicon dioxide or hafnium oxide, more preferably silicon dioxide. In the present invention, the thickness of the oxide layer is preferably 270 to 300 nm, more preferably 280 to 290 nm, and most preferably 285 nm. In the present invention, the oxide layer serves as an insulating layer and a material growth platform.

[0042] In the present invention, the material of the gate electrode layer is preferably titanium nitride or tantalum nitride, more preferably titanium nitride. In the present invention, the thickness of the gate electrode layer is preferably 30 to 50 nm, more preferably 35 to 45 nm, and most preferably 40 nm. In the present invention, the function of the gate electrode layer is to apply a gate voltage to the device.

[0043] In the present invention, the material of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is preferably a doped hafnium oxide-based ferroelectric material; the doping element of the doped hafnium oxide-based ferroelectric material is preferably one or more of zirconium, silicon, yttrium and aluminum, and more preferably zirconium; when the doping element is two or more of the above-mentioned specific elements, the present invention does not have any special restrictions on the ratio of the above-mentioned specific substances, and they can be mixed in any ratio. In the present invention, the molar amount of hafnium and the doping element in the doped hafnium oxide-based ferroelectric material is preferably 1: (0.7-1), more preferably 1: (0.8-1), and most preferably 1: 1. In the present invention, the thickness of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is preferably 5-10nm, more preferably 6-9nm, and most preferably 7-8nm. In the present invention, based on the consideration of the required ferroelectric properties of the ferroelectric thin film, the device structure and the realization of high-sensitivity photoelectric detection function at room temperature, the above-mentioned doped hafnium oxide-based ferroelectric material is selected as the ferroelectric gate dielectric layer. The hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect has the advantages of ultra-thin thickness, semiconductor process compatibility and environmental friendliness, and the ferroelectric localized electrostatic field, ferroelectric materials have negative capacitance effect, and ferroelectric field effect transistors have voltage amplification effect; using the hafnium oxide-based ferroelectric gate electrolyte as the gate electrolyte layer of the tunneling field effect transistor can effectively amplify the channel potential and improve device performance. When illuminated, the photoexcited carrier base is transmitted through the tunnel effect, which can achieve rapid light response.

[0044] In the present invention, the material of the oxide gate dielectric layer is preferably hafnium oxide and / or aluminum oxide, more preferably hafnium oxide. In the present invention, the thickness of the oxide gate dielectric layer is preferably 10 to 14 nm. In the present invention, the oxide gate dielectric layer matches the capacitance of the hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, improves the interface, and further reduces the hysteresis in the subthreshold region of the device transfer characteristics, thereby improving the device performance.

[0045] In the present invention, the first low-dimensional semiconductor material is preferably a transition metal chalcogenide, and the transition metal chalcogenide is preferably rhenium sulfide; the thickness of the first low-dimensional semiconductor material is preferably a monolayer thickness of 15 nm, more preferably 6 to 10 nm.

[0046] In the present invention, the second low-dimensional semiconductor material is preferably a two-dimensional black phosphorus material and / or a two-dimensional purple phosphorus material, more preferably a two-dimensional black phosphorus material. In the present invention, the thickness of the second low-dimensional semiconductor material is preferably 10 to 40 nm, more preferably 15 to 20 nm, and the thickness of the second low-dimensional semiconductor material is greater than the thickness of the first low-dimensional semiconductor material.

[0047] In the present invention, the function of the low-dimensional semiconductor heterojunction formed between the first low-dimensional semiconductor material and the second low-dimensional semiconductor material is to form a gap-type heterojunction with a tunnel effect to construct a tunneling channel.

[0048] In the present invention, the metal source electrode and the metal drain electrode preferably include a chromium electrode layer and a gold electrode layer stacked in sequence, the thickness of the chromium electrode layer is preferably 10 to 15 nm, and the thickness of the gold electrode layer is preferably 30 to 50 nm. In the present invention, the function of the metal source electrode and the metal drain electrode is to apply a source-drain bias voltage to the device.

[0049] The present invention also provides a method for preparing the negative capacitance tunneling phototransistor described in the above technical solution, comprising the following steps:

[0050] An oxide layer is prepared on the surface of the substrate by thermal oxidation;

[0051] Depositing a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer having a negative capacitance effect, and an oxide gate dielectric layer in sequence on the surface of the oxide layer;

[0052] Using a mechanical lift-off transfer method, a low-dimensional semiconductor heterojunction layer is prepared on the second surface and the third surface of the oxide gate dielectric layer;

[0053] A metal drain electrode is prepared on the first surface of the oxide gate dielectric layer, and a metal source electrode is prepared on the fourth surface of the oxide gate dielectric layer, and both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

[0054] The invention uses a thermal oxidation method to prepare an oxide layer on the surface of a substrate.

[0055] The present invention does not have any special limitation on the process of preparing the oxide layer by the thermal oxidation method, and the process can be carried out using a process well known to those skilled in the art.

[0056] After the oxide layer is obtained, the present invention sequentially deposits a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, and an oxide gate dielectric layer on the surface of the oxide layer.

[0057] In the present invention, the gate electrode layer is preferably deposited by ion beam sputtering. The present invention does not have any special limitation on the ion beam sputtering process, and the process well known to those skilled in the art can be used.

[0058] In the present invention, the deposition method of the hafnium oxide-based ferroelectric gate electrode with negative capacitance effect is preferably atomic layer deposition. The present invention has no special limitation on the atomic layer deposition process, and the process well known to those skilled in the art can be used.

[0059] In the present invention, the deposition method of the oxide gate dielectric layer is preferably atomic layer deposition. The present invention has no special limitation on the process of atomic layer deposition, and the process well known to those skilled in the art can be used.

[0060] After the oxide gate dielectric layer is obtained, the present invention adopts a mechanical lift-off transfer method to prepare a low-dimensional semiconductor heterojunction layer on the second surface and the third surface of the oxide gate dielectric layer.

[0061] The present invention does not have any special limitation on the process of mechanical peeling and transfer, and the process well known to those skilled in the art can be used.

[0062] After obtaining the low-dimensional semiconductor heterojunction layer, the present invention prepares a metal drain electrode on the first surface of the oxide gate dielectric layer, and prepares a metal source electrode on the fourth surface of the oxide gate dielectric layer, and both the metal drain electrode and the metal source electrode form ohmic contact with the low-dimensional semiconductor heterojunction layer.

[0063] In the present invention, the preparation method of the metal drain electrode and the metal source electrode is preferably prepared by electron beam etching combined with thermal evaporation and stripping process or by ultraviolet lithography combined with thermal evaporation and stripping process; the present invention does not have any special limitation on the above method, and the method familiar to those skilled in the art can be used.

[0064] The present invention also provides the application of the negative capacitance tunneling phototransistor described in the above technical solution or the negative capacitance tunneling phototransistor prepared by the preparation method described in the above technical solution in the field of optoelectronics. The present invention does not have any special limitation on the method of the application, and the method well known to those skilled in the art can be used.

[0065] The negative capacitance tunneling phototransistor and its preparation method and application provided by the present invention are described in detail below in conjunction with the embodiments, but they should not be understood as limiting the protection scope of the present invention.

[0066] Example 1

[0067] like Figure 1 As shown, the negative capacitance tunneling phototransistor includes a substrate stacked in sequence (a P-type doped silicon substrate with a thickness of 550 nm and a P-type doping concentration of 4×10 19 cm -3 ), oxide layer (285nm thick silicon dioxide layer), gate electrode layer (40nm thick titanium nitride gate electrode layer), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (10nm thick Hf 0.5 Zr 0.5 O 2 Thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 10nm) and low-dimensional semiconductor material heterojunction layer;

[0068] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multi-layer rhenium disulfide with a thickness of 14 nm) and a second low-dimensional semiconductor material (the material is a two-dimensional black phosphorus material with a thickness of 30 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same level;

[0069] The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer;

[0070] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0071] It also includes a metal source electrode (a chromium metal layer with a thickness of 15 nm and a gold metal layer with a thickness of 50 nm stacked in sequence) and a metal drain electrode (a chromium metal layer with a thickness of 15 nm and a gold metal layer with a thickness of 50 nm stacked in sequence); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0072] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode is in contact with the first surface;

[0073] The preparation method of the negative capacitance tunneling phototransistor:

[0074] A silicon dioxide layer is prepared on the surface of a P-type doped silicon substrate by a thermal oxidation method;

[0075] Depositing a titanium nitride gate electrode layer on the surface of the silicon dioxide layer by ion beam sputtering;

[0076] At a substrate temperature of 280°C, Hf[N(C 2 H 5 )CH 3 ] 4 、Zr[N(C 2 H 5 )CH 3 ] 4 and water were used as Hf, Zr and O sources, respectively, and a cycle of HfO 2 and a cyclic ZrO 2 The element composition was controlled and rapid annealing was performed in a nitrogen environment at 500°C for 60 seconds to ensure the crystallization characteristics of the ferroelectric grinding, thereby growing a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect on the gate electrode (Hf with a thickness of 10 nm). 0.5 Zr 0.5 O 2 film);

[0077] Depositing a hafnium oxide gate dielectric layer with a thickness of 10 nm on the surface of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect by an atomic layer deposition process;

[0078] Using a mechanical lift-off transfer method, transferring the low-dimensional semiconductor material heterojunction to the second surface and the third surface of the hafnium oxide gate dielectric layer;

[0079] A pattern of a metal drain electrode is prepared on the first surface of the oxide gate dielectric layer by using ultraviolet lithography technology, a pattern of a metal source electrode is prepared on the fourth surface of the oxide gate dielectric layer by using exposure and development technology, a metal electrode (including a chromium electrode layer with a thickness of 15 and a gold electrode layer with a thickness of 50 stacked in sequence) is prepared on the sample after the ultraviolet lithography operation by using thermal evaporation technology, and after completing the evaporation of the metal electrode, the metal film is peeled off by combining a stripping method to obtain a metal source electrode and a metal drain electrode.

[0080] Figure 2 Schematic diagram of the operation of the negative capacitance tunneling phototransistor under ferroelectric control, where the gate voltage V G Applied to the gate electrode layer and the metal source electrode grounded, the source-drain bias voltage V SD Applied to the metal drain electrode; the equivalent capacitance diagram of the negative capacitance tunneling phototransistor is as follows Figure 3 As shown, S is the surface potential of the low-dimensional semiconductor heterojunction, CS is the low-dimensional semiconductor heterojunction channel capacitance, C ox is the gate hafnium oxide dielectric capacitance, C Fe is a ferroelectric gate dielectric capacitor doped with zirconium hafnium oxide;

[0081] Electrical test: A small constant bias voltage of 0.2V is applied between the source and drain to detect the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes. Then the gate voltage scanning range is set to -2V to 2V, and the gate voltage scanning direction is from negative to positive and then to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 are measured to determine the cut-off voltage; the test results are as follows: Figure 4 As shown, a is the electrical transfer characteristic curve, b is the calculated value of the subthreshold swing of the electrical transfer characteristic curve, Figure 4 It can be seen that Figure 4 The forward and reverse transfer characteristics of the device almost completely overlap, the subthreshold swing is less than 60mV / dec, the minimum value reaches 13.4mV / dec, and the maximum switching ratio of the device reaches 10 6 It can be seen that the negative capacitance tunneling phototransistor under the control of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect described in the present invention can achieve electrical transfer characteristics with no hysteresis, ultra-low subthreshold swing, and high switching ratio;

[0082] Photoelectric response test: The working gate voltage of the negative capacitance tunneling phototransistor described in Example 1 is set to V g = 0V, the voltage sweep range between the metal source electrode and the metal drain electrode is set from 0V to 1V. The test results are as follows Figure 5 As shown, a is the output characteristic curve under different incident light powers, b is the responsivity of the negative capacitance tunneling phototransistor under different incident light powers, and c is the response time under the action of 520nm laser. Figure 5 It can be seen that when a certain power laser with a wavelength of 520nm is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of the incident light power. When the incident light power is 14nW, the light response of the negative capacitance tunneling phototransistor is as high as 41A / W, showing extremely high light response sensitivity, and the response time is 8μs at this time.

[0083] Example 2

[0084] The negative capacitance tunneling phototransistor includes a substrate stacked in sequence (a P-type doped silicon substrate with a thickness of 500 nm and a P-type doping concentration of 4×10 19 cm -3), oxide layer (270nm thick silicon dioxide layer), gate electrode layer (30nm thick titanium nitride gate electrode layer), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (10nm thick Hf 0.93 Zr 0.07 O 2 Thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 12nm) and low-dimensional semiconductor material heterojunction layer;

[0085] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multi-layer rhenium disulfide with a thickness of 10 nm) and a second low-dimensional semiconductor material (the material is a two-dimensional black phosphorus material with a thickness of 25 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same level;

[0086] The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer;

[0087] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0088] It also includes a metal source electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked in sequence) and a metal drain electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked in sequence); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0089] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface.

[0090] Preparation method reference example 1;

[0091] Electrical test: A small constant bias voltage of 0.2V is applied between the source and drain to detect the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes. The gate voltage scanning range is set to -2V to 2V, and the gate voltage scanning direction is from negative to positive and then to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 are measured to determine the cut-off voltage; the forward and reverse curves of the transfer characteristics are almost completely overlapped, the subthreshold region swing is less than 60mV / dec, and the maximum switching ratio of the device reaches 10 6 It can be seen that the negative capacitance tunneling phototransistor under the control of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect described in the present invention can achieve electrical transfer characteristics with no hysteresis, ultra-low subthreshold swing, and high switching ratio;

[0092] Photoelectric response test: The working gate voltage of the negative capacitance tunneling phototransistor is set to V g = 0V, and the voltage scanning range between the metal source electrode and the metal drain electrode is set from 0V to 1V. When a laser with a wavelength of 520nm and a certain power is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of the incident light power, and the response speed is significantly improved.

[0093] Example 3

[0094] The negative capacitance tunneling phototransistor includes a substrate stacked in sequence (a P-type doped silicon substrate with a thickness of 550 nm and a P-type doping concentration of 4×10 19 cm -3 ), oxide layer (270nm thick silicon dioxide layer), gate electrode layer (30nm thick titanium nitride gate electrode layer), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (10nm thick Hf 0.93 Zr 0.07 O 2 Thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 14nm) and low-dimensional semiconductor material heterojunction layer;

[0095] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multi-layer rhenium disulfide with a thickness of 10 nm) and a second low-dimensional semiconductor material (the material is a two-dimensional black phosphorus material with a thickness of 40 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material have the same level;

[0096] The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer;

[0097] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0098] It also includes a metal source electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked in sequence) and a metal drain electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked in sequence); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0099] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface.

[0100] Preparation method reference example 1;

[0101] Electrical test: A small constant bias voltage of 0.2V is applied between the source and drain to detect the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes. The gate voltage scanning range is set to -2V to 2V, and the gate voltage scanning direction is from negative to positive and then to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 are measured to determine the cut-off voltage; the forward and reverse curves of the transfer characteristics are almost completely overlapped, the subthreshold region swing is less than 60mV / dec, and the maximum switching ratio of the device reaches 10 6 It can be seen that the negative capacitance tunneling phototransistor under the control of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect described in the present invention can achieve electrical transfer characteristics with no hysteresis, ultra-low subthreshold swing, and high switching ratio;

[0102] Photoelectric response test: The working gate voltage of the negative capacitance tunneling phototransistor is set to V g = 0V, and the voltage scanning range between the metal source electrode and the metal drain electrode is set from 0V to 1V. When a laser with a wavelength of 520nm and a certain power is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of the incident light power, and the response speed is significantly improved.

[0103] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A negative capacitance tunneling phototransistor, characterized in that: It includes a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, an oxide gate dielectric layer and a low-dimensional semiconductor material heterojunction layer which are stacked in sequence; The low-dimensional semiconductor material heterojunction layer comprises a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; A portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and a lower surface of the first low-dimensional semiconductor material and a lower surface of the second low-dimensional semiconductor material are at the same level; The surface of the oxide gate dielectric layer is divided into a first surface, a second surface, a third surface and a fourth surface in sequence, and the first surface and the fourth surface are located outside the surface of the oxide gate dielectric layer; The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface; Also including a metal source electrode and a metal drain electrode; The second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same level, and the lower surface of the metal source electrode is in contact with the fourth surface; The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same level, and the lower surface of the metal drain electrode contacts the first surface.

2. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The substrate is a P-type doped silicon substrate.

3. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The material of the oxide layer is silicon dioxide.

4. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The material of the gate electrode layer is titanium nitride.

5. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The material of the hafnium oxide-based ferroelectric gate dielectric layer having a negative capacitance effect is a doped hafnium oxide-based ferroelectric material; The doping element of the hafnium oxide-doped ferroelectric material is one or more of zirconium, silicon, yttrium and aluminum.

6. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The material of the oxide gate dielectric layer is hafnium oxide and / or aluminum oxide.

7. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The first low-dimensional semiconductor material is a transition metal chalcogenide; The second low-dimensional semiconductor material is a two-dimensional black phosphorus material.

8. The negative capacitance tunneling phototransistor according to claim 1, characterized in that: The metal source electrode and the metal drain electrode are both a chromium electrode and a gold electrode stacked in layers.

9. The method for preparing the negative capacitance tunneling phototransistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: An oxide layer is prepared on the surface of the substrate by thermal oxidation; Depositing a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer having a negative capacitance effect, and an oxide gate dielectric layer in sequence on the surface of the oxide layer; Using a mechanical lift-off transfer method, a low-dimensional semiconductor heterojunction layer is prepared on the second surface and the third surface of the oxide gate dielectric layer; A metal drain electrode is prepared on the first surface of the oxide gate dielectric layer, and a metal source electrode is prepared on the fourth surface of the oxide gate dielectric layer, and both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

10. Application of the negative capacitance tunneling phototransistor according to any one of claims 1 to 8 or the negative capacitance tunneling phototransistor prepared by the preparation method according to claim 9 in the field of optoelectronics.

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