High-reliability LED chip and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to a high-reliability LED chip and a preparation method thereof, and the preparation method comprises the following steps: forming an epitaxial wafer structure; etching the p-type semiconductor layer to the n-type semiconductor layer through a patterning etching process to form an n-type semiconductor mesa, the n-type semiconductor mesa being a concave curved surface; an n contact electrode is arranged on the concave surface of the n-type semiconductor mesa, and the n contact electrode is subjected to high-temperature annealing to form n-type ohmic contact; and arranging a p contact electrode on the p-type semiconductor layer, and performing high-temperature annealing on the p contact electrode to form p-type ohmic contact. According to the invention, the n-type semiconductor layer etching mesa is modified and designed, the n-type semiconductor layer etching mesa is etched into a concave curved surface, the area of the concave surface is larger than the projection area of the concave surface in the vertical direction, and the center of the concave surface is the deepest etched part, so that the specific contact resistivity is reduced, the transverse current guiding capability is improved, and the current distribution is improved; and the antistatic capability, the service life and the reliability of the device are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a high-reliability LED chip and a preparation method thereof. Background Art

[0002] As the most promising new light source, light emitting diodes (LEDs) have the characteristics of high luminous efficiency, low voltage, long life, small size, low energy consumption, green environmental protection, and short response time, and are widely used in lighting, display, polymer curing, sterilization, communication and other fields.

[0003] According to the different electrode positions, packaging forms, etc., LEDs are divided into normal LEDs, flip-chip LEDs, and vertical LEDs. In traditional normal LED chips, the p-electrode and n-electrode are on the same side of the LED chip and located on the light-emitting surface. The light-emitting surface of the flip-chip LED is the sapphire surface of the substrate, the n-electrode and the p-electrode are on the same side, and the electrode surface is at the bottom. The light is not blocked by the electrode, and the luminous efficiency is higher. The p-electrode is often designed as a reflective electrode, which further improves the light-emitting efficiency. At the same time, the flip-chip LED does not require leads, and the pad is directly connected to the packaging bracket. This connection method can reduce resistance, better heat dissipation, and is conducive to increasing the life of the device, making the flip-chip LED very popular in the application market.

[0004] LED is a device that uses III-V compounds to make P-type and N-type semiconductors through doping, and combines them into a PN junction as the core part. When the PN junction is forward biased and the electric field is large enough, the PN junction is turned on, holes are injected from the P region to the N region, and electrons are injected from the N region to the P region. In the quantum well region of the LED, radiation recombination of electron-hole pairs occurs and energy is released in the form of photons. For conventional forward-mounted LEDs and inverted LEDs, since the p-electrode and n-electrode are on the same side of the LED chip, when electrons are injected from the N region to the P region, Figure 1 As shown in Figure 2, it is easy to aggregate under the n-electrode and at the step corners, which reduces the device life. Figure 4 As shown, it may even cause ESD explosion points at the edge of the P region ( Figure 4 The circle in the middle is the ESD explosion point), which causes device degradation or even failure. Summary of the invention

[0005] In view of the technical problem that the current conventional technology usually does not optimize the design of the n-type semiconductor table, resulting in current congestion in the corner of the step and the area below the n-electrode, thereby affecting the reliability of the device, the present invention provides a high-reliability LED chip and a preparation method thereof.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for preparing a high-reliability LED chip comprises the following steps: S1. Growing an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, and a p-type semiconductor layer in sequence on a sapphire substrate to form an epitaxial wafer structure; S2, etching the p-type semiconductor layer to the n-type semiconductor layer through a patterned etching process to form an n-type semiconductor mesa, wherein the n-type semiconductor mesa is a concave curved surface; S3, disposing an n-type contact electrode on the concave surface of the n-type semiconductor table, and performing high-temperature annealing on the n-type contact electrode to form an n-type ohmic contact; S4. A p-type contact electrode is provided on the p-type semiconductor layer, and the p-type contact electrode is subjected to high-temperature annealing to form a p-type ohmic contact.

[0007] The thickness of the AlN buffer layer is 2800 nm, the thickness of the n-type semiconductor layer is 2800 nm, the thickness of the quantum well layer is 80 nm, and the thickness of the p-type semiconductor layer is 30 nm.

[0008] The concave surface area of ​​the n-type semiconductor mesa in S2 is larger than the projection area of ​​the concave surface in the vertical direction, and the center of the concave surface of the n-type semiconductor mesa is the deepest point of etching.

[0009] The etching depth of the n-type semiconductor mesa is 450 nm, and the thickness of the etched n-type semiconductor layer is 340 nm.

[0010] The method for setting the n-contact electrode in S3 is: using photoresist as a mask and using a metal evaporation machine to evaporate the n-contact electrode on the concave surface of the n-type semiconductor table.

[0011] The n-type contact electrode in S3 is a TiAlTiAu composite system with a thickness of 150 / 1200 / 300 / 400 Å.

[0012] The annealing atmosphere in S3 is nitrogen, the flow rate of nitrogen is 2000 sccm, the annealing temperature is 850° C., and the annealing time is 150 s.

[0013] The method for providing the p-type contact electrode in S4 is: using photoresist as a mask and using a metal evaporation machine to evaporate the p-type contact electrode on the p-type semiconductor layer.

[0014] The p-contact electrode in S4 is a NiAuNiAu laminated metal system with a thickness of 100 / 100 / 100 / 100Å; the annealing atmosphere is air, the annealing temperature is 550°C, and the annealing time is 360s.

[0015] A high-reliability LED chip comprises a sapphire substrate, an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, a p-type semiconductor layer, an n-type semiconductor table, an n-contact electrode and a p-contact electrode, wherein the AlN buffer layer is grown on the sapphire substrate, the n-type semiconductor layer is grown on the AlN buffer layer, the quantum well layer is grown on the n-type semiconductor layer, and the p-type semiconductor layer is grown on the quantum well layer; the p-type semiconductor layer is etched to the n-type semiconductor layer to expose the n-type semiconductor layer to form an n-type semiconductor table; the n-type semiconductor table presents a concave curved surface, an n-contact electrode is arranged on the concave surface of the n-type semiconductor table, and a p-contact electrode is arranged on the p-type semiconductor layer.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention redesigns the etching table of the n-type semiconductor layer to etch into a concave curved surface, wherein the area of ​​the concave surface is larger than the projection area of ​​the concave surface in the vertical direction, and the center of the concave surface is the deepest part of the etching, thereby reducing the specific contact resistivity, increasing the lateral current guiding capability, improving the current distribution, and enhancing the antistatic capability, service life and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0018] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0019] Figure 1 Schematic diagram of the chip structure of the control example; Figure 2 Schematic diagram of the structure of the epitaxial wafer of this embodiment; Figure 3 Schematic diagram of the chip structure of this embodiment; Figure 4 This is the back side image of a 20mil×20mil chip that has undergone ESD testing; Figure 5 This is a diagram showing the aging results of the lamp beads in this embodiment; Figure 6This is the aging result of the lamp beads in the control example.

[0020] Wherein: 101 is a sapphire substrate, 102 is an AlN buffer layer, 103 is an n-type semiconductor layer, 104 is a quantum well layer, 105 is a p-type semiconductor layer, 201 is an n-type semiconductor table, 202 is an n-contact electrode, and 203 is a p-contact electrode. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. These descriptions are only to further illustrate the features and advantages of the present invention, rather than to limit the claims of the present invention. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0023] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] The preparation method of the LED chip in this embodiment has the following specific steps: Step 1: Figure 2 As shown, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are sequentially grown on a sapphire substrate 101 to form an epitaxial wafer structure.

[0025] Preferably, the thickness of the epitaxial wafer AlN buffer layer 102 is 2800 nm, the thickness of the n-type semiconductor layer 103 is 2800 nm, the thickness of the quantum well layer is 80 nm, and the thickness of the p-type semiconductor layer 105 is 30 nm.

[0026] Step 2: Figure 3As shown, the n-type semiconductor mesa 201 is defined by photoresist, and the n-type semiconductor layer 103 is etched by ICP dry etching to expose the n-type semiconductor mesa 201. The n-type semiconductor mesa 201 is a concave surface, and the area of ​​the concave surface is larger than the projection area of ​​the concave surface in the vertical direction. The center of the concave surface is the deepest point of etching.

[0027] Preferably, the etching depth of the n-type semiconductor mesa 201 is 450 nm, which is the maximum etching depth at the lowest point of the concave surface. The thickness of the n-type semiconductor layer 103 etched away is 340 nm.

[0028] Step 3: Figure 3 As shown, a photoresist is used as a mask, and an n-contact electrode 202 is evaporated on the concave surface of the n-type semiconductor table 201 by a metal evaporator, and high-temperature annealing is performed to form an n-type ohmic contact.

[0029] Preferably, the n-type contact electrode is a TiAlTiAu composite system with a thickness of 150 / 1200 / 300 / 400 Å. The annealing atmosphere is nitrogen with a flow rate of 2000 sccm, an annealing temperature of 850°C, and a time of 150 s.

[0030] Step 4: Figure 3 As shown, a photoresist is used as a mask, and a p-type contact electrode 203 is evaporated on the p-type semiconductor layer 105 by a metal evaporator, and high-temperature annealing is performed to form a p-type ohmic contact.

[0031] Preferably, the p-contact electrode 203 is made of a NiAuNiAu laminated metal system with a thickness of 100 / 100 / 100 / 100 Å. The annealing atmosphere is air, the annealing temperature is 550° C., and the time is 360 s.

[0032] A high-reliability LED chip comprises a sapphire substrate 101, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, a p-type semiconductor layer 105, an n-type semiconductor table 201, an n-contact electrode 202 and a p-contact electrode 203. The AlN buffer layer 102 is grown on the sapphire substrate 101, the n-type semiconductor layer 103 is grown on the AlN buffer layer 102, the quantum well layer 104 is grown on the n-type semiconductor layer 103, and the p-type semiconductor layer 105 is grown on the quantum well layer 104. The p-type semiconductor layer 105 is etched to the n-type semiconductor layer 103 to expose the n-type semiconductor layer 103 to form an n-type semiconductor table 201. The n-type semiconductor table 201 is a concave curved surface. The n-contact electrode 202 is grown on the concave surface of the n-type semiconductor table 201, and the p-contact electrode 203 is grown on the p-type semiconductor layer 105.

[0033] Taking a 20×20mil chip as an example, the transmission line model (TLM) method was used to test the specific resistivity of the n-type ohmic contact of the control example and the present embodiment. The control example is a deep ultraviolet LED flip chip with a conventional structure in the prior art. The results are shown in Table 1. Compared with the control example, the specific contact resistivity of the present embodiment is reduced.

[0034] Table 1 Comparison of contact resistivity between control example and this embodiment (unit: Ω / cm 2 ) Specific contact resistivity Example 1.4×10-4 Comparison Example 2.1×10-4 The 2020mil chips of the embodiment and the control example were packaged into lamp beads using a 3535 bracket and equipped with a 12-17V (1020) Zener tube. The ESD test results are shown in Table 2. The average ESD value of the control example is 3880V, and the average ESD value of the embodiment is 6680V. The antistatic ability of the embodiment is improved, and the ESD explosion point is reduced.

[0035] Table 2 ESD test table of control example and this embodiment (unit: V) Zener tube model No. 1 No. 2 No. 3 No. 4 No. 5 No. 6 No. 7 No. 8 No. 9 No. 10 Example 12-17V（1020） 7000 7600 8000 8600 4400 5200 3600 4600 8400 9400 Comparison Example 12-17V（1020） 4400 4600 4200 3200 4600 3600 3600 3200 3600 3800 The 2020mil chips of the embodiment and the control example were packaged into lamp beads using a 3535 bracket and subjected to long-term aging at room temperature and 100mA current. Figure 5 , Figure 6 As shown, after aging to 1125 hours, the light maintenance rate of the embodiment is 83.1%, and the light maintenance rate of the control example is 78.3%. The life of the device in the embodiment is improved.

[0036] Only the preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention, and various changes should be included in the protection scope of the present invention.

Claims

1. A method for preparing a high-reliability LED chip, characterized in that: The following steps are involved: S1, sequentially growing an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), and a p-type semiconductor layer (105) on a sapphire substrate (101) to form an epitaxial wafer structure; S2, etching the p-type semiconductor layer (105) to the n-type semiconductor layer (103) through a patterned etching process to form an n-type semiconductor mesa (201), wherein the n-type semiconductor mesa (201) is a concave curved surface; S3, disposing an n-type contact electrode (202) on the concave surface of the n-type semiconductor table (201), and performing high-temperature annealing on the n-type contact electrode (202) to form an n-type ohmic contact; S4. A p-type contact electrode (203) is provided on the p-type semiconductor layer (105), and the p-type contact electrode (203) is subjected to high-temperature annealing to form a p-type ohmic contact.

2. A method for preparing a high-reliability LED chip according to claim 1, characterized in that: The thickness of the AlN buffer layer (102) is 2800 nm, the thickness of the n-type semiconductor layer (103) is 2800 nm, the thickness of the quantum well (104) layer is 80 nm, and the thickness of the p-type semiconductor layer (105) is 30 nm.

3. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The concave surface area of ​​the n-type semiconductor mesa (201) in S2 is larger than the projection area of ​​the concave surface in the vertical direction, and the center of the concave surface of the n-type semiconductor mesa (201) is the deepest point of etching.

4. A method for preparing a high-reliability LED chip according to claim 3, characterized in that: The etching depth of the n-type semiconductor mesa (201) is 450 nm, and the thickness of the etched n-type semiconductor layer (103) is 340 nm.

5. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The method for providing the n-type contact electrode (202) in S3 is: using photoresist as a mask and using a metal vapor deposition machine to vapor-deposit the n-type contact electrode (202) on the concave surface of the n-type semiconductor table (201).

6. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The n-type contact electrode (202) in S3 is selected to be a TiAlTiAu composite system with a thickness of 150 / 1200 / 300 / 400 Å.

7. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The annealing atmosphere in S3 is nitrogen, the flow rate of nitrogen is 2000 sccm, the annealing temperature is 850° C., and the annealing time is 150 s.

8. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The method for providing the p-type contact electrode (203) in S4 is: using photoresist as a mask and using a metal vapor deposition machine to vapor-deposit the p-type contact electrode (203) on the p-type semiconductor layer (105).

9. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The p-contact electrode (203) in S4 is a NiAuNiAu laminated metal system with a thickness of 100 / 100 / 100 / 100Å; the annealing atmosphere is air, the annealing temperature is 550°C, and the annealing time is 360s.

10. A high-reliability LED chip prepared by the method for preparing a high-reliability LED chip according to any one of claims 1 to 9, characterized in that: The invention comprises a sapphire substrate (101), an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), a p-type semiconductor layer (105), an n-type semiconductor table (201), an n-contact electrode (202) and a p-contact electrode (203), wherein the AlN buffer layer (102) is grown on the sapphire substrate (101), the n-type semiconductor layer (103) is grown on the AlN buffer layer (102), and the quantum well layer (104) is grown on the n-type semiconductor layer. (103), the p-type semiconductor layer (105) is grown on the quantum well layer (104), the p-type semiconductor layer (105) is etched to the n-type semiconductor layer (103), the n-type semiconductor layer (103) is exposed to form an n-type semiconductor table (201), the n-type semiconductor table (201) is a concave curved surface, an n-contact electrode (202) is arranged on the concave surface of the n-type semiconductor table (201), and a p-contact electrode (203) is arranged on the p-type semiconductor layer (105).

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