Annular voltage-controlled oscillator with low power supply sensitivity

Abstract

The invention provides an annular voltage-controlled oscillator with low power supply sensitivity. The annular voltage-controlled oscillator comprises a differential delay unit, a bias current controller and a voltage swing controller. The output frequency of the ring voltage-controlled oscillator is controlled by Ibias / Vswing. The low power supply sensitivity is realized by adjusting the ratio. In the bias current controller, a feedback amplifier 1 controls a bias current branch copied from a delay unit to generate a reference bias current, and a current generated by a compensation branch compensates a current related to a square term of a power supply, so that the reference bias current is changed along with the direct proportion of the power supply, and the change rate is small. In the voltage swing controller, a feedback amplifier 2 adjusts a bias voltage Vpbias to enable an output voltage of a delay unit to be equal to a reference voltage, and the voltage swing is limited between a power supply voltage and the reference voltage. Through the two adjusting mechanisms, Ibias and Vswing are both in direct proportion to the power supply, Ibias / Vswing is kept approximately constant, and low power supply sensitivity of the annular voltage-controlled oscillator is achieved.

Description

Technical Field

[0001] The invention relates to the technical field of low-power analog circuit design, and in particular to a ring voltage-controlled oscillator with low power supply sensitivity. Background Art

[0002] Ring oscillator is a basic and important oscillator circuit. It is composed of a series of inverters (or other types of delay units) connected end to end to form a closed loop. It uses the delay characteristics of the inverter to generate an oscillation signal. Due to its simple structure, small footprint and easy integration, it is widely used in clock generation units, phase-locked loops, and random number generators.

[0003] The earliest ring oscillator was based on the CMOS inverter structure, which uses a PMOS tube and an NMOS tube in series. When the two MOS tubes are working, they do not provide a direct DC path from the power supply to the ground. There is only a small leakage current, which reduces the static power consumption. However, since the structure adopts a single-ended design, the suppression ability of power supply noise and ground line noise is poor, and the oscillation frequency of the ring oscillator will change with the change of the power supply voltage. The differential delay unit structure adopts a symmetrical design, which improves the common-mode noise suppression capability and shows better phase noise performance. It is currently a widely used ring oscillator structure. However, with the reduction of process and the increase of integration, the phase noise and power consumption problems of the ring oscillator have become more prominent. In low-power design, a lower power supply voltage is usually used, but the low power supply voltage requires the circuit to have a lower power supply sensitivity. The original differential delay unit structure has poor power supply noise suppression ability under low power supply voltage conditions, resulting in more frequency deviations, and as the power supply voltage continues to decrease, the problem becomes more serious. Summary of the invention

[0004] The purpose of the present invention is to provide a ring voltage controlled oscillator structure with low power supply sensitivity to solve the defects of the prior art. The ring voltage controlled oscillator of the present invention adds a bias current controller and a voltage swing controller on the basis of a differential delay structure with a current source as a load, so as to compensate for the frequency change caused by the power supply voltage change and reduce the power supply sensitivity of the ring voltage controlled oscillator.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a ring voltage-controlled oscillator with low power supply sensitivity, characterized in that it includes a differential delay unit (1), a bias current controller (2), a voltage swing controller (3),

[0006] The differential delay unit (1) is configured in a differential input and differential output mode, the gate of the first NMOS tube (MN1) is a positive input terminal, the gate of the second NMOS tube (MN2) is a negative input terminal, the drains of the first NMOS tube (MN1) and the first PMOS tube (MP1) are negative output terminals, and the drains of the second PMOS tube (MP2) and the second NMOS tube (MN2) are positive output terminals;

[0007] The bias current controller (2) has a power supply voltage VDD as input signal and an output signal V nbias Used to adjust the bias current I of the differential delay unit (1) bias ;

[0008] The voltage swing controller (3) is based on the power supply voltage VDD and the output signal V nbias At the same time, the output signal V pbias Used to adjust the bias voltage of the first PMOS tube (MP1) and the second PMOS tube (MP2) in the differential delay unit (1).

[0009] Specifically, the differential delay unit (1) comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4).

[0010] The gate of the first PMOS tube (MP1) is connected to the gate of the second PMOS tube (MP2) and the output signal V of the voltage swing controller (3). pbias The drain of the first PMOS tube (MP1) is connected to the drain of the first NMOS tube (MN1) and outputs a voltage V out- , the source of the first PMOS tube (MP1) is connected to the power supply voltage (VDD);

[0011] The gate of the second PMOS tube (MP2) is connected to the gate of the first PMOS tube (MP1) and the output signal V of the voltage swing controller (3). pbias The drain of the second PMOS tube (MP2) is connected to the drain of the second NMOS tube (MN2) and outputs a voltage V out+ , the source of the second PMOS tube (MP2) is connected to the power supply voltage (VDD);

[0012] The gate of the first NMOS transistor (MN1) is connected to the differential input signal V in+ The drain of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1) and outputs a voltage V out-, the source of the first NMOS tube (MN1) is connected to the source of the second NMOS tube (MN2), the drain of the third NMOS tube (MN3) and the drain of the fourth NMOS tube (MN4);

[0013] The gate of the second NMOS transistor (MN2) is connected to the differential input signal V in- The drain of the second NMOS transistor (MN2) is connected to the drain of the second PMOS transistor (MP2) and outputs a voltage V out+ , the source electrode of the second NMOS tube (MN2) is connected to the source electrode of the first NMOS tube (MN1), the drain electrode of the third NMOS tube (MN3) and the drain electrode of the fourth NMOS tube (MN4);

[0014] The gate of the third NMOS tube (MN3) is connected to the output signal V of the bias current controller (2). nbias , the drain of the third NMOS tube (MN3) is connected to the source of the first NMOS tube (MN1), the source of the second NMOS tube (MN2) and the drain of the fourth NMOS tube (MN4), and the source of the third NMOS tube (MN3) is connected to the power ground (GND);

[0015] The gate of the fourth NMOS transistor (MN4) is connected to the input control signal V cont , a drain of the fourth NMOS tube (MN4) is connected to the source of the first NMOS tube (MN1), the source of the second NMOS tube (MN2) and the drain of the third NMOS tube (MN3), and a source of the fourth NMOS tube (MN4) is connected to a power ground (GND);

[0016] Specifically, the bias current controller (2) is used to generate the signal V nbias , including a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a seventh NMOS tube (MN7), an eighth NMOS tube (MN8), a ninth NMOS tube (MN9), a tenth NMOS tube (MN10), an eleventh NMOS tube (MN11), and a feedback amplifier 1,

[0017] The gate of the third PMOS tube (MP3) is connected to the drain of the third PMOS tube (MP3), the drain of the fifth NMOS tube (MN5) and the negative end of the feedback amplifier 1; the drain of the third PMOS tube (MP3) is connected to the gate of the third PMOS tube (MP3), the drain of the fifth NMOS tube (MN5) and the negative end of the feedback amplifier 1; the source of the third PMOS tube (MP3) is connected to the power supply voltage (VDD);

[0018] The gate of the fourth PMOS tube (MP4) is connected to the power ground (GND), the drain of the fourth PMOS tube (MP4) is connected to the drain of the sixth NMOS tube (MN6), the drain of the eighth NMOS tube (MN8) and the positive terminal of the feedback amplifier 1, and the current in the fourth PMOS tube (MP4) is I tot , the source of the fourth PMOS tube (MP4) is connected to the power supply voltage (VDD);

[0019] The gate of the fifth PMOS tube (MP5) is connected to the drain of the fifth PMOS tube (MP5), the gate of the ninth NMOS tube (MN9) and the drain of the tenth NMOS tube (MN10); the drain of the fifth PMOS tube (MP5) is connected to the gate of the fifth PMOS tube (MP5), the gate of the ninth NMOS tube (MN9) and the drain of the tenth NMOS tube (MN10); and the source of the fifth PMOS tube (MP5) is connected to the power supply voltage (VDD);

[0020] The gate of the fifth NMOS transistor (MN5) is connected to the power supply voltage (VDD), the source of the fifth NMOS transistor (MN5) is connected to the power ground (GND), and the drain of the fifth NMOS transistor (MN5) is connected to the gate and drain of the third PMOS transistor (MP3) and connected to the negative terminal of the feedback amplifier 1;

[0021] The gate of the sixth NMOS transistor (MN6) is connected to the power supply voltage (VDD), the drain of the sixth NMOS transistor (MN6) is connected to the drain of the fourth PMOS transistor (MP4), the drain of the eighth NMOS transistor (MN8) and the positive terminal of the feedback amplifier 1, and the source of the sixth NMOS transistor (MN6) is connected to the drain of the seventh NMOS transistor (MN7);

[0022] The gate of the seventh NMOS tube (MN7) is connected to the output end of the feedback amplifier 1, the drain of the seventh NMOS tube (MN7) is connected to the source of the sixth NMOS tube (MN6), the source of the seventh NMOS tube (MN7) is connected to the power ground (GND), and the current in the seventh NMOS tube (MN7) is I bias ;

[0023] The gate of the eighth NMOS transistor (MN8) is connected to the power supply voltage (VDD), the drain of the eighth NMOS transistor (MN8) is connected to the drain of the fourth PMOS transistor (MP4), the drain of the sixth NMOS transistor (MN6) and the positive terminal of the feedback amplifier 1, and the source of the eighth NMOS transistor (MN8) is connected to the drain of the ninth NMOS transistor (MN9);

[0024] The gate of the ninth NMOS tube (MN9) is connected to the gate and drain of the fifth PMOS tube (MP5) and the drain of the tenth NMOS tube (MN10), the gate voltage is V2, the drain of the ninth NMOS tube (MN9) is connected to the source of the eighth NMOS tube (MN8), the source of the ninth NMOS tube (MN9) is connected to the power ground (GND), and the current in the ninth NMOS tube (MN9) is I comp ;

[0025] The gate of the tenth NMOS tube (MN10) is connected to the power supply voltage (VDD), the source of the tenth NMOS tube (MN10) is connected to the gate and drain of the eleventh NMOS tube (MN11), and the drain of the tenth NMOS tube (MN10) is connected to the gate and drain of the fifth PMOS tube (MP5) and the gate of the ninth NMOS tube (MN9);

[0026] The gate of the eleventh NMOS tube (MN11) is connected to the source of the tenth NMOS tube (MN10) and the drain of the eleventh NMOS tube (MN11), the source of the eleventh NMOS tube (MN11) is connected to the power ground (GND), and the drain of the eleventh NMOS tube (MN11) is connected to the source of the tenth NMOS tube (MN10) and the gate of the eleventh NMOS tube (MN11);

[0027] The positive input terminal of the feedback amplifier 1 is connected to the drain of the fourth PMOS tube (MP4), the drain of the sixth NMOS tube (MN6) and the drain of the eighth NMOS tube (MN8), and the input voltage is V3; the negative input terminal of the feedback amplifier 1 is connected to the gate and drain of the third PMOS tube (MP3) and the drain of the fifth NMOS tube (MN5), and the input voltage is V1; the output terminal of the feedback amplifier 1 is connected to the gate of the seventh NMOS tube (MN7), the gate of the third NMOS tube (MN3) in the differential delay unit (1) and the gate of the fourteenth NMOS tube (MN14) in the voltage swing controller (3), and the output voltage is V nbias ;

[0028] Specifically, the voltage swing controller (3) is used to generate the signal V pbias , including a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a twelfth NMOS tube (MN12), a thirteenth NMOS tube (MN13), a fourteenth NMOS tube (MN14), a fifteenth NMOS tube (MN15), and a feedback amplifier 2,

[0029] The gate of the sixth PMOS tube (MP6) is connected to the power ground (GND), the drain of the sixth PMOS tube (MP6) is connected to the gate and drain of the twelfth NMOS tube (MN12) and connected to the positive terminal of the feedback amplifier 2, and the source of the sixth PMOS tube (MP6) is connected to the power supply voltage (VDD);

[0030] The gate of the seventh PMOS transistor (MP7) is connected to the output end of the feedback amplifier 2, the drain of the seventh PMOS transistor (MP7) is connected to the drain of the thirteenth NMOS transistor (MN13) and connected to the negative end of the feedback amplifier 2, and the source of the seventh PMOS transistor (MP7) is connected to the power supply voltage (VDD);

[0031] The gate of the twelfth NMOS tube (MN12) is connected to the drain of the sixth PMOS tube (MP6), the drain of the twelfth NMOS tube (MN12) and the positive terminal of the feedback amplifier 2; the drain of the twelfth NMOS tube (MN12) is connected to the drain of the sixth PMOS tube (MP6), the gate of the twelfth NMOS tube (MN12) and the positive terminal of the feedback amplifier 2; the source of the twelfth NMOS tube (MN12) is connected to the power ground (GND);

[0032] The gate of the thirteenth NMOS transistor (MN13) is connected to the power supply voltage (VDD), the drain of the thirteenth NMOS transistor (MN13) is connected to the drain of the seventh PMOS transistor (MP7) and connected to the negative terminal of the feedback amplifier 2, and the source of the thirteenth NMOS transistor (MN13) is connected to the drain of the fourteenth NMOS transistor (MN14) and the drain of the fifteenth NMOS transistor (MN15);

[0033] The gate of the fourteenth NMOS tube (MN14) is connected to the output end of the feedback amplifier 1 in the bias current controller (2), the drain of the fourteenth NMOS tube (MN14) is connected to the source of the thirteenth NMOS tube (MN13) and the drain of the fifteenth NMOS tube (MN15), and the source of the fourteenth NMOS tube (MN14) is connected to the power ground (GND);

[0034] The gate of the fifteenth NMOS transistor (MN15) is connected to the input control signal V cont , the drain of the fifteenth NMOS tube (MN15) is connected to the source of the thirteenth NMOS tube (MN13) and the drain of the fourteenth NMOS tube (MN14), and the source of the fifteenth NMOS tube (MN15) is connected to the power ground (GND);

[0035] The positive input end of the feedback amplifier 2 is connected to the drain of the sixth PMOS tube (MP6), the gate and drain of the twelfth NMOS tube (MN12), and the input voltage is V4; the negative input end of the feedback amplifier 2 is connected to the drain of the seventh PMOS tube (MP7), the drain of the thirteenth NMOS tube (MN13), and the input voltage is V5; the output end of the feedback amplifier 2 is connected to the gate of the seventh PMOS tube (MP7), the gates of the first PMOS tube (MP1) and the second PMOS tube (MP2) in the differential delay unit (1), and the output voltage is V pbias .

[0036] Through the above technical solution, compared with the prior art, the present invention can achieve the following beneficial effects:

[0037] The present invention is based on 0.13-μm CMOS technology. On the basis of the differential delay structure with a current source as the load, a bias current controller and a voltage swing controller are added. The bias current and the voltage swing jointly compensate for the frequency change caused by the change of the power supply voltage, so that the ratio of the bias current to the voltage swing remains constant, thereby reducing the power supply sensitivity. It has been verified that under a power supply voltage of 1.2V, the output frequency of the ring voltage controlled oscillator without the bias current controller and the voltage swing controller changes by ±2.5% under a power supply voltage change of ±5%, while the output frequency of the ring voltage controlled oscillator with the bias current controller and the voltage swing controller changes by only ±0.225% under a power supply voltage change of ±5%. Compared with Chinese patent CN101546984A, the patent uses a current mirror and a feedback amplifier to respectively copy the bias current and the lower limit output voltage to act on the off-chip resistor so as to keep the ratio of the bias current to the output voltage swing constant, and the oscillation frequency depends on the off-chip resistor. The present invention uses a bias current controller and a voltage swing controller to keep the ratio of the bias current to the output voltage swing constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the overall structure of a ring voltage-controlled oscillator for reducing power supply sensitivity provided by an embodiment of the present invention.

[0039] Figure 2 This is the circuit diagram of the bias current controller.

[0040] Figure 3 This is the circuit diagram of the voltage swing controller.

[0041] Figure 4 Define the graph for the input-output characteristics and delay time of the inverter.

[0042] Description of the reference numerals: differential delay unit 1, bias current controller 2, voltage swing controller 3. DETAILED DESCRIPTION

[0043] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0044] The present invention proposes a ring voltage-controlled oscillator with reduced power supply sensitivity, based on a differential delay unit with a current source as a load, using a bias current controller and a voltage swing controller to detect power supply changes, and adjust the bias current and voltage swing to maintain I bias With V swing The ratio remains constant relative to the power supply, thereby reducing the power supply sensitivity of the ring voltage controlled oscillator.

[0045] like Figure 1 The figure shows the overall block diagram of the ring voltage controlled oscillator structure proposed by the present invention, which includes a differential delay unit (1), a bias current controller (2), and a voltage swing controller (3). The ring voltage controlled oscillator is composed of an odd number N of differential delay units connected in series, wherein the V out+ Connect the next level V in- , the previous level V out- Connect the next level V in+ ; The input signal of the bias current controller (2) is the power supply voltage VDD, and the output signal V nbias Used to adjust the bias current I of the differential delay unit (1) bias The input signal of the voltage swing controller (3) is the power supply voltage VDD and the output signal V of the bias current controller (2). nbias , output signal V pbias The invention is used for adjusting the bias voltage of the first PMOS tube (MP1) and the second PMOS tube (MP2) in the differential delay unit (1). The bias current controller and the voltage swing controller are used to detect the power supply change, and the bias current and the voltage swing are adjusted to keep the ratio of the two constant, thereby reducing the power supply sensitivity of the ring voltage controlled oscillator.

[0046] The differential delay cell (1) uses a differential input V in+ 、V in- , generating a differential output V out+ 、V out- ,like Figure 1 A delay differential unit implementation structure is provided, comprising a first PMOS tube (MP1), a second PMOS tube (MP2), a first NMOS tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), and a fourth NMOS tube (MN4), wherein the gate of the first PMOS tube (MP1) is connected to the gate of the second PMOS tube (MP2) and the output signal V of the voltage swing controller (3). pbias The drain of the first PMOS tube (MP1) is connected to the drain of the first NMOS tube (MN1) and outputs a voltage V out-The source of the first PMOS tube (MP1) is connected to the power supply voltage (VDD); the gate of the second PMOS tube (MP2) is connected to the gate of the first PMOS tube (MP1) and the output signal V pbias The drain of the second PMOS tube (MP2) is connected to the drain of the second NMOS tube (MN2) and outputs a voltage V out+ The source of the second PMOS transistor (MP2) is connected to the power supply voltage (VDD); the gate of the first NMOS transistor (MN1) is connected to the differential input signal V in+ The drain of the first NMOS tube (MN1) is connected to the drain of the first PMOS tube (MP1) and outputs a voltage V out- The source of the first NMOS tube (MN1) is connected to the source of the second NMOS tube (MN2), the drain of the third NMOS tube (MN3) and the drain of the fourth NMOS tube (MN4); the gate of the second NMOS tube (MN2) is connected to the differential input signal V in- The drain of the second NMOS transistor (MN2) is connected to the drain of the second PMOS transistor (MP2) and outputs a voltage V out+ The source of the second NMOS tube (MN2) is connected to the source of the first NMOS tube (MN1), the drain of the third NMOS tube (MN3) and the drain of the fourth NMOS tube (MN4); the gate of the third NMOS tube (MN3) is connected to the output signal V of the bias current controller (2). nbias The drain of the third NMOS tube (MN3) is connected to the source of the first NMOS tube (MN1), the source of the second NMOS tube (MN2) and the drain of the fourth NMOS tube (MN4); the source of the third NMOS tube (MN3) is connected to the power ground (GND); the gate of the fourth NMOS tube (MN4) is connected to the input control signal V cont , the drain of the fourth NMOS tube (MN4) is connected to the source of the first NMOS tube (MN1), the source of the second NMOS tube (MN2) and the drain of the third NMOS tube (MN3), and the source of the fourth NMOS tube (MN4) is connected to the power ground (GND); the obtained differential signal V out+ 、V out- In phase with V in- 、V in+ The phase difference is 180° and the delay time is τ. In order to derive the output frequency of the oscillator, the following first studies the input and output characteristics of a simple inverter. Figure 4 As shown, for the convenience of analysis, it is assumed that the input is an ideal step pulse and V av Equal to V OH With V OL The average value of τ PHL represents the fall time, τ PLHrepresents the rise time, then the total delay τ of the inverter is τ PHL With τ PLH The average value of the ring oscillator is

[0047]

[0048] Assume that the charging current and discharging current of the output node are equal, both I, and the rise time τ PLH and the fall time τ PHL It can be expressed as

[0049]

[0050] Combining the above three formulas, we get

[0051]

[0052] V OH With V OL The difference is the output voltage swing, so the ring oscillator composed of an odd number N of these differential delay units connected end to end has an oscillation frequency of

[0053]

[0054] Where N is the number of ring oscillators, I bias is the bias current of the delay unit, C total is the total load capacitance of the delay unit, V swing is the output voltage swing of the delay unit. Power supply changes will affect I bias , C total and V swing , thus causing the oscillation frequency to shift. total It is relatively fixed and less affected by the power supply. According to the expression of the oscillation frequency, if the bias current I bias and voltage swing V swing The ratio of is set to be independent of the power supply voltage, so that the output frequency of the ring oscillator is insensitive to the power supply voltage fluctuation. Therefore, the idea of ​​the present invention is to use two controllers to detect the change of the power supply voltage and appropriately compensate for the I caused by the change of the power supply voltage. bias and V swing Changes, keep I bias / V swing Relatively constant to reduce the sensitivity of the oscillation frequency to the power supply. The principle analysis of the two controllers is as follows.

[0055] The circuit diagram of the bias current controller (2) is shown in Figure 2As shown, it includes a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a seventh NMOS tube (MN7), an eighth NMOS tube (MN8), a ninth NMOS tube (MN9), a tenth NMOS tube (MN10), an eleventh NMOS tube (MN11), and a feedback amplifier 1, wherein the gate of the third PMOS tube (MP3) is connected to the drain of the third PMOS tube (MP3), the drain of the fifth NMOS tube (MN5) and is connected to the feedback amplifier 1. The negative end of the feedback amplifier 1 is connected to the drain of the third PMOS tube (MP3), the drain of the fifth NMOS tube (MN5) and the negative end of the feedback amplifier 1, and the source of the third PMOS tube (MP3) is connected to the power supply voltage (VDD); the gate of the fourth PMOS tube (MP4) is connected to the power ground (GND), the drain of the fourth PMOS tube (MP4) is connected to the drain of the sixth NMOS tube (MN6), the drain of the eighth NMOS tube (MN8) and the positive end of the feedback amplifier 1, and the current in the fourth PMOS tube (MP4) is I tot The source of the fourth PMOS tube (MP4) is connected to the power supply voltage (VDD); the gate of the fifth PMOS tube (MP5) is connected to the drain of the fifth PMOS tube (MP5), the gate of the ninth NMOS tube (MN9) and the drain of the tenth NMOS tube (MN10); the drain of the fifth PMOS tube (MP5) is connected to the gate of the fifth PMOS tube (MP5), the gate of the ninth NMOS tube (MN9) and the drain of the tenth NMOS tube (MN10); the source of the fifth PMOS tube (MP5) is connected to the power supply voltage (VDD); the gate of the fifth NMOS tube (MN5) is connected to the power supply voltage (VDD), the source of the fifth NMOS tube (MN5) is connected to the power ground (GND), and the drain of the fifth NMOS tube (MN5) is connected to the third The gate and drain of the PMOS tube (MP3) are connected to the negative end of the feedback amplifier 1; the gate of the sixth NMOS tube (MN6) is connected to the power supply voltage (VDD), the drain of the sixth NMOS tube (MN6) is connected to the drain of the fourth PMOS tube (MP4), the drain of the eighth NMOS tube (MN8) and the positive end of the feedback amplifier 1, and the source of the sixth NMOS tube (MN6) is connected to the drain of the seventh NMOS tube (MN7); the gate of the seventh NMOS tube (MN7) is connected to the output end of the feedback amplifier 1, the drain of the seventh NMOS tube (MN7) is connected to the source of the sixth NMOS tube (MN6), the source of the seventh NMOS tube (MN7) is connected to the power ground (GND), and the current in the seventh NMOS tube (MN7) is I biasThe gate of the eighth NMOS tube (MN8) is connected to the power supply voltage (VDD), the drain of the eighth NMOS tube (MN8) is connected to the drain of the fourth PMOS tube (MP4), the drain of the sixth NMOS tube (MN6) and the positive terminal of the feedback amplifier 1, and the source of the eighth NMOS tube (MN8) is connected to the drain of the ninth NMOS tube (MN9); the gate of the ninth NMOS tube (MN9) is connected to the gate and drain of the fifth PMOS tube (MP5) and the drain of the tenth NMOS tube (MN10), the gate voltage is V2, the drain of the ninth NMOS tube (MN9) is connected to the source of the eighth NMOS tube (MN8), the source of the ninth NMOS tube (MN9) is connected to the power ground (GND), and the current in the ninth NMOS tube (MN9) is I comp The gate of the tenth NMOS tube (MN10) is connected to the power supply voltage (VDD), the source of the tenth NMOS tube (MN10) is connected to the gate and drain of the eleventh NMOS tube (MN11), the drain of the tenth NMOS tube (MN10) is connected to the gate and drain of the fifth PMOS tube (MP5) and the gate of the ninth NMOS tube (MN9); the gate of the eleventh NMOS tube (MN11) is connected to the source of the tenth NMOS tube (MN10) and the drain of the eleventh NMOS tube (MN11), the source of the eleventh NMOS tube (MN11) is connected to the power supply ground (GND), and the drain of the eleventh NMOS tube (MN11) is connected to the source of the tenth NMOS tube (MN10). The positive input terminal of the feedback amplifier 1 is connected to the drain of the fourth PMOS tube (MP4), the drain of the sixth NMOS tube (MN6) and the drain of the eighth NMOS tube (MN8), and the input voltage is V3; the negative input terminal of the feedback amplifier 1 is connected to the gate and drain of the third PMOS tube (MP3) and the drain of the fifth NMOS tube (MN5), and the input voltage is V1; the output terminal of the feedback amplifier 1 is connected to the gate of the seventh NMOS tube (MN7), the gate of the third NMOS tube (MN3) in the differential delay unit (1) and the gate of the fourteenth NMOS tube (MN14) in the voltage swing controller (3), and the output voltage is V nbias .

[0056] In the bias current controller (2), the magnitudes of V1 and V2 are proportional to the change of the power supply. When the power supply voltage increases, the current I flowing through the fourth PMOS tube (PM4) increases. tot Increases and both V1 and V2 increase in direct proportion to the power supply voltage, the gate voltage V2 of the ninth NMOS tube (MN9) increases, and the compensation current I flowing through it comp Increase, due to the current I flowing through the fourth PMOS tube (PM4) tot is the current I flowing through the seventh NMOS tube (MN7) biasThe current I flowing through the ninth NMOS tube (MN9) comp The sum of the total current and the current related to the square term of the power supply flows through the ninth NMOS tube (MN9). The above current subtraction operation makes the current I flowing through the seventh NMOS tube (MN7) bias Although it rises slightly, it does not change much. Feedback amplifier 1 adjusts V nbias To ensure that V3 is equal to V1 and maintains a proportional relationship with the power supply voltage, the feedback amplifier can also reduce the I flowing through the fourth PMOS tube (PM4) due to the channel length modulation effect. tot Assuming that the power supply voltage changes slightly by ΔVDD based on VDD, the bias current I flowing through the seventh NMOS tube (MN7) bias The relationship with the change in power supply voltage ΔVDD is derived as follows

[0057] Before the power supply voltage changes, the current I flowing through the fourth PMOS tube (PM4) tot for

[0058]

[0059] The current I flowing through the ninth NMOS tube (MN9) comp for

[0060]

[0061] The current I flowing through the seventh NMOS tube (MN7) bias for

[0062] I bias =I tot -I comp

[0063] After the power supply voltage changes, the current I flowing through the fourth PMOS tube (PM4) tot 'for

[0064]

[0065] The current I flowing through the ninth NMOS tube (MN9) comp 'for

[0066]

[0067] The current I flowing through the seventh NMOS tube (MN7) bias 'for

[0068]

[0069] where μ p and μ nare the mobility of holes and electrons, respectively, C ox is the gate oxide capacitance per unit area, (W / L) P4 is the width-to-length ratio of the fourth PMOS transistor (PM4), (W / L) N9 is the width-to-length ratio of the ninth NMOS transistor (MN9), α is the ratio of the gate voltage V2 of the seventh NMOS transistor (MN7) to the power supply voltage, and since ΔVDD is small, the square term in the formula can be ignored. From the above derivation, it can be obtained that the current I flowing through the seventh NMOS transistor (MN7) is bias Varies in direct proportion to the power supply voltage.

[0070] The circuit diagram of the voltage swing controller (3) is shown in Figure 3As shown, it includes a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a twelfth NMOS tube (MN12), a thirteenth NMOS tube (MN13), a fourteenth NMOS tube (MN14), a fifteenth NMOS tube (MN15), and a feedback amplifier 2, wherein the gate of the sixth PMOS tube (MP6) is connected to the power ground (GND), the drain of the sixth PMOS tube (MP6) is connected to the gate and drain of the twelfth NMOS tube (MN12) and is connected to the positive terminal of the feedback amplifier 2, and the sixth PMOS tube (MP6) The source of the seventh PMOS tube (MP7) is connected to the power supply voltage (VDD); the gate of the seventh PMOS tube (MP7) is connected to the output end of the feedback amplifier 2; the drain of the seventh PMOS tube (MP7) is connected to the drain of the thirteenth NMOS tube (MN13) and connected to the negative end of the feedback amplifier 2; the source of the seventh PMOS tube (MP7) is connected to the power supply voltage (VDD); the gate of the twelfth NMOS tube (MN12) is connected to the drain of the sixth PMOS tube (MP6) and the drain of the twelfth NMOS tube (MN12) and connected to the positive end of the feedback amplifier 2; The drain of the NMOS tube (MN12) is connected to the drain of the sixth PMOS tube (MP6), the gate of the twelfth NMOS tube (MN12) and connected to the positive terminal of the feedback amplifier 2, and the source of the twelfth NMOS tube (MN12) is connected to the power ground (GND); the gate of the thirteenth NMOS tube (MN13) is connected to the power supply voltage (VDD), the drain of the thirteenth NMOS tube (MN13) is connected to the drain of the seventh PMOS tube (MP7) and connected to the negative terminal of the feedback amplifier 2, and the source of the thirteenth NMOS tube (MN13) is connected to the power ground (GND). The drain of the fourteenth NMOS tube (MN14) and the drain of the fifteenth NMOS tube (MN15); the gate of the fourteenth NMOS tube (MN14) is connected to the output end of the feedback amplifier 1 in the bias current controller (2); the drain of the fourteenth NMOS tube (MN14) is connected to the source of the thirteenth NMOS tube (MN13) and the drain of the fifteenth NMOS tube (MN15); the source of the fourteenth NMOS tube (MN14) is connected to the power ground (GND); the gate of the fifteenth NMOS tube (MN15) is connected to the input control signal V contThe drain of the fifteenth NMOS tube (MN15) is connected to the source of the thirteenth NMOS tube (MN13) and the drain of the fourteenth NMOS tube (MN14), and the source of the fifteenth NMOS tube (MN15) is connected to the power ground (GND); the positive input end of the feedback amplifier 2 is connected to the drain of the sixth PMOS tube (MP6), the gate and drain of the twelfth NMOS tube (MN12), and the input voltage is V4; the negative input end of the feedback amplifier 2 is connected to the drain of the seventh PMOS tube (MP7) and the drain of the thirteenth NMOS tube (MN13), and the input voltage is V5; the output end of the feedback amplifier 2 is connected to the gate of the seventh PMOS tube (MP7), the gates of the first PMOS tube (MP1) and the second PMOS tube (MP2) in the differential delay unit (1), and the output voltage is V pbias .

[0071] In the voltage swing controller (3), the drains of the sixth PMOS transistor (MP6) and the twelfth NMOS transistor (MN12) can generate a reference terminal voltage V4 that is independent of the power supply voltage, and the feedback amplifier 2 and the feedback terminal voltage V5 can jointly adjust V pbias V5 is made equal to V4, thereby, the output voltage swing is limited between V4 and VDD. When the power supply voltage changes, the output voltage swing changes in direct proportion to the power supply voltage.

[0072] In summary, the present invention designs a ring voltage-controlled oscillator structure, which uses a bias current controller and a voltage swing controller to detect changes in the power supply voltage and adjust the bias current I related to the power supply voltage accordingly. bias and voltage swing V swing The size of the bias current I bias and voltage swing V swing The ratio of is independent of the power supply voltage, thereby achieving low sensitivity of the ring voltage controlled oscillator output frequency to power supply voltage fluctuations. bias / V swing The present invention achieves low power supply sensitivity by adjusting the ratio. In the bias current controller, the feedback amplifier 1 controls the bias current branch copied from the delay unit to generate a reference bias current, and the current generated by the compensation branch compensates the current related to the square term of the power supply, so that the reference bias current changes in direct proportion to the power supply and the rate of change is small. In the voltage swing controller, the feedback amplifier 2 adjusts the bias voltage V pbias The output voltage of the delay unit is made equal to the reference voltage, and the voltage swing is limited to between the power supply voltage and the reference voltage. Through the above two adjustment mechanisms, I bias With V swing are proportional to the power supply, I bias / V swing Keeping it approximately constant, the low power supply sensitivity of the ring voltage controlled oscillator is achieved.

[0073] It is to be understood that the above is only a preferred embodiment of the present invention, and the present invention is not limited to the precise configuration and components shown above. Various modifications and optimizations can be made to the step sequence, details and operations of the above-described methods and structures without departing from the scope of protection of the claims.

Claims

1. A ring voltage controlled oscillator with low power supply sensitivity, characterized in that: It includes a differential delay unit (1), a bias current controller (2), and a voltage swing controller (3). The differential delay unit (1) is configured in a differential input and differential output mode, the gate of the first NMOS transistor MN1 is a positive input terminal, the gate of the second NMOS transistor MN2 is a negative input terminal, the drains of the first NMOS transistor MN1 and the first PMOS transistor MP1 are negative output terminals, and the drains of the second PMOS transistor MP2 and the second NMOS transistor MN2 are positive output terminals; The bias current controller (2) has a power supply voltage VDD as an input signal, and the output end of the feedback amplifier 1 in the bias current controller (2) is connected to the gate of the third NMOS transistor MN3 of the differential delay unit (1) and provides an output signal V nbias Used to adjust the bias current I of the differential delay unit (1) bias ; The voltage swing controller (3) is based on the power supply voltage VDD and the output signal V nbias At the same time, the output end of the feedback amplifier 1 in the bias current controller (2) is connected to the gate of the fourteenth NMOS transistor MN14 in the voltage swing controller (3) and provides an output signal V nbias The bias current of the replica branch is adjusted, and the output end of the feedback amplifier 2 of the voltage swing controller (3) is connected to the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 in the differential delay unit (1) and provides an output signal V pbias Used to adjust the gate bias voltage.

2. The ring voltage controlled oscillator with low power supply sensitivity according to claim 1, characterized in that: The differential delay unit (1) comprises a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, and a fourth NMOS tube MN4; The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the output signal V pbias The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and outputs a voltage V out- , the source of the first PMOS tube MP1 is connected to the power supply voltage VDD; The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 and the output signal V pbias The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and outputs a voltage V out+ , the source of the second PMOS tube MP2 is connected to the power supply voltage (VDD); The gate of the first NMOS transistor MN1 is connected to the differential input signal V in+ The drain of the first NMOS tube MN1 is connected to the drain of the first PMOS tube MP1 and outputs a voltage V out- , the source of the first NMOS tube MN1 is connected to the source of the second NMOS tube MN2, the drain of the third NMOS tube MN3 and the drain of the fourth NMOS tube MN4; The gate of the second NMOS transistor MN2 is connected to the differential input signal V in- The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2 and outputs a voltage V out+ , the source of the second NMOS tube MN2 is connected to the source of the first NMOS tube MN1, the drain of the third NMOS tube MN3 and the drain of the fourth NMOS tube MN4; The gate of the third NMOS transistor MN3 is connected to the output signal V of the bias current controller (2). nbias , the drain of the third NMOS tube MN3 is connected to the source of the first NMOS tube MN1, the source of the second NMOS tube MN2 and the drain of the fourth NMOS tube MN4, and the source of the third NMOS tube MN3 is connected to the power ground GND; The gate of the fourth NMOS transistor MN4 is connected to the input control signal V cont The drain of the fourth NMOS tube MN4 is connected to the source of the first NMOS tube MN1, the source of the second NMOS tube MN2 and the drain of the third NMOS tube MN3, and the source of the fourth NMOS tube MN4 is connected to the power ground GND.

3. The ring voltage controlled oscillator with low power supply sensitivity according to claim 1, characterized in that: The bias current controller (2) comprises a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, and a feedback amplifier 1; The gate of the third PMOS tube MP3 is connected to the drain of the third PMOS tube MP3, the drain of the fifth NMOS tube MN5 and the negative terminal of the feedback amplifier 1; the drain of the third PMOS tube MP3 is connected to the gate of the third PMOS tube MP3, the drain of the fifth NMOS tube MN5 and the negative terminal of the feedback amplifier 1; the source of the third PMOS tube MP3 is connected to the power supply voltage VDD; The gate of the fourth PMOS tube MP4 is connected to the power ground GND, the drain of the fourth PMOS tube MP4 is connected to the drain of the sixth NMOS tube MN6, the drain of the eighth NMOS tube MN8 and the positive terminal of the feedback amplifier 1, and the current in the fourth PMOS tube MP4 is I tot , the source of the fourth PMOS tube MP4 is connected to the power supply voltage VDD; The gate of the fifth PMOS tube MP5 is connected to the drain of the fifth PMOS tube MP5, the gate of the ninth NMOS tube MN9 and the drain of the tenth NMOS tube MN10, the drain of the fifth PMOS tube MP5 is connected to the gate of the fifth PMOS tube MP5, the gate of the ninth NMOS tube MN9 and the drain of the tenth NMOS tube MN10, and the source of the fifth PMOS tube MP5 is connected to the power supply voltage VDD; The gate of the fifth NMOS transistor MN5 is connected to the power supply voltage VDD, the source of the fifth NMOS transistor MN5 is connected to the power ground GND, and the drain of the fifth NMOS transistor MN5 is connected to the gate and drain of the third PMOS transistor MP3 and connected to the negative terminal of the feedback amplifier 1; The gate of the sixth NMOS transistor MN6 is connected to the power supply voltage VDD, the drain of the sixth NMOS transistor MN6 is connected to the drain of the fourth PMOS transistor MP4, the drain of the eighth NMOS transistor MN8 and the positive terminal of the feedback amplifier 1, and the source of the sixth NMOS transistor MN6 is connected to the drain of the seventh NMOS transistor MN7; The gate of the seventh NMOS transistor MN7 is connected to the output end of the feedback amplifier 1, the drain of the seventh NMOS transistor MN7 is connected to the source of the sixth NMOS transistor MN6, the source of the seventh NMOS transistor MN7 is connected to the power ground GND, and the current in the seventh NMOS transistor MN7 is I bias ; The gate of the eighth NMOS tube MN8 is connected to the power supply voltage VDD, the drain of the eighth NMOS tube MN8 is connected to the drain of the fourth PMOS tube MP4, the drain of the sixth NMOS tube MN6 and the positive terminal of the feedback amplifier 1, and the source of the eighth NMOS tube MN8 is connected to the drain of the ninth NMOS tube MN9; The gate of the ninth NMOS tube MN9 is connected to the gate and drain of the fifth PMOS tube MP5 and the drain of the tenth NMOS tube MN10, and the gate voltage is V2. The drain of the ninth NMOS tube MN9 is connected to the source of the eighth NMOS tube MN8, and the source of the ninth NMOS tube MN9 is connected to the power ground GND. The current in the ninth NMOS tube MN9 is I comp ; The gate of the tenth NMOS transistor MN10 is connected to the power supply voltage VDD, the source of the tenth NMOS transistor MN10 is connected to the gate and drain of the eleventh NMOS transistor MN11, and the drain of the tenth NMOS transistor MN10 is connected to the gate and drain of the fifth PMOS transistor MP5 and the gate of the ninth NMOS transistor MN9; The gate of the eleventh NMOS transistor MN11 is connected to the source of the tenth NMOS transistor MN10 and the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is connected to the power ground GND, and the drain of the eleventh NMOS transistor MN11 is connected to the source of the tenth NMOS transistor MN10 and the gate of the eleventh NMOS transistor MN11; The positive input terminal of the feedback amplifier 1 is connected to the drain of the fourth PMOS tube MP4, the drain of the sixth NMOS tube MN6 and the drain of the eighth NMOS tube MN8, and the input voltage is V3. The negative input terminal of the feedback amplifier 1 is connected to the gate and drain of the third PMOS tube MP3 and the drain of the fifth NMOS tube MN5, and the input voltage is V1. The output terminal of the feedback amplifier 1 is connected to the gate of the seventh NMOS tube MN7, the gate of the third NMOS tube MN3 in the differential delay unit (1) and the gate of the fourteenth NMOS tube MN14 in the voltage swing controller (3), and the output voltage is V nbias .

4. The ring voltage controlled oscillator with low power supply sensitivity according to claim 1, characterized in that: The voltage swing controller (3) comprises a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a feedback amplifier 2. The gate of the sixth PMOS transistor MP6 is connected to the power ground GND, the drain of the sixth PMOS transistor MP6 is connected to the gate and drain of the twelfth NMOS transistor MN12 and connected to the positive terminal of the feedback amplifier 2, and the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD; The gate of the seventh PMOS transistor MP7 is connected to the output end of the feedback amplifier 2, the drain of the seventh PMOS transistor MP7 is connected to the drain of the thirteenth NMOS transistor MN13 and connected to the negative end of the feedback amplifier 2, and the source of the seventh PMOS transistor MP7 is connected to the power supply voltage VDD; The gate of the twelfth NMOS tube MN12 is connected to the drain of the sixth PMOS tube MP6, the drain of the twelfth NMOS tube MN12 and connected to the positive terminal of the feedback amplifier 2; the drain of the twelfth NMOS tube MN12 is connected to the drain of the sixth PMOS tube MP6, the gate of the twelfth NMOS tube MN12 and connected to the positive terminal of the feedback amplifier 2; the source of the twelfth NMOS tube MN12 is connected to the power ground GND; The gate of the thirteenth NMOS tube MN13 is connected to the power supply voltage VDD, the drain of the thirteenth NMOS tube MN13 is connected to the drain of the seventh PMOS tube MP7 and to the negative terminal of the feedback amplifier 2, and the source of the thirteenth NMOS tube MN13 is connected to the drain of the fourteenth NMOS tube MN14 and the drain of the fifteenth NMOS tube MN15; The gate of the fourteenth NMOS transistor MN14 is connected to the output end of the feedback amplifier 1 in the bias current controller (2), the drain of the fourteenth NMOS transistor MN14 is connected to the source of the thirteenth NMOS transistor MN13 and the drain of the fifteenth NMOS transistor MN15, and the source of the fourteenth NMOS transistor MN14 is connected to the power ground GND; The gate of the fifteenth NMOS transistor MN15 is connected to the input control signal V cont , the drain of the fifteenth NMOS tube MN15 is connected to the source of the thirteenth NMOS tube MN13 and the drain of the fourteenth NMOS tube MN14, and the source of the fifteenth NMOS tube MN15 is connected to the power ground GND; The positive input terminal of the feedback amplifier 2 is connected to the drain of the sixth PMOS tube MP6, the gate and drain of the twelfth NMOS tube MN12, and the input voltage is V4. The negative input terminal of the feedback amplifier 2 is connected to the drain of the seventh PMOS tube MP7 and the drain of the thirteenth NMOS tube MN13, and the input voltage is V5. The output terminal of the feedback amplifier 2 is connected to the gate of the seventh PMOS tube MP7, the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 in the differential delay unit (1), and the output voltage is V pbias .

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