Light-emitting component and method for producing light-emitting component

Abstract

The invention relates to an optoelectronic device comprising an epitaxially grown functional layer stack and an electrically conductive contact layer arranged on the functional layer stack. The functional layer stack includes a first layer having a dopant of a first conductivity type; an active region disposed on the first layer; a second layer having a dopant of a second conductivity type disposed on the active region; and a third layer having a dopant of the second conductivity type disposed on the second layer, the third layer having a higher concentration of the dopant of the second conductivity type than the second layer. The functional layer stack is delimited in a lateral direction by a side surface of the functional layer stack and includes a central region along a centerline of the functional layer stack, where the central region is spaced apart from the side surface. A current path from the conductive contact layer through the third layer to the second layer is confined to the central region.

Description

[0001] The present invention relates to an optoelectronic device and a method for manufacturing an optoelectronic device. Background Art

[0002] Optoelectronic devices, also known as light emitting diodes or LEDs, require a supply of energy for illumination. Charge carriers introduced into the active region of the optoelectronic device recombine under emission of light.

[0003] However, it is a known problem for light emitting diodes, especially very small LEDs like μ-LEDs, whose dimensions are less than 1000 μm in area or less, to efficiently generate and outcouple light. 2 and can be as low as about 10μm 2 On the one hand, impurities caused during the manufacturing process along the side surfaces of the optoelectronic device lead to (efficiency) losses due to non-radiative recombination of charge carriers. On the other hand, a large part of the internally generated light can be trapped within the structure of the LED, since only a small part of the internally generated light can be coupled out of the LED via internal reflections or direct emission from the active area. The trapped light then has to be decoupled from the LED, for example by suitable outcoupling structures.

[0004] Therefore, it is an object of the present invention to solve at least one of the above problems and to provide a corresponding improved optoelectronic device. Another object of the present invention is to provide a method for manufacturing a corresponding improved optoelectronic device. Summary of the invention

[0005] This and other requirements are met by an optoelectronic component having the features of independent claim 1 and by a method for producing an optoelectronic component having the features of independent claim 14. Embodiments and further developments of the invention are described in the dependent claims.

[0006] The concept proposed by the inventors is to achieve current confinement for an epitaxially grown functional semiconductor layer stack so that the carrier flow within the layer stack is concentrated in the central region of the functional layer stack. As a result, the carrier density along the side surfaces of the layer stack is reduced, and impurities along the sides have no significant effect or a less significant effect on the (efficiency) losses due to non-radiative recombination of carriers. Therefore, the functional layer stack and / or the conductive contact layer arranged on the functional layer stack are modified / configured to form a current path from the conductive contact layer through the layer stack only in the central region of the layer stack. In order to additionally provide an improved outcoupling of the light generated in the layer stack, several possibilities for outcoupling structures on the surface of the layer stack facing the conductive contact layer are proposed.

[0007] According to one aspect, an epitaxially grown functional layer stack is provided with a conductive contact layer arranged on the functional layer stack, thereby forming an optoelectronic device together. The functional layer stack includes a first layer having a dopant of a first conductivity type, an active area, a second layer having a dopant of a second conductivity type, and a third layer having a dopant of the second conductivity type. The functional layer stack is limited by the side surface of the functional layer stack in the lateral direction, and the functional layer stack includes a central region along the center line of the functional layer stack, wherein the center line extends in the growth direction of the functional layer stack. The central region is defined in such a way that the central region is spaced apart from the side surface of the functional layer stack, thereby forming a "real" central region of the functional layer stack, thereby forming only a sub-region of the functional layer stack. The third layer has a higher concentration of the dopant of the second conductivity type than the second layer, and behaves like a current diffusion layer, but its current diffusion function is limited to the central region of the functional layer stack. This is because the functional layer stack is modified / configured so that the current path extending from the conductive contact layer through the third layer to the second layer is limited to the central region.

[0008] The functional layer stack particularly comprises a layer stack of epitaxially grown layers, which has an active region arranged between a first layer and a second layer. The first layer may be, for example, a p-doped layer, and the second layer may be an n-doped layer. In this case, the third layer may be a highly n-doped top layer of the functional layer stack to form electrical contact with a conductive contact layer (metal, TCO, etc.) coated on the functional layer stack. The high doping of the third layer generally achieves good lateral current diffusion in the functional layer stack. In order to achieve current confinement to the central region of the layer stack, the structuring of the conductive contact layer may not be sufficient, because lateral current diffusion may still occur in the third layer. This is why the highly doped n-epi top layer is a) removed in the region outside the central region, or b) discontinuous / disconnected to form an electrically separated central region to suppress lateral current diffusion in the third layer.

[0009] The optoelectronic device is, for example, a radiation emitting optoelectronic semiconductor chip. For example, the semiconductor chip may be a light emitting diode (LED) chip or a laser chip. The optoelectronic semiconductor chip may generate light during operation. Specifically, the optoelectronic semiconductor chip may generate light in a spectral range from UV radiation to light in the infrared range, in particular visible light. Alternatively, the optoelectronic semiconductor chip may be a radiation detecting semiconductor chip, for example a photodiode.

[0010] The optoelectronic device may, for example, comprise an edge length of less than 100 μm, or less than 40 μm, and in particular less than 10 μm. Thus, the optoelectronic semiconductor chip may, for example, be a μLED (LED for light emitting devices, μLED for microLEDs) or a μLED chip. For such small optoelectronic devices, current confinement for reducing (efficiency) losses due to non-radiative recombination of charge carriers caused by impurities along the side surfaces of the device is currently unknown. However, the proposed principle provides a solution to this problem.

[0011] In some aspects, the third layer is confined to the central region to provide current confinement to the central region of the layer stack. The third layer can be removed in particular in regions outside the central region compared to a complete third layer to inhibit lateral current spreading into the removed region of the third layer.

[0012] In some aspects, the third layer includes at least one intersection, wherein the at least one intersection divides the third layer into at least a first region and a second region separated from each other. The first region and the second region are within the third region and are particularly electrically insulated from each other. The first region is confined to the central region, thereby providing current confinement to the central region of the layer stack.

[0013] In some aspects, the conductive contact layer is in electrical contact with the third layer only in the central region. Thus, the conductive contact layer can, for example, be limited to the central region of the functional layer stack, or can extend outside the central region but only in electrical contact with the third layer in the central region. In some aspects, the conductive contact layer is arranged on the third layer only in the central region and is therefore limited to the central region of the functional layer stack.

[0014] In some aspects, the optoelectronic device, and in particular the functional layer stack, further comprises a p-type dopant, such as, for example, Zn (zinc), which is deposited in the edge regions of the active region, in particular in the region outside the central region, thereby causing quantum well intermixing (QWI) thereof. Thereby, the efficiency of, for example, very small InGaAlP optoelectronic devices can be further improved. Such QWI is particularly preferably located outside the central region to further enhance the effect already created by the confinement. The QWI enlarges the band gap of the quantum well in this outer region close to the side surface of the layer stack, so that the charge carriers in the quantum well can no longer reach the side surface close to the quantum well, thereby further improving the efficiency of such very small LEDs.

[0015] In order to provide an improved outcoupling of the light generated in the layer stack, several possibilities for outcoupling structures on the surface of the layer stack facing the electrically conductive contact layer are proposed. By using outcoupling structures as proposed below, an enhanced light extraction of the light generated in the active region can be provided even for small optoelectronic devices such as LEDs, in particular μ-LEDs, whose dimensions lie in the area or less than 1000 μm 2 and can be as low as about 10μm 2 .

[0016] In some aspects, the third layer or the third layer and the second layer include a first surface structure having a plurality of protrusions and grooves on the surface facing the conductive contact layer, the first surface structure serving as an outcoupling structure on the third layer to enhance the outcoupling efficiency of light generated in the optoelectronic device. Thus, the protrusions and grooves of the first surface structure can be evenly distributed, but can also have an uneven / random distribution. The protrusions of the first surface structure can all have the same height, or their height can vary for all protrusions or only for a few of the protrusions.

[0017] In some aspects, the protrusions in the central region of the first surface structure are higher than the protrusions outside the central region of the first surface structure. Thus, for example, a conductive contact layer extending over the entire third layer can contact the third layer, and in particular only contact the protrusions of the first surface structure of the third layer in the central region. Higher in this context can be understood in particular in the following way, so that the top level of the protrusions outside the central region is higher than the top level of the protrusions in the central region.

[0018] In some aspects, the protrusions at least in the central region of the first surface structure have a planarized surface facing the conductive contact layer. In particular, the protrusions contacting the conductive contact layer have a planarized surface facing the conductive contact layer. For example, such a planarized surface can be the result of planarization of the protrusions to provide a contact surface having a planarized surface facing the conductive contact layer.

[0019] In some aspects, the protrusions of the first surface structure are in electrical contact with the electrically conductive contact layer at least in a central region.

[0020] In some aspects, the second layer includes a second surface structure having a plurality of protrusions and grooves on the surface facing the conductive contact layer, in particular in an area outside the central area. The second surface structure can be particularly arranged in the area outside the central area where the third layer is removed, and used as a coupling-out structure on the second layer to enhance the coupling-out efficiency of the light generated in the optoelectronic device. Thus, the protrusions and grooves of the second surface structure can be evenly distributed, but can also have an uneven / random distribution. The protrusions of the second surface structure can all have the same height, or their height can vary for all protrusions or only for a few of the protrusions.

[0021] The first surface structure and / or the second surface structure may correspond to a roughening of the third layer and / or the second layer and may be selected / generated with regard to desired requirements and desired outcoupling properties.

[0022] In some aspects, the optoelectronic device further comprises a planarization layer arranged on the third layer and / or the second layer. The planarization layer particularly fills at least one intersection and / or a groove of the first surface structure and / or the second surface structure and / or covers the first surface structure and / or the second surface structure at least in an area outside the central area. The planarization layer is specifically a transparent material to allow light generated in the optoelectronic device to be transmitted through the planarization layer. In the case where the planarization layer covers the first surface structure and / or the second surface structure, the planarization layer additionally has a low refractive index to further improve or at least not offset the outcoupling efficiency due to the outcoupling improvement of the first surface structure and / or the second surface structure.

[0023] In some aspects, the planarization layer is an electrically insulating material.Thereby, regions of the third layer and optionally the second layer outside the central region can be electrically insulated from the electrically conductive contact layer, in particular if the electrically conductive contact layer extends over the entire functional layer stack.

[0024] In some aspects, the planarization layer covers the functional layer stack over the entire functional layer stack, while in some aspects, the planarization layer covers the functional layer stack only in a central region. In the latter case, the planarization layer can also be a transparent conductive material, such as indium tin oxide (ITO), for example.

[0025] In some aspects, the central region is limited to half the distance between two opposite side surfaces of the functional layer stack. The central region can in particular be a subregion of the functional layer stack extending along a centerline of the functional layer stack, wherein the central region is smaller than the rest of the functional layer stack, and in particular is smaller than half of the functional layer stack.

[0026] In some aspects, the distance from the central region to the adjacent side surface is within the range of the mean free path of mobile carriers of the functional layer stack. Thus, the recombination of charge carriers near the side surface can be suppressed. In some aspects, the distance between the central region and the adjacent side surface is between 500nm and 2500nm, between 500nm and 2000nm, or between 500nm and 1500nm.

[0027] In some aspects, the first layer and / or the second layer and / or the third layer comprises a base material selected from the group consisting of:

[0028] -GaN;

[0029] -AlGaN;

[0030] -AlGaInP;

[0031] -AlGaInN; and

[0032] -AlGaP.

[0033] Other materials may also be used. The first layer and / or the second layer may in particular comprise an epitaxially grown layer.

[0034] Some other aspects relate to a method for manufacturing at least one optoelectronic device. In a first step, a functional layer stack is provided, the functional layer stack comprising a first layer having a dopant of a first conductivity type, an active area arranged on the first layer, a second layer having a dopant of a second conductivity type arranged on the active area, and a third layer having a dopant of the second conductivity type arranged on the second layer, the third layer having a higher concentration of the dopant of the second conductivity type than the second layer. The functional layer stack is laterally limited by the side surfaces of the functional layer stack and includes a central region along a center line of the functional layer stack, wherein the central region is spaced apart from the side surfaces to form a sub-region of the functional layer stack. A conductive contact layer is then provided on the third layer so that a current path from the conductive contact layer through the third layer to the second layer is limited to the central region.

[0035] In some aspects, the method further comprises removing or thinning the third layer in an area outside the central area, or the method further comprises creating at least one intersection in the third layer, such that the at least one intersection divides the third layer into at least a first area and a second area separated from each other, the first area being confined to the central area. The creation or removal of the intersection can be completed after the functional layer stack has been grown, for example, on a wafer, and after the functional layer stack has been removed from the wafer and transferred to a final destination. The creation or removal of the intersection can include an etching process and / or a photolithography process.

[0036] In some aspects, the method further includes roughening a surface of the third layer facing the conductive contact layer to create a first surface structure having a plurality of protrusions and grooves.

[0037] In some aspects, the method further comprises roughening a surface of the second layer facing the conductive contact layer, particularly in regions outside the central region where the third layer has been removed, to create a second surface structure having a plurality of protrusions and grooves.

[0038] The steps of removing or thinning the third layer, creating at least one intersection in the third layer, roughening the surface of the third layer and / or roughening the surface of the second layer can be done, for example, in one and the same process. This can be achieved, for example, by using a loading effect with a dry etching process. Thus, large structures are etched faster / deeper than small structures, so that the creation of roughening and, for example, the creation of at least one intersection can start simultaneously, thereby producing the corresponding structure.

[0039] Roughening of the second layer and / or the third layer may include an etching process and / or a photolithography process. Roughening may be done, for example, over the entire surface of the third layer facing the conductive contact layer, or may be done only in a central area, or may be done only near a central area.

[0040] Roughening can be done, for example, by using "Kugelfischen / native lithography" from OSRAM Thin Film Products or by a lithography process followed by an etching process. In order to avoid far field features due to a regular surface pattern (photonic grid), it can be beneficial to arrange the structures / protrusions randomly. Etching can be done by etching "holes" into the surface of the third layer and / or the second layer or by reserved areas (etching all areas except defined areas). It has been found that etching resulting in shaped / angled sidewalls (e.g., cones and columns) is beneficial, as well as etching all areas except defined areas. It has also been found that structure sizes with a CD (critical dimension, e.g., diameter of the top surface) below 1 μm are beneficial.

[0041] For example, the roughening of the third layer can be done after at least a portion of the conductive contact layer has been arranged on the third layer, in particular on the third layer in the central region. For example, AuGe can be deposited on the third layer in the central region before roughening using a photolithography and etching process. The roughening process can be done in such a way that a portion of the metal is retained on top of the resulting protrusions in the third layer (AuGe is only present on top of the remaining cone and in contact with the third layer). In a subsequent step and in order to complete the conductive contact layer, the AuGe portion can be connected by subsequently depositing a conductive material, such as, for example, a transparent conductive oxide (TCO).

[0042] The step of providing an electrically conductive contact layer may comprise applying a thin metal layer and / or a TCO layer onto the third layer and in particular onto the protrusions of the first surface structure.

[0043] In some aspects, the method further comprises filling at least one intersection and / or the grooves of the first surface structure and / or the second surface structure with a filling material, such as an electrically insulating filling material. The filling may, for example, comprise depositing the filling material onto the third layer and / or the second layer. The filling material may form a planarization layer that covers the functional layer stack over the entire functional layer stack or only covers the functional layer stack in a central region. The planarization layer may, for example, also be a transparent conductive material, such as, for example, indium tin oxide (ITO).

[0044] The filling can be done, for example, with any transparent material. For the choice of material, the following aspects may be considered, among others:

[0045] - Low refractive index; the higher the refractive index, the less effective the roughening is in improving the outcoupling efficiency.

[0046] The electrically insulating material electrically insulates the electrically conductive contact layer from the third layer in the desired region.

[0047] - Conductive materials can have the following advantages:

[0048] 1) Electrical contact is easily made and no additional processing steps are required.

[0049] 2) If a pick-up method using electrostatic forces is used, a polarizable surface is beneficial for the pick-up process, and conductive materials are always well polarizable.

[0050] In some aspects, the method further comprises planarizing the protrusions of the first surface structure at least in the central region and planarizing the fill material (if present). Planarization can help provide a flat surface for disposing a conductive contact layer thereon.

[0051] An advantage of optoelectronic devices according to some aspects of the present invention is that the internal efficiency (IQE) is higher due to the reduced losses at the side surfaces of the optoelectronic device. In addition, the light extraction efficiency (LEE) can be improved by appropriately removing the third layer, or by shaping the emitting surface (for example, by creating surface structures on the emitting surface of the optoelectronic device). In addition to improving the light extraction efficiency, shaping the emitting surface can also result in a higher level of Lambertian far-field distribution. At the same time, optoelectronic devices according to some aspects of the present invention can still be provided with good pick-and-place capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the accompanying drawings:

[0053] Figure 1 schematically shows a cross-sectional view of an optoelectronic device,

[0054] Figure 2A and Figure 2B each schematically showing a cross-sectional view of an optoelectronic device according to some aspects of the present invention, and

[0055] FIG. 3A to FIG. 7C Each schematically shows a cross-sectional view of other embodiments of optoelectronic devices according to aspects of the present invention. DETAILED DESCRIPTION

[0056] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for comprehensiveness and completeness. Throughout the specification, like reference numerals refer to like elements. The drawings are not necessarily drawn to scale, and certain features may be exaggerated in order to better illustrate and describe the exemplary embodiments of the present disclosure.

[0057] Figure 1 A cross-sectional view of an optoelectronic device is shown, the optoelectronic device comprising a layer stack 2, the layer stack 2 comprising a first layer 3 having a dopant of a first conductivity type, an active region 4 arranged on the first layer 3, a second layer 5 having a dopant of a second conductivity type arranged on the active region 4, and a third layer 6 having a dopant of the second conductivity type arranged on the second layer 5, the third layer 6 having a higher concentration of the dopant of the second conductivity type than the second layer 5. In addition, a conductive contact layer 7 is arranged on the third layer 6. By electrically connecting the optoelectronic device, charge carriers (indicated by tree-shaped arrows) are diffused throughout the third layer due to the high doping of the third layer 6 and are introduced into the active region 4 of the optoelectronic device, and are recombined under the emission of light. However, the charge carriers recombined along the side surfaces of the functional layer stack may recombine without the emission of light due to impurities in the material, resulting in non-radiative losses (indicated by two lightning bolts). These non-radiative losses reduce the internal efficiency (IQE) of the optoelectronic device and are therefore undesirable, in particular for particularly small optoelectronic devices.

[0058] However, the inventors have found that implementing current confinement for the functional layer stack such that the carrier flow within the layer stack is concentrated to a central region of the functional layer stack can help reduce these non-radiative losses. By current confinement, the carrier density along the side surfaces 8 of the layer stack is reduced, and impurities along the side surfaces have no significant effect or a less significant effect on the (efficiency) losses due to non-radiative recombination of carriers. Therefore, the functional layer stack and / or the conductive contact layer arranged on the functional layer stack is modified / configured to form a current path from the conductive contact layer through the layer stack only in the central region of the layer stack, such as FIG. 2A to FIG. 7C Some of the embodiments shown in the figures additionally provide an improved outcoupling of light generated in the layer stack by providing an outcoupling structure on the surface of the layer stack facing the electrically conductive contact layer.

[0059] Figure 2AAn optoelectronic device 1 is shown in a cross-sectional view. The optoelectronic device 1 comprises a layer stack 2, the layer stack 2 comprising a first layer 3 having a dopant of a first conductivity type, an active area 4 arranged on the first layer 3, a second layer 5 having a dopant of a second conductivity type arranged on the active area 4, and a third layer 6 having a dopant of the second conductivity type arranged on the second layer 5, the third layer 6 having a higher concentration of the dopant of the second conductivity type than the second layer 5. In addition, a conductive contact layer 7 is arranged on the third layer 6. The functional layer stack 2 is laterally limited by side surfaces 8 of the functional layer stack 2 and comprises a central region 9 along a center line 10 of the functional layer stack 2. The central region 9 is spaced apart from the side surfaces 8, thereby forming a sub-region of the layer stack, which extends into the entire layer stack along the center line 10 of the functional layer stack. In order to provide current confinement, the third layer 6 is modified in such a way that the current path from the conductive contact layer 7 through the third layer 6 to the second layer 5 is limited to the central region 9. For this purpose, regions of the third layer 6 outside the central region have been removed or their height has been reduced in regions outside the central region in order to guide the current introduced into the electrically conductive contact layer 7 to the central region instead of diffusing it throughout the entire third layer extending over the entire functional layer stack 2. Removing regions of the third layer 6 outside the central region can also additionally lead to at least partial removal of the second layer 5, thereby reducing its height in regions outside the central region.

[0060] Figure 2B An alternative embodiment of the optoelectronic device 1 is shown. In order to provide current confinement, the third layer 6 has not been completely removed in the area outside the central area, but a crossover 11 has been introduced to divide the third layer 6 into a first area 6a and a second area 6b. Thus, the first area 6a is confined to the central area 9, and the conductive contact layer 7 contacts the third layer only in the first area / central area. Therefore, the current path from the conductive contact layer 7 through the third layer 6 to the second layer 5 is confined to the central area 9, so as to guide the current introduced into the conductive contact layer 7 to the central area, rather than allowing it to spread throughout the third layer 6.

[0061] FIG. 3A to FIG. 3C An embodiment is shown in which the area outside the central area 9 of the third layer 6 has been removed to provide current confinement. In addition, a first surface structure 12 is provided on the third layer 6 on the surface facing the conductive contact layer 7, the first surface structure 12 comprising a plurality of protrusions and grooves. The first surface structure can be used to improve the outcoupling efficiency of the optoelectronic device 1.

[0062] like Figure 3A and Figure 3B As shown, the planarization layer 14 is arranged on the layer stack 2, replacing the area outside the central area that has been removed from the third layer 6, and is used to provide the first surface structure 12. The planarization layer 14 is specifically made of a transparent material. Figure 3A and Figure 3B In the case of , it can also be an electrically insulating material so as not to offset the current confinement generated by removing the third layer outside the central area. The conductive contact layer 7 contacts the protrusions of the first surface structure, while the grooves are filled by the planarization layer. For better contact, the protrusions can be planarized to provide a good contact surface for the conductive contact layer 7.

[0063] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Figure 3A ) or may be confined to a central region 9 (see Figure 3B ). In particular in the case where the electrically conductive contact layer 7 extends over the entire functional layer stack, it may be a transparent electrically conductive material to allow light generated in the functional layer stack to exit from the optoelectronic device 1 .

[0064] like Figure 3C As shown, the planarization layer may also cover only the first surface structure, thereby filling the trenches of the first structure 12. In this case, the planarization layer may also be a conductive material, such as, for example, TCO, to provide good current spreading into the third layer within the central region 9.

[0065] Figure 4A and Figure 4B An embodiment of the optoelectronic device 1 without a planarization layer is shown. Figure 2B In addition to the embodiments shown in Figure 4A The optoelectronic device, and in particular the third layer 6 of the optoelectronic device 1, further comprises a first surface structure on the second region 6b of the third layer 6 on the surface facing the conductive contact layer 7. The first surface structure comprises a plurality of protrusions and grooves and can be used to improve the outcoupling efficiency of the optoelectronic device 1.

[0066] Apart from Figure 2A In addition to the embodiments shown in Figure 4B The optoelectronic device, and in particular the second layer 6 outside the central region of the optoelectronic device 1, further comprises a second surface structure on the surface facing the conductive contact layer 7. The second surface structure comprises a plurality of protrusions and grooves and can be used to improve the outcoupling efficiency of the optoelectronic device 1.

[0067] In an embodiment not shown, the third layer 6 of the optoelectronic device 1 comprises, for example Figure 4A , a first surface structure on the second region 6 b of the third layer 6 on the surface facing the electrically conductive contact layer 7 is shown, wherein the first surface structure also extends downward into the second layer 5. Therefore, the first surface structure comprises a plurality of protrusions and grooves, wherein the grooves can be at least partially arranged in the second layer 5 and can be used to improve the outcoupling efficiency of the optoelectronic device 1.

[0068] FIG. 5A to FIG. 5CAn embodiment of an optoelectronic device 1 is shown, except that Figure 4A In addition to the embodiment shown in , the optoelectronic device 1 further comprises a planarization layer 14, and wherein the first surface structure 12 also extends on the surface of the third layer 6 in the central region 9. Thus, the protrusions of the first surface structure 12 are higher in the central region 9 than in the region outside the central region to provide a contact surface for the conductive contact layer 7 and provide current confinement for the central region 9 when the third layer is arranged, wherein the conductive contact layer 7 extends over the entire functional layer stack, as shown in FIG. Figure 5A shown.

[0069] Additionally, and in order to provide current confinement, the third layer may include at least one intersection dividing the third layer into at least a first region and a second region, wherein the first region contacts the conductive contact layer 7 and forms a current path from the conductive contact layer 7 to the second layer.

[0070] like Figure 5A and Figure 5B As shown, the planarization layer 14 is arranged on the layer stack 2, replacing the area outside the central area that has been removed from the third layer 6, and is used to provide the first surface structure 12. The planarization layer 14 is specifically a transparent material. Figure 5A and Figure 5B In the case of the planarization layer 14 should also be an electrically insulating material, so as not to offset the current confinement generated by removing the third layer outside the central area. The conductive contact layer 7 contacts the protrusions of the first surface structure, while the grooves are filled by the planarization layer. For better contact, the protrusions can be planarized to provide a good contact surface for the conductive contact layer 7.

[0071] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Figure 5A ) or may be confined to a central region 9 (see Figure 5B ). In particular in the case where the electrically conductive contact layer 7 extends over the entire functional layer stack, it may be a transparent electrically conductive material to allow light generated in the functional layer stack to exit from the optoelectronic device 1 .

[0072] like Figure 5C As shown in , the planarization layer 14 may also cover only the first surface structure 12, thereby filling the trenches of the first structure 12 in the central region 9. In this case, the planarization layer may also be a conductive material, such as, for example, TCO, to provide good current diffusion into the third layer within the central region 9.

[0073] Fig. 6A and Figure 6B An embodiment of an optoelectronic device 1 is shown, wherein Figure 5A and Figure 5BCompared to the embodiment shown in , the protrusions of the first surface structure 12 have substantially the same height throughout the first surface structure 12. In order to provide current confinement to the central region 9, the third layer includes a crossover 11, which divides the third layer into a first region 6a and a second region 6b, wherein the first region is confined to the central region and contacts the conductive contact layer 7, which is also confined to the central region 9.

[0074] like Fig. 6A As shown in FIG. 1 , a planarization layer 14 is arranged on the layer stack 2 replacing the areas which have been removed from the third layer 6 in the intersections and in the grooves of the first surface structure. Figure 6B As shown in , the planarization layer 14 may only cover the first surface structure 12, thereby filling the trenches of the first structure 12 in the central region 9. In this case, the planarization layer may also be a conductive material, such as, for example, TCO, to provide good current spreading into the third layer within the central region 9.

[0075] FIG. 7A to FIG. 7C Shows Figure 4B According to another development of an embodiment, not only the second layer comprises a second surface structure 13, but the third layer 6 also comprises a first surface structure, which is arranged on the third layer 6 on the surface facing the conductive contact layer 7, and the first surface structure comprises a plurality of protrusions and grooves. The first surface structure can be used to improve the outcoupling efficiency of the optoelectronic device 1.

[0076] like Fig. 7A and Figure 7B As shown in FIG. 1 , the planarization layer 14 is arranged on the layer stack 2, replacing the area outside the central area that has been removed from the third layer 6, and is used to provide the first surface structure 12 and the grooves of the second surface structure 13. The planarization layer 14 is specifically a transparent material. Figure 3A and 3B In the case of , the planarization layer 14 should also be an electrically insulating material so as not to offset the current confinement generated by removing the third layer outside the central area. The conductive contact layer 7 contacts the protrusions of the first surface structure, while the grooves are filled by the planarization layer. For better contact, the protrusions can be planarized to provide a good contact surface for the conductive contact layer 7.

[0077] The electrically conductive contact layer 7 can extend over the entire functional layer stack (see Fig. 7A ), or may be confined to a central region 9 (see Figure 7B ). In particular in the case where the electrically conductive contact layer 7 extends over the entire functional layer stack, it may be a transparent electrically conductive material to allow light generated in the functional layer stack to exit from the optoelectronic device 1 .

[0078] like Figure 7CAs shown in , the planarization layer may also cover only the first surface structure, thereby filling the trenches of the first structure 12. In this case, the planarization layer may also be a conductive material, such as, for example, TCO, to provide good current spreading into the third layer within the central region 9.

[0079] Reference numerals list

[0080] 1 Optoelectronic devices

[0081] 2 functional layer stacking

[0082] 3First floor

[0083] 4 Active area

[0084] 5 Second floor

[0085] 6Third floor

[0086] 6a The first area

[0087] 6b Second area

[0088] 7Conductive contact layer

[0089] 8 Side surface

[0090] 9Central Area

[0091] 10 Center Line

[0092] 11 Cross

[0093] 12 First Surface Structure

[0094] 13 Second surface structure

[0095] 14 Planarization layer

Claims

1. A photoelectric device (1), comprising: - an epitaxially grown functional layer stack (2) comprising: - a first layer (3) having a dopant of a first conductivity type; - an active region (4) arranged on said first layer (3); - a second layer (5) having a dopant of a second conductivity type arranged on the active area (4); and a third layer (6) having a dopant of the second conductivity type, arranged on the second layer (5), the third layer (6) having a higher concentration of the dopant of the second conductivity type than the second layer (5); as well as - an electrically conductive contact layer (7) arranged on said third layer (6); wherein the functional layer stack (2) is limited in the lateral direction by a side surface (8) of the functional layer stack (2); The functional layer stack (2) comprises a central region (9) along a center line (10) of the functional layer stack (2); wherein the central region (9) is spaced apart from the side surface (8); and The current path from the conductive contact layer (7) through the third layer (6) to the second layer (5) is confined to the central area (9).

2. The optoelectronic device according to claim 1, wherein The third layer (6) is confined to the central area (9).

3. The optoelectronic device according to claim 1 or 2, wherein: The third layer (6) comprises at least one intersection (11), and the at least one intersection (11) divides the third layer (6) into at least a first area (6a) and a second area (6b) separated from each other, wherein the first area (6a) is confined to the central area (9).

4. An optoelectronic device according to any one of the preceding claims, wherein: The electrically conductive contact layer (7) is in electrical contact with the third layer (6) only in the central region (9) and / or is arranged on the third layer (6) only in the central region (9).

5. An optoelectronic device according to any one of the preceding claims, wherein: The third layer (6) or the third layer (6) and the second layer (5) comprises a first surface structure (12) having a plurality of protrusions and grooves on a surface facing the conductive contact layer (7).

6. The optoelectronic device according to claim 5, wherein: The protrusions of the first surface structure (12) in the central area (9) are higher than the protrusions of the first surface structure (12) outside the central area (9).

7. The optoelectronic device according to claim 5 or 6, wherein: At least the protrusions of the first surface structure (12) in the central region (9) have a planarized surface facing the electrically conductive contact layer (7).

8. The optoelectronic device according to any one of claims 5 to 7, wherein: In the central region (9), the protrusions of the first surface structure (12) are in electrical contact with the electrically conductive contact layer (7).

9. An optoelectronic device according to any one of the preceding claims, wherein: The second layer (5) comprises a second surface structure (13) having a plurality of protrusions and grooves on a surface facing the conductive contact layer (7), in particular in an area outside the central area (9).

10. The optoelectronic device according to any one of the preceding claims, further comprising a planarization layer (14) arranged on the third layer (6) and / or the second layer (5), wherein: The planarization layer (14) specifically fills the at least one intersection (11) and / or the grooves of the first surface structure (12) and / or the second surface structure (13).

11. The optoelectronic device according to claim 9, wherein: The planarization layer (14) is an electrically insulating material.

12. An optoelectronic device according to any one of the preceding claims, wherein: The central region (9) is limited to half the distance between two opposite side surfaces (8) of the functional layer stack (2).

13. An optoelectronic device according to any one of the preceding claims, wherein: The first layer (3) and / or the second layer (5) and / or the third layer (6) comprises a base material selected from the group consisting of: -GaN; -AlGaN; -AlGaInP; -AlGaInN; and -AlGaP.

14. A method for manufacturing at least one optoelectronic device (1), comprising the following steps: - providing a functional layer stack (2), the functional layer stack (2) comprising: - a first layer (3) having a dopant of a first conductivity type; - an active region (4) arranged on said first layer (3); - a second layer (5) having a dopant of a second conductivity type arranged on the active area (4); and a third layer (6) having a dopant of the second conductivity type, arranged on the second layer (5), the third layer (6) having a higher concentration of the dopant of the second conductivity type than the second layer (5); wherein the functional layer stack (2) is limited in the lateral direction by a side surface (8) of the functional layer stack (2); wherein the functional layer stack (2) comprises a central region (9) along a center line (10) of the functional layer stack (2); and wherein the central area (9) is spaced apart from the side surface (8); as well as - a conductive contact layer (7) is arranged on the third layer (6) so that the current path from the conductive contact layer (7) through the third layer (6) to the second layer (5) is limited to the central area (9).

15. The method according to claim 14, further comprising removing the third layer (6) in an area outside the central area (9).

16. The method according to claim 14 further includes creating at least one intersection (11) in the third layer (6), so that the at least one intersection (11) divides the third layer (6) into at least a first area (6a) and a second area (6b) separated from each other, and the first area (6a) is limited to the central area (9).

17. The method according to any one of claims 14 to 16, further comprising roughening a surface of the third layer (6) facing the conductive contact layer (7) to create a first surface structure (12) having a plurality of protrusions and grooves.

18. The method according to any one of claims 14 to 17, further comprising roughening the surface of the second layer (5) facing the conductive contact layer (7), in particular in an area outside the central area (9), to create a second surface structure (13) having a plurality of protrusions and grooves.

19. The method according to any one of claims 14 to 18, further comprising filling the at least one intersection (11) and / or the grooves of the first surface structure (12) and / or the second surface structure (13) with a filling material, in particular an electrically insulating filling material.

20. The method according to any one of claims 17 to 19, further comprising planarizing the protrusions of the first surface structure (12) at least in the central region (9).

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