AC108 audio chip control system and method based on FPGA module

Abstract

The invention discloses an AC108 audio chip control system and method based on an FPGA module, and the system comprises a clock and reset management module which is used for generating a stable clock signal and synchronizing a reset signal; the I2S / PCM driving control module is responsible for controlling a hardware reset signal of the chip and managing transmission and counting of audio data; the register configuration module is responsible for reading register data from an ROM (Read Only Memory) and sending the register data to the I2S / PCM driving control module; the FIFO module is used for temporarily storing register configuration data; and the I2S / PCM protocol bottom layer driver is used for processing the audio data and generating effective signals. The system provides accurate clock and reset management, flexible register configuration capability and a function of supporting four-channel data acquisition and analysis. Through a self-defined parameter configuration function and a soft reset function, the portability and the applicability of a driving program are remarkably improved, and the efficient control and optimization requirements on an AC108 chip on an FPGA platform are met.

Description

Technical Field

[0001] The present invention relates to the technical field of audio signal processing, and in particular to an AC108 audio chip control system and method based on an FPGA module. Background Art

[0002] The existing AC108 chip is a highly integrated four-channel ADC that supports I2S / TDM output conversion and is widely used in smart voice assistants, recording equipment, digital cameras, camcorders, and voice conferencing systems. However, the current drivers designed for the AC108 chip are usually developed in C language and rely on the Advanced Linux Sound Architecture (ALSA) for function control. Although the ALSA architecture provides rich audio processing functions, its complexity and bulkiness make it difficult for the driver to run efficiently on embedded systems and platforms with limited resources.

[0003] In addition, the portability of existing drivers is poor, especially on specific hardware platforms such as FPGA. It takes a lot of time and effort to adjust the driver to adapt to different architectures. Due to the high degree of encapsulation of ALSA, it is difficult for users to further customize and optimize the underlying hardware when facing specific application requirements, which limits the flexibility and applicability of the driver. In addition, when processing audio applications with high real-time requirements, the existing driver may not fully meet the strict delay requirements, affecting the processing quality of audio data and the stability of the system. These factors restrict the widespread application and performance optimization of the AC108 chip on the FPGA platform. Summary of the invention

[0004] The present invention aims at solving the defects of the prior art and provides an AC108 audio chip control system and method based on an FPGA module.

[0005] In order to achieve the above invention object, the technical solution adopted by the present invention is as follows:

[0006] An AC108 audio chip control system based on FPGA module, including the following modules:

[0007] Clock and reset management module: used to generate a stable clock signal, lock the board-level crystal oscillator signal through the phase-locked loop PLL, obtain the required TWI protocol clock, AC108 chip working clock and system main frequency. It is also responsible for generating the corresponding reset signal to ensure that the system runs synchronously in the same clock domain and reduce metastable phenomena.

[0008] I2S / PCM driver control module: controls the hardware reset signal RSTn of the AC108 chip and manages the transmission and analysis of audio data. It is responsible for counting the number of audio sampling points, receiving the sampling signal sent by the user, starting the sampling process, and sending configuration instructions to the AC108 chip according to the TWI protocol.

[0009] Register configuration module: responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to the I2S / PCM driver control module to complete the register configuration.

[0010] FIFO module: used to temporarily store register configuration data read from ROM to ensure correct data sequence and timing when transmitting to I2S / PCM driver control module.

[0011] I2S / PCM protocol bottom-level driver: According to the configured audio mode, 4-channel audio data is parsed through the frame-aligned clock, bit-aligned clock and data line, serial-to-parallel conversion is performed, and the corresponding valid signal is generated to indicate that the data is valid.

[0012] The present invention also discloses a control method based on the AC108 audio chip control system, comprising the following steps:

[0013] Step S1: After power-on, the board-level crystal oscillator signal is phase-locked by a phase-locked loop (PLL) to generate a stable clock signal.

[0014] Through frequency multiplication and division, the TWI protocol clock signal, AC108 chip working clock, and the main frequency suitable for the system are obtained.

[0015] Each clock signal generates a corresponding reset signal independently to ensure that the clock and reset signals are synchronized in the same clock domain and reduce the occurrence of metastable phenomena.

[0016] Step S2: The I2S / PCM drive control module pulls down the reset signal RSTn of the AC108 chip to ensure that all registers in the chip are restored to their initial states.

[0017] The reset signal is maintained for 20ms, then released, and then waited for another 20ms to ensure that the chip enters a stable working state and is ready to receive the user's sampling signal.

[0018] Step S3: The user sends a sampling trigger signal, and after the register configuration module detects the rising edge of the signal, it starts to read the register data from the ROM in sequence and temporarily stores it in the FIFO module of the I2S / PCM drive control module.

[0019] Step S4: After the register data stored in the FIFO is ready, the register configuration module sends the operation address, length, and read / write direction to the I2S / PCM drive control module according to the timing.

[0020] The configuration process is as follows: first configure the initialization information, and then perform additional configuration of parameter information after an interval of 50ms to ensure the success of the configuration process.

[0021] Step S5: The I2S / PCM drive control module parses the operation information sent in step S3, and sends configuration instructions to the AC108 chip through the TWI protocol.

[0022] Step S6: After the register configuration is completed, the I2S / PCM protocol bottom layer driver parses the 4-channel audio data received through the frame alignment clock, bit alignment clock and data line according to the configured audio mode, performs serial-to-parallel conversion and counts the audio sampling points.

[0023] A corresponding valid signal is generated on each channel to indicate that the data is valid.

[0024] Step S7: Send a soft reset instruction to restore the register of the AC108 chip to the initial state to stop the sampling process.

[0025] Furthermore, the configuration process includes two stages:

[0026] Configuration phase 1 includes: power supply configuration, clock configuration, enable reset configuration, frame alignment clock configuration, bit alignment clock configuration, I2S encoding configuration, sampling depth configuration, sampling order configuration, gain configuration, and analog channel configuration.

[0027] Configuration phase 2 includes: power supply configuration and sampling rate configuration.

[0028] Furthermore, the specific process of the soft reset instruction is as follows:

[0029] The sending operation address is 0x30, the operation data is 0x10, and the corresponding register name is I2S_CTRL. Its function is to turn off the frame alignment clock, bit alignment clock and data line.

[0030] The sending operation address is 0x00, the operation data is 0x12, and the corresponding register name is CHIP_AU DIO_RST. Its function is to restore all registers to their initial values.

[0031] Compared with the prior art, the advantages of the present invention are:

[0032] 1. High portability and applicability: By using Verilog language development, it can be easily deployed on the FPGA platform. Compared with the existing drivers that rely on ALSA, it has higher portability and wider applicability.

[0033] 2. Accurate clock and reset management: Use phase-locked loop (PLL) technology to generate a stable clock signal and ensure that the clock and reset signals run synchronously in the same clock domain, reducing metastable phenomena and ensuring system stability.

[0034] 3. Flexible register configuration: Two configuration stages are provided to accurately control and adjust system parameters, ensuring that all functions of the AC108 chip can be correctly configured and initialized, improving the flexibility and reliability of the system.

[0035] 4. Multi-channel data acquisition capability: The system supports 4-channel data acquisition and analysis, which can meet the needs of multi-channel audio signal processing and is suitable for various application scenarios such as smart voice assistants, recorders, cameras, etc.

[0036] 5. Custom parameter configuration and control: Allows users to customize sampling parameters and control the sampling process through the soft reset function, providing higher control flexibility and ease of system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural block diagram of the FPGA driver module according to an embodiment of the present invention.

[0038] Figure 2 It is a working flow chart of the FPGA driver module according to an embodiment of the present invention.

[0039] Figure 3 It is a schematic diagram of 4-channel data collected in the test mode and the corresponding validity diagram of the embodiment of the present invention.

[0040] Figure 4 It is a schematic diagram of data 5A5A collected from channel 1 in the test mode according to an embodiment of the present invention.

[0041] Figure 5 It is a waveform diagram of frame alignment, bit alignment clock and data lines observed by an oscilloscope in the test mode of an embodiment of the present invention.

[0042] Figure 6 This is a graph of 0.5V voltage values ​​collected in an actual working mode according to an embodiment of the present invention.

[0043] Figure 7 This is a graph of 1V voltage values ​​collected by an embodiment of the present invention in an actual working mode. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples.

[0045] like Figure 1 and 2 As shown, the present invention provides an AC108 audio chip control method based on an FPGA module, comprising the following steps:

[0046] Step S1: When the device is powered on, the clock and reset management module phase-locks the board-level crystal oscillator signal through a phase-locked loop to obtain a more stable clock signal, and obtains a 400KHz TWI protocol clock signal, a 24.576MHz AC108 chip working clock, and a system main frequency of any frequency by multiplying and dividing the frequency; each clock generates a corresponding reset signal separately to ensure that the clock and reset signals are in the same clock domain to reduce metastable phenomena.

[0047] Step S2: The I2S / PCM drive control module pulls down the AC108 hardware reset signal (RSTn) to ensure that all registers in the AC108 chip are restored to their initial state. The reset signal lasts for 20ms. After canceling the reset signal, wait for another 20ms to ensure that the chip works stably. Then it enters the normal working state and waits for the start sampling signal sent by the user.

[0048] Step S3: The user sends a sampling signal, and after the register configuration module detects the rising edge of the sampling signal, it reads out the register data stored in the ROM in sequence and sends it to the FIFO module in the I2S / PCM drive control module for temporary storage.

[0049] Step S4: After the register data in the ROM is successfully temporarily stored in the FIFO, the register configuration module sends the operation address, operation length, read and write direction and other information to the I2S / PCM drive control module according to the timing. The entire configuration phase is divided into two stages, first configuring the initialization information, with an interval of 50ms, and then supplementing the configuration parameter information to ensure successful configuration.

[0050] Step S5: The I2S / PCM drive control module parses the operation information sent in step S3, and sends configuration instructions to the AC108 chip through the bus according to the TWI protocol.

[0051] Step S6: After the register configuration is completed, the I2S / PCM protocol bottom layer driver parses the 4-channel data according to the configured audio mode through the frame alignment clock, bit alignment clock and data line, performs serial-to-parallel conversion, and generates a corresponding valid signal on each channel to indicate that the data is valid.

[0052] Step S7: Send a soft reset instruction to restore the AC108 register to stop sampling.

[0053] Test the acquisition constant function. Use Xilinx XC7S50FGGA484-1 chip as the experimental platform, use the built-in debug function of AC108 chip, test data is 5A5A, 96KHz sampling rate, 4-channel transmission, slot depth 16bit, data width 16bit, PCM TDM mode, LRCK changes on the falling edge of BCLK, data becomes valid on the second rising edge of BCLK after LRCK, change data on the falling edge of BCLK, read data on the rising edge. Figure 3 , Figure 4 Figure 5 As shown in the results, the driver correctly samples 5A5A.

[0054] like Figure 3 As shown, 4-channel data and corresponding valid signals:

[0055] In test mode, 4 channels of audio data are collected and valid signals are generated accordingly, which shows that the driver can correctly collect and process multi-channel data.

[0056] like Figure 4 As shown, the collected single channel data "5A5A:"

[0057] The driver successfully collected 5A5A data in test mode, verifying the correctness of data transmission and analysis. The sampling rate is 96KHz, the data width is 16bit, and the PCM TDM mode is used.

[0058] like Figure 5 As shown, the waveforms of frame alignment, bit alignment clock and data lines:

[0059] The waveform observed by the oscilloscope shows the timing relationship between the frame alignment clock (LRCK), bit alignment clock (BCLK) and data line during the transmission process. This result verifies the synchronization and correctness of the clock signal and the data line signal.

[0060] Test results in actual working mode

[0061] like Figure 6 As shown, the collected data of 0.5V voltage:

[0062] In the actual working mode, a signal generator is used to output a 0.5V DC signal, which is connected to the analog input of the AC108 chip. The driver successfully collects data and obtains a hexadecimal value of 1E8F (decimal 7823). The actual measured value is 0.501V, which is compared with the reference voltage of 2.1V, and the sampling result is accurate.

[0063] like Figure 7 As shown, the collected data of 1V voltage:

[0064] Similarly, in the actual working mode, a 1V DC signal is output, and the collected data is a hexadecimal value of 3717 (decimal 14103). The actual measured value is 0.903V, which is somewhat different from the expected value of 1V, but still within the acceptable range, indicating that the acquisition function of the driver is effective.

[0065] In another embodiment of the present invention, an AC108 audio chip control system based on an FPGA module is provided. The system can be used to implement the above-mentioned AC108 audio chip control method based on an FPGA module, specifically including:

[0066] Clock and reset management module: used to generate a stable clock signal, lock the board-level crystal oscillator signal through the phase-locked loop PLL, obtain the required TWI protocol clock, AC108 chip working clock and system main frequency. It is also responsible for generating the corresponding reset signal to ensure that the system runs synchronously in the same clock domain and reduce metastable phenomena.

[0067] I2S / PCM driver control module: controls the hardware reset signal RSTn of the AC108 chip and manages the transmission and analysis of audio data. It is responsible for counting the number of audio sampling points, receiving the sampling signal sent by the user, starting the sampling process, and sending configuration instructions to the AC108 chip according to the TWI protocol.

[0068] Register configuration module: responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to the I2S / PCM driver control module to complete the register configuration.

[0069] FIFO module: used to temporarily store register configuration data read from ROM to ensure correct data sequence and timing when transmitting to I2S / PCM driver control module.

[0070] I2S / PCM protocol bottom-level driver: According to the configured audio mode, 4-channel audio data is parsed through the frame-aligned clock, bit-aligned clock and data line, serial-to-parallel conversion is performed, and the corresponding valid signal is generated to indicate that the data is valid.

[0071] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0072] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0073] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0074] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0075] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the implementation methods of the present invention, and should be understood that the protection scope of the present invention is not limited to such special statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. An AC108 audio chip control system based on FPGA module, characterized in that: Includes the following modules: Clock and reset management module: used to generate a stable clock signal, lock the board-level crystal oscillator signal through the phase-locked loop PLL, obtain the required TWI protocol clock, AC108 chip working clock and system main frequency; it is also responsible for generating the corresponding reset signal to ensure that the system runs synchronously in the same clock domain and reduce metastable phenomena; I2S / PCM driver control module: controls the hardware reset signal RSTn of the AC108 chip and manages the transmission and analysis of audio data; is responsible for counting the number of audio sampling points, controls the sampling signal received from the user, starts the sampling process, and sends configuration instructions to the AC108 chip according to the TWI protocol; Register configuration module: responsible for reading register data from ROM and temporarily storing it in FIFO, and then sending information such as operation address, operation length and read / write direction to I2S / PCM driver control module to complete register configuration; FIFO module: used to temporarily store register configuration data read from ROM to ensure the correct data sequence and timing when transmitting to the I2S / PCM driver control module; I2S / PCM protocol bottom-level driver: According to the configured audio mode, 4-channel audio data is parsed through the frame-aligned clock, bit-aligned clock and data line, serial-to-parallel conversion is performed, and the corresponding valid signal is generated to indicate that the data is valid.

2. A control method based on the AC108 audio chip control system according to claim 1, characterized in that: The following steps are involved: Step S1: After power-on, the board-level crystal oscillator signal is phase-locked by a phase-locked loop (PLL) to generate a stable clock signal; Through frequency multiplication and division, the TWI protocol clock signal, AC108 chip working clock, and main frequency suitable for the system are obtained; Each clock signal generates a corresponding reset signal independently to ensure that the clock and reset signals are synchronized in the same clock domain, reducing the occurrence of metastable phenomena; Step S2: The I2S / PCM drive control module pulls down the reset signal RSTn of the AC108 chip to ensure that all registers in the chip are restored to their initial state; The reset signal is maintained for 20ms, then released, and then waited for another 20ms to ensure that the chip enters a stable working state and is ready to receive the user's sampling signal; Step S3: The user sends a sampling trigger signal, and after the register configuration module detects the rising edge of the signal, it starts to read the register data from the ROM in sequence and temporarily stores it in the FIFO module of the I2S / PCM drive control module; Step S4: After the register data stored in the FIFO is ready, the register configuration module sends the operation address, length, and read / write direction to the I2S / PCM drive control module according to the timing; The configuration process is as follows: first configure the initialization information, and then perform additional configuration of parameter information after an interval of 50ms to ensure the success of the configuration process; Step S5: The I2S / PCM drive control module parses the operation information sent in step S3, and sends a configuration instruction to the AC108 chip via the TWI protocol; Step S6: After the register configuration is completed, the I2S / PCM protocol bottom layer driver parses the 4-channel audio data received through the frame alignment clock, bit alignment clock and data line according to the configured audio mode, and performs serial-to-parallel conversion; Generate a corresponding valid signal on each channel to indicate that the data is valid; Step S7: Send a soft reset instruction to restore the register of the AC108 chip to the initial state to stop the sampling process.

3. The control method according to claim 2, characterized in that: The configuration process consists of two stages: Configuration phase 1 includes: power supply configuration, clock configuration, enable reset configuration, frame alignment clock configuration, bit alignment clock configuration, I2S encoding configuration, sampling depth configuration, sampling order configuration, gain configuration and analog channel configuration; Configuration phase 2 includes: power supply configuration and sampling rate configuration.

4. The control method according to claim 2, characterized in that: The specific process of the soft reset instruction is as follows: The sending operation address is 0x30, the operation data is 0x10, and the corresponding register name is I2S_CTRL; its function is to turn off the frame alignment clock, bit alignment clock and data line; The sending operation address is 0x00, the operation data is 0x12, and the corresponding register name is CHIP_AUDIO_RST; its function is to restore all registers to their initial values.

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