Virtual machine thread scheduling method and equipment

Abstract

The embodiment of the invention provides a virtual machine thread scheduling method and device, and the method comprises the steps: responding to a received scheduling instruction for a first VCPU thread on a virtual processor of a virtual machine, and determining the processor affinity of the first VCPU thread through a load balancing scheduler; according to the processor affinity of the first VCPU thread, determining that the processor affinity of a second VCPU thread in the virtual processor is a second super-thread logic processor in the target physical processor; according to the processor affinity of the first VCPU thread, scheduling the first hyper-thread logic processor to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, scheduling the second super-thread logic processor to run the second VCPU thread. According to the method, the stability of the virtual machine is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of cloud computing technology, and in particular to a method and device for scheduling virtual machine threads. Background Art

[0002] In cloud computing scenarios, based on the binding status of VCPU (Virtual Central Processing Unit) threads in the virtual processors of virtual machines, virtual processors can be roughly divided into two categories: dedicated instance virtual processors and oversold instance virtual processors. Among them, dedicated instance virtual processors bind VCPU threads to PCPU (Physical Central Processing Unit) one-to-one, and do not bind multiple VCPU threads to the same PCPU at the same time. This type of instance has the highest performance.

[0003] Now, all physical processors of X86 architecture provide hyperthreading capability, which divides a physical processor into two HT logical cores (Hyper-Threading, hyperthreaded logical processors), which can improve the throughput of the physical processor. Turning on / off hyperthreading will affect the overall performance of the physical processor. Assuming that after turning off hyperthreading, the maximum computing performance of a physical processor is X, then after turning on hyperthreading, the maximum computing performance of a physical processor is 1.3X, and at this time, two hyperthreaded logical processors run tasks at the same time.

[0004] The inventors have discovered that the prior art has at least the following technical problems: when the physical processor has hyperthreading enabled, the performance stability of the virtual machine is poor. Summary of the invention

[0005] The embodiments of the present disclosure provide a method and device for scheduling virtual machine threads, which can improve the stability of virtual machine operation.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for scheduling a virtual machine thread, comprising:

[0007] In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining a processor affinity of the first VCPU thread by a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs;

[0008] Determining, according to the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor;

[0009] According to the processor affinity of the first VCPU thread, the first hyperthreaded logical processor is scheduled to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, the second hyperthreaded logical processor is scheduled to run the second VCPU thread.

[0010] In a second aspect, an embodiment of the present disclosure provides a scheduling device for a virtual machine thread, including:

[0011] a receiving unit, configured to determine, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, a processor affinity of the first VCPU thread through a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs;

[0012] a determining unit, configured to determine, based on the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor;

[0013] A scheduling unit is used to schedule the first hyperthreaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and to schedule the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0014] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: a processor and a memory;

[0015] The memory stores computer-executable instructions;

[0016] The processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the virtual machine thread scheduling method described in the first aspect and various possible designs of the first aspect.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, in which computer execution instructions are stored. When a processor executes the computer execution instructions, the scheduling method of the virtual machine thread as described in the first aspect and various possible designs of the first aspect is implemented.

[0018] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, including a computer program, which, when executed by a processor, implements the scheduling method for virtual machine threads as described in the first aspect and various possible designs of the first aspect.

[0019] The present embodiment provides a method and device for scheduling virtual machine threads, the method comprising: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancing scheduler, the processor affinity of the first VCPU thread being used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs; according to the processor affinity of the first VCPU thread, determining the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor; according to the processor affinity of the first VCPU thread, scheduling the first hyperthreaded logical processor to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, scheduling the second hyperthreaded logical processor to run the second VCPU thread. In this technical solution, the processor affinity of the second VCPU thread in the virtual processor is determined based on the processor affinity of the first VCPU thread, ensuring that the hyper-threaded logical processor running the first VCPU thread and the hyper-threaded logical processor running the second VCPU thread are in the same physical processor, thereby solving the performance burst problem caused by two VCPU threads in the same virtual processor running on two physical processors at the same time, thereby improving the stability of the virtual processor operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 Schematic diagram of a virtual machine thread scheduling method provided by the prior art Figure 1 ;

[0022] Figure 2 The process of the virtual machine thread scheduling method provided by the embodiment of the present disclosure Figure 1 ;

[0023] Figure 3 Schematic diagram of a virtual machine thread scheduling method provided in an embodiment of the present disclosure Figure 1 ;

[0024] Figure 4 Schematic diagram of a virtual machine thread scheduling method provided by the prior art Figure 2 ;

[0025] Figure 5The process of the virtual machine thread scheduling method provided by the embodiment of the present disclosure Figure 2 ;

[0026] Figure 6 Schematic diagram of a virtual machine thread scheduling method provided in an embodiment of the present disclosure Figure 2 ;

[0027] Figure 7 A schematic diagram of the structure of a scheduling device for virtual machine threads provided in an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] In the cloud computing scenario, according to the binding status of the VCPU (Virtual Central Processing Unit) threads in the virtual processor of the virtual machine, the virtual processors can be roughly divided into two categories: exclusive instance virtual processors and oversold instance virtual processors. Among them, the exclusive instance virtual processor binds the VCPU thread to the PCPU (Physical Central Processing Unit) one-to-one, and does not bind multiple VCPU threads to the same PCPU at the same time. This type of instance has the highest performance. Among them, the oversold instance virtual processor binds the VCPU thread to multiple PCPUs, and sells the PCPU according to a certain oversold ratio. For example: there are 10 PCPUs on the physical processor. If it is oversold by 2 times, 20 VCPUs will be displayed on this physical processor. This type of instance is cheap, but the performance jitter is relatively large.

[0032] Now all physical processors of X86 architecture provide hyperthreading capability, which divides a physical processor into two HT logical cores (Hyper-Threading, hyperthreaded logical processors), which can improve the throughput of the physical processor. Turning on / off hyperthreading will affect the overall performance of the physical processor. Assuming that after turning off hyperthreading, the maximum computing performance of a physical processor is X, then after turning on hyperthreading, the maximum computing performance of a physical processor is 1.3X, and at this time, two hyperthreaded logical processors run tasks at the same time. The maximum computing performance of a single hyperthreaded logical processor is still X, and at this time one HT hyperthread runs tasks, and the other HT hyperthread does not run tasks.

[0033] This application mainly solves two performance jitter problems of oversold instances in cloud computing scenarios. The first performance jitter problem is how to solve the performance burst problem caused by two VCPU threads in a virtual processor running on two physical processors at the same time. The second performance jitter problem is how to avoid VCPU threads on different virtual processors running on the same physical processor at the same time, causing performance interference.

[0034] The introduction and solution to the first performance jitter problem are as follows: In an oversold scenario, the VCPU threads in the virtual processor of the oversold instance need to be bound to cores. As a result, two VCPU threads of the same virtual processor will run on two hyperthreaded logical processors of two physical processors. This may cause the computing performance of one virtual processor to be equivalent to that of two physical processors.

[0035] For example, Figure 1 As shown, the virtual processor contains two VCPU threads (such as Figure 1 VCPU thread 0 and VCPU thread 1) run simultaneously on two hyperthreaded logical processors of two physical processors (such as Figure 1 In this case, the computing performance of a virtual processor is the sum of the performance of the two physical processors (for example, 2X). When the two VCPU threads contained in a virtual processor run on the two HT hyperthreads on the same physical processor, the computing performance of a virtual processor is at most 1.3X. This will lead to unstable running performance of the virtual processor. Moreover, in the exclusive scenario, the two VCPU threads of each virtual processor will only be bound to the two hyperthreaded logical processors on one physical processor, so the computing performance of a virtual processor is equal to the computing performance of one physical processor. In this way, the performance of the virtual processor of the cheap oversold instance may be higher than that of the expensive exclusive instance virtual processor, which is not what the cloud service provider wants.

[0036] The inventors have discovered that the prior art has at least the following technical problems: when the physical processor has hyperthreading enabled, the performance stability of the virtual processor is poor.

[0037] In view of the technical problems in the prior art, the inventor's technical idea is as follows: two VCPU threads of a virtual processor can only run on the same physical processor at the same time. In order to ensure that two VCPU threads in the same virtual processor run on the same physical processor, the running VCPU threads can be dynamically bound to the core.

[0038] Corresponding specific steps may include: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancing scheduler, the processor affinity of the first VCPU thread being used to configure a first hyper-threaded logical processor running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs; according to the processor affinity of the first VCPU thread, determining the processor affinity of the second VCPU thread in the virtual processor as the second hyper-threaded logical processor in the target physical processor; according to the processor affinity of the first VCPU thread, scheduling the first hyper-threaded logical processor to run the first VCPU thread; and, according to the processor affinity of the second VCPU thread, scheduling the second hyper-threaded logical processor to run the second VCPU thread.

[0039] In this technical solution, since the processor affinity of the second VCPU thread in the virtual processor is determined based on the processor affinity of the first VCPU thread, it is ensured that the hyper-threaded logical processor running the first VCPU thread and the hyper-threaded logical processor running the second VCPU thread are in the same physical processor, which solves the performance mutation problem caused by two VCPU threads in the same virtual processor running on two physical processors at the same time, thereby improving the stability of the virtual processor operation.

[0040] The following is a specific implementation process of the virtual machine thread scheduling method and device involved in the embodiment of the present disclosure, some examples are only for example and not for limitation. The execution subject of the virtual machine thread scheduling method involved in the embodiment of the present disclosure is an electronic device, which can be a terminal, a server, etc.

[0041] Figure 2 The scheduling method process of the virtual machine thread provided by the embodiment of the present disclosure Figure 1 ,like Figure 2 As shown, the scheduling method of the virtual machine thread may include:

[0042] S201. In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, a processor affinity of the first VCPU thread is determined by a load balancing scheduler, and the processor affinity of the first VCPU thread is used to configure a first hyper-threaded logical processor running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs.

[0043] In the embodiment of the present disclosure, the virtual machine includes one or more virtual processors, and the first VCPU thread and the second VCPU thread represent two different virtual hyperthreads on the same virtual processor. The physical machine includes one or more physical processors, and the first hyperthreaded logical processor and the second hyperthreaded logical processor represent two different hyperthreaded logical processors on the same physical processor. Among them, the hyperthreaded logical processor can also be called a logical core. The physical processor can be called a physical core.

[0044] In some embodiments, the first VCPU thread is scheduled by a load balancing scheduler. Accordingly, this step may include: in response to receiving a scheduling instruction for the first virtual processor VCPU thread on the virtual processor of the virtual machine, determining the target physical processor with the smallest load from multiple candidate physical processors by the load balancing scheduler; and determining that the processor affinity of the first VCPU thread is the first hyperthreaded logical processor in the target physical processor with the smallest load.

[0045] In the embodiment of the present disclosure, the thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities. The first VCPU thread may be a VCPU thread with an even thread number or a VCPU thread with an odd thread number. For example, the thread number of the first VCPU thread is an even number and the thread number of the second VCPU thread is an odd number, or the thread number of the first VCPU thread is an odd number and the thread number of the second VCPU thread is an even number.

[0046] Optionally, the first VCPU thread may be a VCPU thread with an even-numbered thread number. Figure 3 As shown, the first VCPU thread is VCPU thread 0 in the virtual processor.

[0047] S202: Determine, according to the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor.

[0048] In the embodiment of the present disclosure, the thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

[0049] In some embodiments, the thread number of the first VCPU thread is an even number, and the thread number of the second VCPU thread is an odd number; in this case, the processor affinity of the even-numbered VCPU thread can be scheduled by the load balancing scheduler. The processor affinity of the odd-numbered VCPU thread is adjusted as the processor affinity of the even-numbered VCPU thread is adjusted.

[0050] For example, Figure 3 As shown, the first VCPU thread is VCPU thread 0 in the virtual processor, and the thread number is an even number. The second VCPU thread is VCPU thread 1 in the virtual processor, and the thread number is an odd number. The processor affinity of VCPU thread 0 can be scheduled by the load balancing scheduler. The processor affinity of VCPU thread 1 is adjusted as the processor affinity of VCPU thread 0 is adjusted.

[0051] like Figure 3 As shown, when the processor affinity of VCPU thread 0 is TH hyperthread 0 on physical processor 0, the processor affinity of VCPU thread 1 is adjusted to TH hyperthread 1 on physical processor 0. When the processor affinity of VCPU thread 0 is TH hyperthread 0 on physical processor 1, the processor affinity of VCPU thread 1 is adjusted to TH hyperthread 1 on physical processor 1.

[0052] In some other embodiments, the thread number of the first VCPU thread is an odd number, and the thread number of the second VCPU thread is an even number. In this case, the processor affinity of the odd-numbered VCPU thread can be scheduled by the load balancing scheduler. The processor affinity of the even-numbered VCPU thread is adjusted as the processor affinity of the odd-numbered VCPU thread is adjusted.

[0053] S203. According to the processor affinity of the first VCPU thread, schedule the first hyperthreading logical processor to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, schedule the second hyperthreading logical processor to run the second VCPU thread.

[0054] In some embodiments, before scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method also includes: determining the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is a running state, scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0055] The embodiment of the present disclosure provides a scheduling method for virtual machine threads: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancing scheduler, the processor affinity of the first VCPU thread being used to configure a first hyper-threaded logical processor running the first VCPU thread and a target physical processor to which the first hyper-threaded logical processor belongs; according to the processor affinity of the first VCPU thread, determining the processor affinity of the second VCPU thread in the virtual processor as the second hyper-threaded logical processor in the target physical processor; according to the processor affinity of the first VCPU thread, scheduling the first hyper-threaded logical processor to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, scheduling the second hyper-threaded logical processor to run the second VCPU thread. In this technical solution, since the processor affinity of the second VCPU thread in the virtual processor is determined based on the processor affinity of the first VCPU thread, it is ensured that the hyper-threaded logical processor running the first VCPU thread and the hyper-threaded logical processor running the second VCPU thread are in the same physical processor, which solves the performance mutation problem caused by two VCPU threads in the same virtual processor running on two physical processors at the same time, thereby improving the stability of the virtual processor operation.

[0056] The introduction and solution to the second performance jitter problem are as follows: In an oversold scenario, different virtual processors may have the following performance interference. For example, Figure 4 As shown in the figure: a VCPU thread 0 in virtual processor 1 and a VCPU thread 1 in virtual processor 2 are running on two hyper-threaded logical processors (HT hyper-thread 0 and TH hyper-thread 1) of the same physical processor at the same time. At this time, the performance of the hyper-threaded logical processor corresponding to virtual processor 1 and the performance of the hyper-threaded logical processor corresponding to virtual processor 2 will be affected, thereby affecting the stability of the virtual processor operation.

[0057] The core idea of ​​this solution is: when a VCPU thread in a virtual processor is running and another VCPU thread is not running, ensure that the non-running VCPU thread occupies another hyperthreaded logical processor on the same physical processor. In this way, it is possible to avoid the VCPU threads running on other virtual processors being scheduled to the physical processor. Figure 5 As shown, the method includes:

[0058] S501: Obtain the working status of two VCPU threads running on each virtual processor.

[0059] The working states of the VCPU threads include: running state; runnable state, that is, the state of waiting to be scheduled; and dormant state.

[0060] S502: If a VCPU thread on the same virtual processor is in a running state and occupies a hyperthreaded logical processor of a physical processor, and another VCPU thread is in a dormant state, then wake up the other VCPU thread in the dormant state and seize another hyperthreaded logical processor of the physical processor.

[0061] In this step, when a VCPU thread is being processed by the first hyperthreaded logical processor on the physical processor, another VCPU thread in a dormant state is awakened to avoid scheduling VCPU threads running on other virtual processors to the physical processor.

[0062] In some embodiments, a VCPU thread on a virtual processor runs on a hyper-threaded logical processor of a physical processor; accordingly, another VCPU thread in a dormant state is awakened, and another hyper-threaded logical processor of the physical processor is preempted, including: sending a wake-up instruction to another VCPU thread in a dormant state, awakening another VCPU thread in a dormant state, and letting the awakened VCPU thread execute an mwait (processor wait) instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in a low power consumption mode.

[0063] For example, Figure 6 As shown, VCPU thread 0 on virtual processor 1 is in the running state, and VCPU thread 1 on virtual processor 1 is in the dormant state. Among them, VCPU thread 0 on virtual processor 1 runs on TH hyperthread 0 on the physical processor. At this time, in order to prevent VCPU threads running on other virtual processors from being scheduled to the physical processor, VCPU thread 1 on virtual processor 1 can be awakened to preempt another hyperthreaded logical processor on the same physical processor ( Figure 6 TH Hyperthreading in 1).

[0064] For example, Figure 6As shown, VCPU thread 1 on virtual processor 2 is in the running state, and VCPU thread 0 on virtual processor 2 is in the dormant state. Among them, VCPU thread 1 on virtual processor 2 runs on TH hyperthread 1 on the physical processor. At this time, in order to prevent VCPU threads running on other virtual processors from being scheduled to the physical processor, VCPU thread 0 on virtual processor 2 can be awakened to preempt another hyperthreaded logical processor on the same physical processor ( Figure 6 TH Hyperthreading 0 in.

[0065] It should be noted that if the working state of a VCPU thread on the same virtual processor is switched from the running state to the sleeping state, another VCPU thread is controlled to stop executing the mwait instruction and switch to the sleeping state.

[0066] In the embodiment of the present disclosure, when a VCPU thread on a virtual processor is processed by the first hyper-threaded logical processor on the physical processor, by waking up another VCPU thread in a dormant state on the virtual processor, it is possible to avoid scheduling VCPU threads running on other virtual processors to the physical processor. At this time, the computing power of the VCPU thread processed by the first hyper-threaded logical processor is equivalent to the computing power of the physical processor, thereby ensuring that the performance of the running VCPU thread is not affected.

[0067] It should be noted that the above scheduling method is a virtual machine thread scheduling method based on the KVM (kernel-based virtual machine) side, which not only effectively solves the performance jitter problem of the virtual machine after Hyper-Threading (TH) is enabled in the oversold scenario. Moreover, the advantage of the virtual machine thread scheduling method based on the KVM side is that the virtual machine can be flexibly hot-upgraded without relying on the kernel or other component versions.

[0068] Figure 7 A structural diagram of a virtual machine thread scheduling device provided in an embodiment of the present disclosure, such as Figure 7 As shown, the scheduling device of the virtual machine thread includes:

[0069] A receiving unit 701 is configured to determine, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, a processor affinity of the first VCPU thread through a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs;

[0070] A determining unit 702 is configured to determine, based on the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor;

[0071] The scheduling unit 703 is used to schedule the first hyperthreading logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and to schedule the second hyperthreading logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0072] According to one or more embodiments of the present disclosure, the thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

[0073] According to one or more embodiments of the present disclosure, the scheduling unit 703 is also used to determine the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is in a running state, then according to the processor affinity of the second VCPU thread, the second hyper-threaded logical processor is scheduled to run the second VCPU thread.

[0074] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, each of which runs two VCPU threads; accordingly, the scheduling unit 703 is also used to obtain the working status of the two VCPU threads running on each virtual processor; if a VCPU thread on the same virtual processor is in a running state and occupies a hyper-threaded logical processor of a physical processor, and another VCPU thread is in a dormant state, then the other VCPU thread in the dormant state is awakened and another hyper-threaded logical processor of the physical processor is preempted.

[0075] According to one or more embodiments of the present disclosure, the scheduling unit 703 wakes up another VCPU thread in a dormant state and preempts another hyper-threaded logical processor of the physical processor, including: sending a wake-up instruction to another VCPU thread in a dormant state, waking up another VCPU thread in a dormant state, and letting the awakened VCPU thread execute a processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in a low power consumption mode.

[0076] According to one or more embodiments of the present disclosure, the scheduling unit 703 is also used to control another VCPU thread to stop executing the mwait instruction and switch to the sleep state if the working state of a VCPU thread on the same virtual processor switches from the running state to the sleep state.

[0077] According to one or more embodiments of the present disclosure, the determination unit 702, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determines the processor affinity of the first VCPU thread through a load balancing scheduler, including: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of the virtual machine, determining a target physical processor with the smallest load from multiple candidate physical processors through a load balancing scheduler; determining the processor affinity of the first VCPU thread to be the first hyper-threaded logical processor in the target physical processor with the smallest load.

[0078] refer to Figure 8 , which shows a schematic diagram of the structure of an electronic device 800 suitable for implementing the embodiment of the present disclosure, and the electronic device 800 may be a terminal device or a server. The terminal device may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers, portable multimedia players (PMPs), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0079] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 to a random access memory (RAM) 803. Various programs and data required for the operation of the electronic device 800 are also stored in the RAM 803. The processing device 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0080] Typically, the following devices may be connected to the I / O interface 805: input devices 806 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 808 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 809. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0081] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by the processing device 801, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0082] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0083] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0084] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0085] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0086] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0087] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a unit does not limit the unit itself in some cases. For example, the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses".

[0088] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0089] In a first aspect, according to one or more embodiments of the present disclosure, a method for scheduling a virtual machine thread is provided, comprising:

[0090] In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining a processor affinity of the first VCPU thread by a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs;

[0091] Determining, according to the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor;

[0092] According to the processor affinity of the first VCPU thread, the first hyperthreaded logical processor is scheduled to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, the second hyperthreaded logical processor is scheduled to run the second VCPU thread.

[0093] According to one or more embodiments of the present disclosure, the thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

[0094] According to one or more embodiments of the present disclosure, before scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method also includes: determining the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is a running state, scheduling the second hyper-threaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0095] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, each of which runs two VCPU threads; accordingly, the method also includes: obtaining the working status of the two VCPU threads running on each virtual processor; if a VCPU thread on the same virtual processor is in a running state and occupies a hyper-threaded logical processor of a physical processor, and another VCPU thread is in a dormant state, then waking up the other VCPU thread in the dormant state and preempting another hyper-threaded logical processor of the physical processor.

[0096] According to one or more embodiments of the present disclosure, waking up another VCPU thread in a dormant state and preempting another hyper-threaded logical processor of the physical processor includes: sending a wake-up instruction to another VCPU thread in a dormant state, waking up another VCPU thread in a dormant state, and letting the awakened VCPU thread execute a processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in a low power consumption mode.

[0097] According to one or more embodiments of the present disclosure, the method further includes: if the working state of a VCPU thread on the same virtual processor switches from a running state to a sleeping state, controlling another VCPU thread to stop executing the mwait instruction and switch to a sleeping state.

[0098] According to one or more embodiments of the present disclosure, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread through a load balancing scheduler includes: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of the virtual machine, determining a target physical processor with the smallest load from multiple candidate physical processors through a load balancing scheduler; and determining the processor affinity of the first VCPU thread to be the first hyper-threaded logical processor in the target physical processor with the smallest load.

[0099] In a second aspect, according to one or more embodiments of the present disclosure, a scheduling device for a virtual machine thread is provided, comprising:

[0100] a receiving unit, configured to determine, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, a processor affinity of the first VCPU thread through a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs;

[0101] a determining unit, configured to determine, based on the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor;

[0102] A scheduling unit is used to schedule the first hyperthreaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and to schedule the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

[0103] According to one or more embodiments of the present disclosure, the thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

[0104] According to one or more embodiments of the present disclosure, the scheduling unit is also used to determine the working state of the second VCPU thread on the virtual processor; if the working state of the second VCPU thread is running, then according to the processor affinity of the second VCPU thread, the second hyper-threaded logical processor is scheduled to run the second VCPU thread.

[0105] According to one or more embodiments of the present disclosure, the virtual machine includes multiple virtual processors, each of which runs two VCPU threads; accordingly, the scheduling unit is also used to obtain the working status of the two VCPU threads running on each virtual processor; if a VCPU thread on the same virtual processor is in a running state and occupies a hyper-threaded logical processor of a physical processor, and another VCPU thread is in a dormant state, then the other VCPU thread in the dormant state is awakened and another hyper-threaded logical processor of the physical processor is preempted.

[0106] According to one or more embodiments of the present disclosure, the scheduling unit wakes up another VCPU thread in a dormant state and preempts another hyper-threaded logical processor of the physical processor, including: sending a wake-up instruction to another VCPU thread in a dormant state, waking up another VCPU thread in a dormant state, and letting the awakened VCPU thread execute a processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in a low power consumption mode.

[0107] According to one or more embodiments of the present disclosure, the scheduling unit is also used to control another VCPU thread to stop executing the mwait instruction and switch to the sleep state if the working state of a VCPU thread on the same virtual processor switches from the running state to the sleep state.

[0108] According to one or more embodiments of the present disclosure, the determination unit, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determines the processor affinity of the first VCPU thread through a load balancing scheduler, including: in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of the virtual machine, determining a target physical processor with the smallest load from multiple candidate physical processors through a load balancing scheduler; determining the processor affinity of the first VCPU thread to be the first hyper-threaded logical processor in the target physical processor with the smallest load.

[0109] In a third aspect, according to one or more embodiments of the present disclosure, there is provided an electronic device, comprising: at least one processor and a memory;

[0110] The memory stores computer-executable instructions;

[0111] The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the virtual machine thread scheduling method described in the first aspect and various possible designs of the first aspect.

[0112] In a fourth aspect, according to one or more embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer execution instructions. When a processor executes the computer execution instructions, the scheduling method of the virtual machine thread as described in the first aspect and various possible designs of the first aspect is implemented.

[0113] In a fifth aspect, according to one or more embodiments of the present disclosure, a computer program product is provided, including a computer program, which, when executed by a processor, implements the scheduling method for virtual machine threads as described in the first aspect and various possible designs of the first aspect.

[0114] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0115] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0116] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for scheduling virtual machine threads, characterized in that: include: In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining a processor affinity of the first VCPU thread by a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs; Determining, according to the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor; According to the processor affinity of the first VCPU thread, the first hyperthreaded logical processor is scheduled to run the first VCPU thread; and according to the processor affinity of the second VCPU thread, the second hyperthreaded logical processor is scheduled to run the second VCPU thread.

2. The method according to claim 1, characterized in that The thread number of the first VCPU thread and the thread number of the second VCPU thread have different parities.

3. The method according to claim 1, characterized in that Before scheduling the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread, the method further includes: Determine the working state of the second VCPU thread on the virtual processor; If the working state of the second VCPU thread is in the running state, the second hyper-threading logical processor is scheduled to run the second VCPU thread according to the processor affinity of the second VCPU thread.

4. The method according to claim 1, characterized in that: The virtual machine includes a plurality of virtual processors, and each virtual processor runs two VCPU threads; accordingly, the method further includes: Get the working status of the two VCPU threads running on each virtual processor; If a VCPU thread on the same virtual processor is in running state and occupies a hyperthreaded logical processor of the physical processor, and another VCPU thread is in sleep state, then the other VCPU thread in sleep state is awakened and seizes another hyperthreaded logical processor of the physical processor.

5. The method according to claim 4, characterized in that The step of waking up another VCPU thread in a dormant state and preempting another hyperthreaded logical processor of the physical processor includes: Send a wake-up instruction to another VCPU thread in a dormant state to wake up the other VCPU thread in a dormant state, and let the awakened VCPU thread execute a processor wait mwait instruction to preempt another hyper-threaded logical processor of the physical processor; wherein the mwait instruction is used to put the VCPU thread in a low power consumption mode.

6. The method according to claim 4, characterized in that The method further comprises: If the working state of a VCPU thread on the same virtual processor is switched from the running state to the sleeping state, another VCPU thread is controlled to stop executing the mwait instruction and switch to the sleeping state.

7. The method according to any one of claims 1 to 6, characterized in that: In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining the processor affinity of the first VCPU thread by a load balancing scheduler includes: In response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, determining a target physical processor with the smallest load from a plurality of candidate physical processors through a load balancing scheduler; The processor affinity of the first VCPU thread is determined to be a first hyperthreaded logical processor in a target physical processor with the smallest load.

8. A scheduling device for a virtual machine thread, characterized in that: include: a receiving unit, configured to determine, in response to receiving a scheduling instruction for a first virtual processor VCPU thread on a virtual processor of a virtual machine, a processor affinity of the first VCPU thread through a load balancing scheduler, wherein the processor affinity of the first VCPU thread is used to configure a first hyperthreaded logical processor running the first VCPU thread and a target physical processor to which the first hyperthreaded logical processor belongs; a determining unit, configured to determine, based on the processor affinity of the first VCPU thread, the processor affinity of the second VCPU thread in the virtual processor as the second hyperthreaded logical processor in the target physical processor; A scheduling unit is used to schedule the first hyperthreaded logical processor to run the first VCPU thread according to the processor affinity of the first VCPU thread; and to schedule the second hyperthreaded logical processor to run the second VCPU thread according to the processor affinity of the second VCPU thread.

9. An electronic device, characterized in that: include: Processor and memory; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor executes the virtual machine thread scheduling method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When the processor executes the computer-executable instructions, the virtual machine thread scheduling method according to any one of claims 1 to 7 is implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for scheduling a virtual machine thread according to any one of claims 1 to 7 is implemented.

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