Memory device and control method based on computing fast link protocol

Abstract

The embodiments of the present disclosure provide a memory device and control method based on the computing fast link protocol. The memory device includes a plurality of dynamic random access memories and non-volatile memories and a controller of the memory device, the controller including a CXL subsystem; a cache manager, which stores a cache table recording the mapping relationship between the device physical address and the cache address; the controller of the dynamic random access memory is configured to perform a read or write operation on the dynamic random access memory according to the cache address; the controller of the non-volatile memory is configured to perform a read or write operation on the non-volatile memory according to the device physical address, so as to write data from the dynamic random access memory to the non-volatile memory, or read data from the non-volatile memory for storage in the dynamic random access memory. The embodiments of the present disclosure implement memory expansion based on the existing server architecture, thereby reducing the cost of using memory.

Description

Technical Field

[0001] The present disclosure relates to the field of data storage, and in particular to a memory device and a control method based on a computing fast link protocol. Background Art

[0002] The Compute Express Link (CXL) protocol is a high-performance, low-latency interconnect protocol for connecting processors, accelerators, storage, and other computing resources. It is designed to provide high-bandwidth, low-latency, and efficient connections to meet the needs of modern data centers and high-performance computing environments.

[0003] The common memory expansion under the CXL protocol uses a dual in-line memory module (DIMM) as a data storage medium. Compared with other storage media, this memory has the characteristics of high performance and low latency. However, the memory stick needs to use a memory interface, occupies a large physical space, and the capacity of each memory stick is limited. The capacity of a single memory stick does not exceed 512GB, and the cost is relatively high.

[0004] At present, some solutions use the traditional double data rate (DDR) memory combined with the DDR memory connected under the CXL protocol, but its cost is still very high. Other memory expansion methods include using PCIe to connect solid-state drives (SSDs) for memory use, but this method will greatly reduce performance.

[0005] In the cloud platform, many virtual machines need to apply for a large amount of memory, but in actual use, these virtual machines do not need to use the memory at the same time. If all DDR memory is used, the cost will be high, the area occupied will be large, the utilization rate will be low, and a lot of waste will be caused. Summary of the invention

[0006] In order to achieve high-performance and low-cost ultra-large memory, the first aspect of the present disclosure provides a memory device based on the computing fast link protocol. The memory device includes multiple volatile access memories and multiple non-volatile memories; and a controller of the memory device based on the computing fast link protocol, which includes a CXL subsystem, the CXL subsystem includes an interface for communicating with the host, and is configured to receive a read or write instruction containing a device physical address from the host; a cache manager, which stores a cache table recording the mapping relationship between the device physical address and the cache address, and is configured to return the cache address to the CXL subsystem according to the device physical address received from the CXL subsystem, and segment the storage space of the dynamic random access memory according to the number and block size of the non-volatile memory, so that data is transmitted in parallel between the dynamic random access memory and the non-volatile memory in segments; a controller of the dynamic random access memory, which is connected to the cache manager and is configured to receive a read or write request from the cache manager , performing a read or write operation on the dynamic random access memory according to the cache address; a controller of the non-volatile memory, which is connected to the cache manager and is configured to receive a read or write request from the cache manager, and perform a read or write operation on the non-volatile memory according to the device physical address to write data from the dynamic random access memory to the non-volatile memory, or read data from the non-volatile memory to store it in the dynamic random access memory, wherein each non-volatile memory includes an additional write layer and a random write layer, when new data is received, the new data is written to the end of the additional write layer, and when a predetermined condition is met, part or all of the data in the additional write layer is merged and written to the random write layer, and the dynamic mapping relationship between the physical address and the address of the non-volatile memory is stored in an index table of the non-volatile memory and updated each time data is written.

[0007] The device disclosed in the present invention uses non-volatile memory as an extension of dynamic random access memory, and manages all memories in a unified manner, so that it can be used as an ultra-large memory of the host, which can reduce memory costs. In the present invention, the reading and writing process of data in the non-volatile memory must go through the dynamic random access memory, and the host cannot directly access the non-volatile memory. The predetermined conditions can be related to data access frequency, task priority, data access timestamp, current business data load, etc., and can also be determined by a certain algorithm. In this way, the read and write rate is guaranteed on the one hand, and the storage space can be reasonably arranged on the other hand.

[0008] According to one aspect of the present disclosure, optionally, when reading data from the dynamic random access memory, the controller of the non-volatile memory returns the address of the non-volatile memory to the cache manager according to the index table and the received physical address.

[0009] According to one aspect of the present disclosure, optionally, the cache manager includes a CXL interface, a cache exchange module, a data tiering module, a data transmission module and a backend management layer, wherein the CXL interface communicates with the CXL subsystem; the cache exchange module calculates a first access value of data in the dynamic random access memory according to a first preset algorithm when the cache is full, and determines data whose first access value is lower than a first threshold; the data tiering module calculates a second access value of data in the dynamic random access memory according to a second preset algorithm, and pre-writes the data whose second access value is lower than a second threshold into the non-volatile memory as cold data; the data transmission module manages the dynamic random access memory by segments, and further divides each segment after the division according to the number of non-volatile memories, so that the data size of each sub-segment is an integer multiple of the block size of the non-volatile memory, and is transmitted in parallel between the dynamic random access memory and each non-volatile memory in units of segments; the backend management layer communicates with a controller of the dynamic random access memory and a controller of the non-volatile memory.

[0010] According to one aspect of the present disclosure, optionally, the data transmission module adds a data storage tag to the data, and the tag is determined based on data reading and writing frequency, task priority, data access timestamp, and current business data load.

[0011] According to one aspect of the present disclosure, optionally, the cache manager can be configured to query the cache address according to the cache table and the device physical address, and if the cache hits, the queried cache address is returned to the CXL subsystem, and if the cache misses, when the cache is full, the cache data to be replaced is selected and stored in the non-volatile memory; if the cache misses, when the cache is not full, a new cache address is allocated for the device physical address. When the cache misses and the cache is not full, when the host sends a read instruction, the data in the non-volatile memory corresponding to the device physical address can be loaded into the new cache address of the dynamic random access memory.

[0012] According to the first aspect of the present disclosure, optionally, when the CXL subsystem receives a read instruction from the host, the cache manager is configured to query the cache address according to the cache table and the device physical address. If the cache misses and the dynamic random access memory is full, the cache manager sends a write request to the controller of the non-volatile memory, writes the data in the dynamic random access memory with an access amount lower than a first threshold into the non-volatile memory, allocates a new cache address, and sends a read request to the controller of the non-volatile memory to read data from the non-volatile memory according to the device physical address and write the read data into the new cache address of the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem; if the cache misses and the dynamic random access memory is not full, the cache manager allocates a new cache address, sends a read request to the controller of the non-volatile memory, reads data from the non-volatile memory according to the device physical address and writes the read data into the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem.

[0013] Determining the data whose access volume is lower than a first threshold may include calculating the data access volume according to an elimination algorithm, and treating the data whose access volume is lower than a certain threshold as data with low access volume.

[0014] According to the first aspect of the present disclosure, optionally, when the CXL subsystem receives a write instruction from the host, the cache manager is configured to query the cache address according to the cache table and the device physical address, and if the cache misses and the dynamic random access memory is full, send a write request to the controller of the non-volatile memory, write the data in the dynamic random access memory with an access volume lower than a first threshold into the non-volatile memory, allocate a new cache address, and return the new cache address to the CXL subsystem; if the cache misses and the dynamic random access memory is not full, the cache manager allocates a new cache address and returns the new cache address to the CXL subsystem.

[0015] According to the first aspect of the present disclosure, optionally, the compute fast link subsystem supports CXL.io and CXL.memory protocols.

[0016] According to the first aspect of the present disclosure, optionally, the first preset algorithm and the second preset algorithm are LRU algorithms. According to the first aspect of the present disclosure, optionally, the dynamic random access memory is DDR, and the non-volatile memory is NVMeSSD.

[0017] The second aspect of the present disclosure provides a control method for the aforementioned memory device, wherein the CXL subsystem receives a read or write instruction from the host and requests a cache address from the cache manager; the cache manager queries the cache address corresponding to the device physical address in the cache table according to the device physical address in the read or write instruction, and if the cache hits, returns the queried cache address to the CXL subsystem, and if the cache misses and the dynamic random access memory is full, selects the cache data to be replaced and stores it in the non-volatile memory, and if the cache misses and the dynamic random access memory is not full, allocates a new cache address to the device physical address. For a more specific method of the read and write process of the method, refer to the above description of the read and write process of the memory device controller.

[0018] The present disclosure is based on the existing server architecture to achieve memory expansion, reduce the cost of memory use, and have no impact on application performance. The storage device of the present disclosure can be used in existing cloud platforms and large-scale computer rooms. Since the controller in the CXL device of the present disclosure can be highly integrated, only simple transformation and upgrading are required.

[0019] It is not necessary to achieve all the advantages described above at the same time for any device or method to implement the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be realized and obtained by the structures indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 It is a schematic diagram of the device structure of the host accessing each memory in the prior art;

[0022] Figure 2 is a structural diagram of a memory device based on a computing fast link protocol according to an embodiment of the present disclosure;

[0023] Figure 3 is a schematic diagram of data flow between a host and various parts of a CXL controller according to an embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of the architecture of a cache manager according to an embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram of a data read processing flow according to an embodiment of the present disclosure;

[0026] Figure 6 is a schematic diagram of a data writing process according to an embodiment of the present disclosure;

[0027] Figure 7 is a schematic diagram of a storage structure of DDR data according to an embodiment of the present disclosure;

[0028] Figure 8 is based on Figure 7 The data storage structure of DDR shown in the figure, and the corresponding relationship diagram of SSD receiving data from DDR;

[0029] Fig. 9 FIG. 4 is a schematic diagram of a data management method in an SSD according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not necessarily indicate a quantity restriction. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] Figure 1It is a memory expansion solution of the prior art, in which the host includes a central processing unit (CPU) and a DDR controller connected to the CPU, an NVMe (Non-Volatile Memory Express) controller and a CXL root port. The DDR controller manages the DDR of the host and provides an interface for the CPU to access the DDR memory. The NVMe controller manages the NVMe SSD (Non-Volatile Memory Express Solid State Drive) connected to the NVMe bus. The CXL root port can be connected to the CXL DDR expander using the PCIe (Peripheral Component Interconnect Express) physical layer, and the CXL DDR expander can connect to multiple DDR memories. In the prior art, the host reads / writes the DDR, NVMe SSD and CXL DDR expander separately, and the latency of each part is different, the utilization efficiency is low, and the cost of expansion is high.

[0033] Figure 2 This is a schematic diagram of the structure of a memory device based on the computing fast link protocol according to an embodiment of the present disclosure. The architecture is based on the CXL protocol, uses DDR as a cache, and uses multiple NVMe SSDs as an extended storage space, which can realize dynamic expansion of memory capacity and can provide up to 64TB or even a large memory with a larger capacity. The embodiments of the present disclosure use DDR and NVMe SSD as examples of dynamic random access memory and non-volatile memory, respectively, for illustration, and other suitable dynamic random access memory and non-volatile memory can also be used for the CXL device of the present disclosure. The dynamic random access memory may include, but is not limited to, various versions of DDR, LPDDR (Low Power Double Data Rate), GDDR (Graphics DDR), etc. In addition to NVMe SSD, the non-volatile memory may also include, but is not limited to, 3D XPoint (three-dimensional X-point technology), ReRAM (Resistive RAM), PCM (Phase-Change Memory), etc. In addition, the dynamic random access memory may also be a remote memory, and the non-volatile memory may be implemented using a cloud disk. The controller of the dynamic random access memory and the controller of the non-volatile memory will also correspond to the dynamic random access memory and non-volatile memory they use respectively. The functions implemented by the controller of the dynamic random access memory and the controller of the non-volatile memory can be found in the description of the DDR controller and the NVMe SSD controller in the embodiments of the present disclosure.

[0034] In this architecture, CXL device 2 (CXL dev) can be connected to CPU 11 in host 1 through PCIe physical layer (based on CXL bus) as CXL memory. Host 1 only needs to send request to CXL device 2 to read or write corresponding data from or to CXL device 2. CXL device 2 is equivalent to a large memory for host 1. The management of this large memory does not need to be completed by host 1. Host 1 does not need to Figure 1 As in the prior art shown in the figure, multiple controllers are added to connect with different storage devices, and there is no need to manage these storage devices separately.

[0035] The CXL device 2 includes a CXL controller 20, a plurality of DDR memories 21 connected to the CXL controller 20, and a plurality of NVMe SSDs 22. The CXL controller 20 includes a CXL subsystem 201, a cache manager 202, a DDR controller 203 connected to the cache manager 202, and an NVMe controller (for example, may include an NVMe Root Complex) 204. The CXL controller 20 is designed to support access to NVMe SSDs. To the host, the NVMe SSD is part of the memory of the CXL device 2. The DDR controller 203 may be connected to a plurality of DDR memories 21, and the NVMe controller 204 may be connected to a plurality of NVMe SSDs 22. The CXL controller may be set on a chip, and access to the DDR memory and the NVMe SSD through corresponding interfaces, without the need for the host 1 to directly manage these storage spaces, while facilitating the expansion of storage spaces.

[0036] Figure 3 FIG. 1 is a schematic diagram of the data flow of the interaction between the host and various parts of the CXL controller according to an embodiment of the present disclosure. Figure 2 The structure diagram shown in the figure explains in detail the functions of each part of the CXL controller.

[0037] The CXL subsystem 201 supports at least the CXL.io protocol and the CXL.memory protocol, and can be used to process CXL protocol commands. The CXL subsystem 201 can use the CXL.memory protocol to enable the host to access the memory of the CXL device 2. The host 1 sends a read / write request to the CXL subsystem 201 and receives a read / write result from it. The CXL subsystem implements the function of an interface for interacting with the host. The CXL subsystem 201 can call the cache manager 202 to find the DDR address of the DPA (Device Physical Address) in the read / write request of the corresponding host, and perform read / write access after obtaining the DDR address.

[0038] The cache manager 202 is used to uniformly manage the data reading / writing of the storage devices (including DDR memory and NVMe SSD) in the CXL device. It saves the mapping relationship between the DPA and the DDR address in the cache table and can update the cache table. The cache manager 202 also manages the relationship between the DPA address and the file path or address in the SSD, and can update it as needed. Here, the host reads / writes data through the DPA address instead of directly accessing the DDR or SSD. The cache manager 202 can move and exchange data between the DDR and the SSD. The cache manager 202 also supports the exchange of cold data and hot data between the DDR and the NVMe SSD and pre-writes the data on the DDR back to the NVMe SSD. Generally speaking, cold data refers to infrequently accessed data, which can be stored on relatively slow storage media; hot data refers to frequently accessed data, which requires fast access to ensure system performance.

[0039] The DDR controller 203 is used to process the read / write commands of the memory, and the DDR controller can be connected to the DDR by a DIMM interface. The NVMe controller 204 may include an NVMe root complex, which manages the read / write of the NVMe SSD. Optionally, the DDR controller and the NVMe controller can be configured by hardware and software to realize direct data transmission between them, or data can be exchanged via a cache manager.

[0040] Figure 4 A schematic diagram of the architecture of a cache manager according to an embodiment of the present disclosure is shown. The cache manager 202 may include at least a CXL interface 2021, a data tiering module 2022, a cache exchange module 2023, a data transmission module 2024, and a backend management layer 2025. The CXL interface 2021 is responsible for communicating with the CXL subsystem, receiving service requests from the upper layer, and returning required information or data such as DDR addresses; the cache exchange module 2023 is used to manage the data in the DDR based on a certain elimination algorithm when the cache is full, and can move the data in the DDR with an access frequency lower than the first preset threshold to the NVMe SSD. The data tiering module 2022 can perform tiering of cold data and hot data, and based on a certain elimination algorithm, such as the LRU (Least Recently Used) algorithm, the LFU (Least Frequently Used) algorithm, etc., the cold data lower than the second preset threshold is pre-written to the NVMe SSD, so as to prevent the overall delay caused by writing back the DDR when the cache is full, and reduce the waiting time for writing. The data transmission module 2024 manages the data transmission between DDR and SSD to improve the data transmission efficiency. The specific management method will refer to Figure 7 and Figure 8Description. The backend management layer 2025 can be used to connect with the DDR controller and the NVMe controller to read data from the DDR or NVMe SSD or write data to these storage devices. The cache switching module and the data tiering module can use the same or different elimination algorithms.

[0041] Figure 5 The schematic diagram of the read data processing flow according to an embodiment of the present disclosure is shown. The host 1 regards the CXL device 2 as a memory device and sends a read instruction to the CXL device 2 in step 501. More specifically, the read instruction to the memory of the CXL device may include a DPA address, and a read request is initiated to a certain DPA address through the instruction. In step 503, the CXL subsystem 201 calls the cache manager 202 to find the cache address to be read. The cache manager 202 searches the cache table according to the DPA address to determine whether the cache hits (i.e., whether the cache address is found). If the cache hits, the cache address is returned to the CXL subsystem 201 in step 505. At this time, the CXL subsystem can execute steps 533, 535, and 537. In step 533, the CXL subsystem initiates a read request to the DDR. In step 535, the DDR controller responds to the CXL subsystem. In step 537, the CXL subsystem returns the read response of the CXL memory to the host.

[0042] When the CXL subsystem receives the read instruction, the cache manager searches the cache table for judgment. If the cache misses and the cache is not full, the cache manager allocates new cache space (cache address) to correspond to the DPA (step 507). A cache miss means that the cache address corresponding to the DPA is not found in the cache table. The cache manager 202 sends a read request to the NVMe controller according to the DPA address in the instruction (step 509). The data of the corresponding address or file path in the NVMe SSD is sent to the DDR controller and stored in the newly allocated DDR (step 511), and then sends an NVMe SSD read response to the cache manager (step 513). In step 515, the cache manager returns the DDR address to the CXL subsystem. Continue to execute steps 533, 535, and 537.

[0043] In the case of a cache miss, in order to read / write data to the NVMe SSD, the cache manager 202 will search the file path or address of the NVMe SSD according to the DPA address. In addition, in the case of a cache miss, the cache manager will update the cache table according to the allocated DDR address.

[0044] After the CXL subsystem receives the read request, the cache manager searches the cache table for judgment. If the cache misses and the cache is full, the cache manager 202 selects the cache data to be replaced. A certain algorithm can be used to select data below a threshold as the cache data to be replaced, such as the LRU algorithm. In step 517, an NVMe write request is issued to the NVMe controller, requesting that the cache data to be replaced be written to the NVMe SSD. In step 519, the cache manager 202 initiates a task to write the data to be replaced in the DDR to the NVMe SSD. Specifically, in this step, the cache manager 202 obtains the cache data to be replaced through the DDR controller and writes the data to the NVMe SSD through the NVMe controller. If the DDR controller and the NVMe controller can support direct data transmission, the DDR controller can also send the DDR data to the NVMe controller and store it in the NVMe SSD. In step 521, after the data is written, the NVMe controller sends the NVMe SSD write response to the cache manager 202 to notify it of the completion of the write. In step 523, the cache manager 202 allocates a new DDR address. In step 525, a request to read data is sent to the NVMe controller, wherein the corresponding address or file path of the NVMe SSD is determined according to the DPA address. In step 527, the data of the NVMe SSD is written to the newly allocated address of the corresponding DDR through the DDR controller. In step 529, after the data reading is completed, the NVMe controller sends a read response to the cache manager 202. In step 531, the cache manager returns the DDR address where the NVMe SSD data is written to the CXL subsystem. Continue to execute steps 533, 535, and 537.

[0045] Figure 6 A schematic diagram of a write data processing flow according to an embodiment of the present disclosure is shown. In step 601, host 1 sends a write instruction to CXL device 2. Steps 603-605 are similar to steps 503-505. In step 603, the CXL subsystem calls the cache manager to find the cache address corresponding to the DPA address. In step 605, in the case of a cache hit, the cache address is returned, and steps 621, 623, and 625 are continued. In step 621, the CXL subsystem initiates a write request to the DDR. In step 623, the DDR controller responds to the CXL subsystem. In step 625, the CXL subsystem returns the write response of the CXL memory to the host.

[0046] In step 603 , when the CXL subsystem receives a write instruction, if the cache misses and the cache is not full, the cache manager allocates new cache space (cache address) to correspond to the DPA (step 607 ), and returns the cache address to the CXL subsystem (step 609 ), and continues to execute steps 621 , 623 , and 625 .

[0047] In step 603, when the CXL subsystem receives the write instruction, if the cache misses and the cache is full, steps 611-617 are executed, which are similar to steps 517-523. In step 611, an NVMe write request is issued to the NVMe controller, requesting that the cache data to be replaced in the DDR be written to the NVMe SSD. In step 613, the cache manager 202 initiates a task to write the data to be replaced in the DDR to the NVMe SSD. In step 615, after the data is written, the NVMe controller sends an NVMe SSD write response to the cache manager 202 to notify it of the completion of the write. In step 617, the cache manager 202 allocates a new DDR address. In step 619, the cache manager returns the DDR address to the CXL subsystem, and continues to execute steps 621-625.

[0048] During the read / write process, if the cache hits, the host reads data with a low latency, which is consistent with the latency of the CXL device reading the DDR memory. If the cache does not hit, it is necessary to read / write the NVMe SSD, and the latency will increase. In order to increase the probability of cache hits and reduce the latency of the host reading data, the cache manager can manage the cached data according to the access frequency and pre-store the data on the DDR to the SSD. The selection of stored data can be implemented by an elimination algorithm, such as the LRU algorithm or the SLRU (Segmented LRU) algorithm. Specifically, the access value of DDR data can be calculated according to the algorithm, and if it is lower than the threshold, the corresponding data can be stored in the SSD.

[0049] Optionally, in order to reduce the increase in overall latency caused by DDR cache writes, thresholds related to indicators such as access frequency can be set. If the access frequency of data on DDR (for example, marked as cold data blocks) is lower than the threshold, the cache manager pre-writes the data in this part of the DDR cache back to the NVMe SSD. In this way, when there is a new DDR cache read / write request later, such DDR blocks can be directly replaced, reducing the time waiting to write to the NVMe SSD. Automatically writing (or writing back) data from DDR to SSD reduces the latency during the read / write process.

[0050] The data transfer module of the cache manager can add a data storage tag to the data. The tag can be determined based on the data read and write frequency, task priority, data access timestamp, current business data load, or based on a certain algorithm (such as the above-mentioned hot and cold data tiering algorithm), or more factors can be considered. The tag can be used to determine whether to move the data from the DDR to the SSD, or whether to keep the data in the DDR.

[0051] Optionally, in order to reduce the latency of data reading / writing, the DDR cache can be managed in larger data units. Specifically, the host's memory is usually managed in pages, and a page is 4KB, 16KB, etc. Since the memory of a process is highly correlated, larger blocks can be used to manage the DDR cache in the present disclosure, and the size of each block can be configured, for example, it can be configured to 64KB, 128KB, etc. as needed, and the block size is a multiple of the memory page size. When reading / writing NVMe SSD, DDR can be operated in blocks. For example, when DDR exchanges data with SSD, data can be transferred in blocks. This method can improve read / write efficiency.

[0052] like Figure 7 and 8 As shown, the space of DDR is divided into 0-m, a total of m+1 data segments, each data segment is divided into 0-n, a total of n+1 sub-segments, where n+1 corresponds to the number of SSDs, and the size of each sub-segment is an integer multiple of the block of the SSD (the integer multiple is 1, 2, 3...). The size of each sub-segment can be adaptively adjusted in length according to parameters such as the capacity and performance of the SSD, so that the load of each SSD in the back end is more balanced, and each sub-segment can be, for example, 4KB, 8KB. When certain data is transferred from DDR to SSD, the sub-segments of each data segment, such as sub-segments 0-0, 0-1, 0-2, 0-3...0-n, are written from DDR to n+1 SSDs in parallel. Similarly, when certain data is transferred from SSD to DDR, n+1 sub-segments can be read from n+1 SSDs in parallel to DDR. The data in the SSD can be set to include metadata mapping from DDR to SSD, storing the mapping relationship between DDR and SSD storage areas. Therefore, DDR data is managed according to data segments. A data segment is sent at the same time each time it is read or written. The data segment contains multiple address data. If an address data needs to be read, the data segment corresponding to the address will be read together. The way of transmitting data between DDR and SSD can improve the efficiency of data reading and writing, and also improve the hit rate of DDR. At the same time, by making the load of SSD more balanced and realizing block reading and writing, the SSD write amplification effect is reduced and the service life of SSD is extended.

[0053] Fig. 9It is a schematic diagram of the data management method within the SSD according to an embodiment of the present disclosure. The storage space in the SSD is divided into an additional write layer 901 and a random write layer 902. The additional write layer 901 is read and written through the data index table 903. Specifically, when the SSD receives data, the data is directly appended to the end of the existing data in the additional write layer 901, and the data index table is updated to complete the writing. When the data in the additional write layer 901 reaches a threshold, the previously written data is merged and recycled, and written to the random write layer 902. The random write layer 902 is managed by a file system. When writing data from the additional write layer 901 to the random write layer 902, it can also be decided whether to choose to write to the random write layer or keep it in the additional write layer based on the data storage label or similar conditions.

[0054] When reading data from the SSD, first search for the data through the data index table 903. If the data is found, it means that the data is in the additional write layer, and it can be read and the result is returned. If the data index table does not find the data, the data is in the random write layer. According to the file manager, the data is found from the random write layer and the result is returned to the cache manager. Since the data location in the SSD is dynamically adjusted, the physical address corresponding to the data to be stored in the SSD and the corresponding storage address at present are in correspondence. The above-mentioned storage space allocation method in the SSD improves the data reading and writing speed on the one hand, and can make more reasonable use of the SSD space on the other hand.

[0055] The above-mentioned embodiments of the present disclosure can be suitable for forming an integrated local device without changing the hardware of the host, that is, the dynamic random access memory and the non-volatile storage device are both set locally, and the CXL device can be made into a board to achieve ultra-large memory expansion, which is particularly suitable for high-speed data centers. When the virtual machine applies for memory, the memory can be allocated more efficiently without having to store all data in DDR, thereby avoiding the waste of storage resources.

[0056] The CXL memory device and memory expansion method disclosed in the present invention use dynamic random access memory (such as DDR) as cache and non-volatile memory (such as NVMe SSD) as expansion space to achieve dynamic expansion of memory capacity. The cache management module can dynamically manage data, exchange hot and cold data between dynamic random access memory and non-volatile memory, and improve data exchange efficiency through a series of algorithms, so that the access performance of the storage device to the host is as close as possible to that of the memory device. The device provides a CXL interface to the outside and supports CXL.memory access.

[0057] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A memory device based on a computing fast link protocol, characterized in that include a plurality of dynamic random access memories and a plurality of non-volatile memories; and A controller for a memory device based on a compute fast link protocol, the controller comprising: The CXL subsystem includes an interface for communicating with a host, and is configured to receive a read or write instruction including a physical address of a device from the host; a cache manager storing a cache table recording a mapping relationship between a device physical address and a cache address, configured to return a cache address to the CXL subsystem according to the device physical address received from the CXL subsystem, and to segment a storage space of the dynamic random access memory according to the number and block size of the non-volatile memory, so that data is transmitted in parallel between the dynamic random access memory and the non-volatile memory in units of segments; a controller of the dynamic random access memory, connected to the cache manager, configured to receive a read or write request from the cache manager, and perform a read or write operation on the dynamic random access memory according to the cache address; a controller of a non-volatile memory connected to the cache manager and configured to receive a read or write request from the cache manager, and to perform a read or write operation on the non-volatile memory according to the device physical address to write data from the dynamic random access memory to the non-volatile memory, or to read data from the non-volatile memory to store in the dynamic random access memory; Each non-volatile memory includes an additional write layer and a random write layer. When new data is received, the new data is written to the end of the additional write layer. The additional write layer is read through a data index table, and the random write layer is managed by a file system. When the data in the additional write layer reaches a threshold, part or all of the data in the additional write layer is merged and written into the random write layer. The dynamic mapping relationship between the physical address and the data address of the non-volatile memory is stored in the index table of the non-volatile memory and updated each time data is written.

2. The memory device based on the computing fast link protocol according to claim 1, characterized in that When reading data from the dynamic random access memory, the controller of the non-volatile memory returns the data address of the non-volatile memory to the cache manager according to the index table and the received physical address.

3. The memory device based on the computing fast link protocol according to claim 1, characterized in that The cache manager includes a CXL interface, a cache exchange module, a data tiering module, a data transmission module, and a backend management layer, wherein the CXL interface communicates with the CXL subsystem; the cache exchange module calculates a first access value of data in the dynamic random access memory according to a first preset algorithm when the cache is full, and determines data whose first access value is lower than a first threshold; The data stratification module calculates a second access value of the data in the dynamic random access memory according to a second preset algorithm, and pre-writes the data whose second access value is lower than a second threshold into the non-volatile memory as cold data; The data transmission module manages the dynamic random access memory in segments, and divides each segment again according to the number of non-volatile memories, so that the data size of each sub-segment is an integer multiple of the block size of the non-volatile memory, and the data is transmitted in parallel between the dynamic random access memory and each non-volatile memory in segments; the back-end management layer communicates with the controller of the dynamic random access memory and the controller of the non-volatile memory.

4. The memory device based on the computing fast link protocol according to claim 3, characterized in that The data transmission module adds a data storage tag to the data, and the tag is determined based on the data reading and writing frequency, task priority, data access timestamp, and current business data load.

5. The memory device based on the computing fast link protocol according to claim 1, characterized in that The cache manager is configured to query the cache address according to the cache table and the device physical address, and if the cache hits, return the queried cache address to the CXL subsystem; If the cache misses, when the cache is full, the cache data to be replaced is selected and stored in the non-volatile memory; If the cache misses, a new cache address is allocated for the device physical address if the cache is not full.

6. The memory device based on the computing fast link protocol according to claim 1, characterized in that When the CXL subsystem receives a read instruction from the host, the cache manager is configured to query the cache address according to the cache table and the device physical address. If the cache does not hit and the dynamic random access memory is full, the cache manager sends a write request to the controller of the non-volatile memory, writes data in the dynamic random access memory whose access amount is lower than a first threshold calculated according to a first preset algorithm into the non-volatile memory, allocates a new cache address, and sends a read request to the controller of the non-volatile memory to read data from the non-volatile memory according to the device physical address and write the read data into the new cache address of the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem; if the cache does not hit and the dynamic random access memory is not full, the cache manager allocates a new cache address, sends a read request to the controller of the non-volatile memory, reads data from the non-volatile memory according to the device physical address and writes the read data into the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem.

7. The memory device based on the computing fast link protocol according to claim 1, characterized in that When the CXL subsystem receives a write instruction from the host, if the cache misses and the dynamic random access memory is full, a write request is sent to a controller of the non-volatile memory, data in the dynamic random access memory whose access amount is lower than a first threshold calculated according to a first preset algorithm is written into the non-volatile memory, a new cache address is allocated, and the new cache address is returned to the CXL subsystem; if the cache misses and the dynamic random access memory is not full, the cache manager allocates a new cache address and returns the new cache address to the CXL subsystem.

8. The memory device based on the computing fast link protocol according to claim 1, characterized in that The dynamic random access memory is DDR memory, and the non-volatile memory is NVMe SSD.

9. The memory device based on the computing fast link protocol according to claim 1, characterized in that The memory device controller is implemented using an integrated circuit.

10. A control method for a memory device based on a computing fast link protocol as claimed in any one of claims 1 to 4, characterized in that include: The CXL subsystem receives a read or write instruction from the host and requests a cache address from the cache manager; The cache manager queries the cache table for the corresponding cache address based on the device physical address in the read or write instruction. If the cache hits, the cache manager returns the queried cache address to the CXL subsystem. If the cache misses and the dynamic random access memory is full, the cache data to be replaced is selected and stored in the non-volatile memory. If the cache misses and the dynamic random access memory is not full, a new cache address is allocated for the device physical address.

11. The control method of a memory device based on a computing fast link protocol as claimed in claim 10, characterized in that include: When the CXL subsystem receives a read instruction from the host, if the cache misses and the dynamic random access memory is full, the cache manager sends a write request to the controller of the non-volatile memory, writes data in the dynamic random access memory whose access amount is lower than a first threshold calculated according to a first preset algorithm into the non-volatile memory, allocates a new cache address, and sends a read request to the controller of the non-volatile memory to read data from the non-volatile memory according to the device physical address and write the read data into a new cache address of the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem; If the cache misses and the dynamic random access memory is not full, the cache manager allocates a new cache address, sends a read request to the controller of the non-volatile memory, reads data from the non-volatile memory according to the device physical address and writes the read data to the dynamic random access memory, and the cache manager returns the new cache address to the CXL subsystem.

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