Operational circuit, chip, and electronic device

Abstract

The invention discloses an operational circuit, a chip and electronic equipment, and the operational circuit comprises a storage unit which is connected with a bus and is used for storing data; the DMA unit is connected with the bus and is used for storing the data into the storage unit or reading the data from the storage unit; and the operation unit is connected with the bus, and the operation unit is used for operation and controlling the DMA unit or the operation unit to store operation data into the storage unit or read the operation data from the storage unit according to the working state of the storage unit. According to the operation circuit, related data in the operation process are stored through the storage unit, application of registers in the operation unit is greatly reduced, the area and application cost of an operation unit hardware implementation circuit are reduced, and meanwhile in the operation process, the operation efficiency is improved. The operation unit can select the data transmission path for storing the operation data to the storage unit or reading the operation data from the storage unit according to the working state of the storage unit, so that the stable operation process is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to an operation circuit, a chip and an electronic equipment. Background Art

[0002] In the related art, the algorithm module usually uses a group of 32-bit triggers as registers for various data, so as to store the data required for algorithm execution. Taking the SHA256 algorithm module as an example, the SHA256 algorithm module uses registers to store 8 groups of 32-bit hash value initial values ​​(a0~h0), 16 groups of 32-bit input messages (M), algorithm message time coefficient Wt, 64 constant numbers K, 8 groups of 32-bit working variables (a~h), and some intermediate variables. These registers will occupy a large amount of chip area and increase chip cost. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to provide an operation circuit, which stores relevant data in the operation process through a storage unit, greatly reducing the application of registers in the operation unit, reducing the area and application cost of the hardware implementation circuit of the operation unit, and at the same time, during the operation process, the operation unit can select the data transmission path for storing the operation data to the storage unit or reading from the storage unit according to the working state of the storage unit, thereby ensuring the stable operation of the operation process.

[0004] The second objective of the present invention is to provide a chip.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] To achieve the above-mentioned purpose, the first aspect of the present invention proposes an operation circuit, comprising: a storage unit, which is connected to a bus and is used to store data; a DMA (Direct Memory Access) unit, which is connected to the bus and is used to store data in the storage unit or read data from the storage unit; and an operation unit, which is connected to the bus and is used for operation, and according to the working state of the storage unit, controls the DMA unit or itself to store the operation data in the storage unit or read from the storage unit.

[0007] According to the operation circuit of the embodiment of the present invention, the storage unit is connected to the bus, the storage unit is used to store data, the DMA unit is connected to the bus, the DMA unit is used to store data in the storage unit or read from the storage unit, the operation unit is connected to the bus, the operation unit is used for operation, and according to the working state of the storage unit, the DMA unit is controlled or itself stores the operation data in the storage unit or reads from the storage unit. Therefore, the operation circuit stores the relevant data in the operation process through the storage unit, which greatly reduces the application of registers in the operation unit, reduces the area and application cost of the hardware implementation circuit of the operation unit, and at the same time, during the operation process, the operation unit can select the data transmission path for storing the operation data in the storage unit or reading from the storage unit according to the working state of the storage unit, thereby ensuring the stable operation of the operation process.

[0008] In addition, the arithmetic circuit according to the above embodiment of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, the operation unit is used to control itself to store the operation data into the storage unit or read from the storage unit when the working state is an idle state; when the working state is a busy state, control the DMA unit to start working to store the operation data into the storage unit or read from the storage unit.

[0010] According to one embodiment of the present invention, the operation unit includes a mutation transmission subunit, which is connected to the storage unit through a data line. The operation unit is used to control the mutation transmission subunit to start working to store the operation data to the storage unit or read it from the storage unit.

[0011] According to one embodiment of the present invention, the operation circuit also includes a bus arbiter, which is arranged between the DMA unit and the bus. The bus arbiter is used to obtain the bus status of the bus, and the DMA unit is used to store the operation data in the storage unit or read it from the storage unit according to the bus status.

[0012] According to one embodiment of the present invention, the operation circuit also includes an identification unit, which is connected to the bus. The identification unit is used to obtain the working status of the storage unit and generate a corresponding signal to send to the operation unit. The operation unit is also used to determine the working status of the storage unit based on the signal.

[0013] According to an embodiment of the present invention, the identification unit is used to record the number of times the storage unit is accessed by the processor within a preset time, and determine the working state of the storage unit according to the number of times.

[0014] According to an embodiment of the present invention, the identification unit is disposed in a bus arbiter or a processor.

[0015] According to one embodiment of the present invention, the operation includes a SHA256 operation, the operation data includes a hash value and a message, the message includes multiple message blocks, each message block includes multiple sub-message blocks, wherein the operation unit is used to perform an iterative operation on each message block, and perform multiple loop operations during the iterative operation process, and in each loop operation process, read the corresponding sub-message block from the storage unit for operation to obtain the calculated sub-message block, and store the calculated sub-message block in the storage unit; read the hash value obtained in the previous loop operation from the storage unit, and update the hash value obtained in the previous loop operation according to the calculated sub-message block to obtain the hash value of this loop operation, and store the hash value of this loop operation in the storage unit.

[0016] According to one embodiment of the present invention, the storage unit includes a first storage space, a second storage space and a third storage space, wherein the operation unit is further used to, during each iterative operation, store the hash value obtained by the last loop operation in the first storage space, so as to use it as the initial value of the hash value of the first loop operation during the iterative operation of the next message block; store the calculated sub-message blocks obtained by each loop operation in the second storage space; and store the hash value obtained by each loop operation in the third storage space.

[0017] According to one embodiment of the present invention, the second storage space includes multiple sub-storage spaces, each sub-storage space is used to store a message block, each sub-storage space includes multiple sub-storage space blocks, each sub-storage space block is used to store a sub-message block, wherein the operation unit is also used to store the sub-message blocks after operation in a first-store-first-overwrite manner when the total number of loop operations in each iterative operation process is greater than the number of sub-storage space blocks.

[0018] To achieve the above object, a second embodiment of the present invention provides a chip including the above-mentioned operation circuit.

[0019] According to the chip of the embodiment of the present invention, based on the above-mentioned operation circuit, the relevant data in the operation process is stored through the storage unit, which greatly reduces the application of registers in the operation unit, reduces the area and application cost of the hardware implementation circuit of the operation unit, and at the same time, during the operation process, the operation unit can select the data transmission path for storing the operation data to the storage unit or reading from the storage unit according to the working state of the storage unit, thereby ensuring the stable operation of the operation process.

[0020] To achieve the above object, a third aspect of the present invention provides an electronic device, including the above chip.

[0021] The electronic device according to the embodiment of the present invention, based on the above chip, ensures stable implementation of the functions of the electronic device.

[0022] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a connection diagram of a computing circuit according to an embodiment of the present invention;

[0024] Figure 2 is a connection diagram of a computing circuit according to an embodiment of the present invention;

[0025] Figure 3 is a block diagram of a chip according to an embodiment of the present invention;

[0026] Figure 4 FIG. 4 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0028] The computing circuit, chip and electronic device proposed in the embodiments of the present invention are described below with reference to the accompanying drawings.

[0029] Figure 1 FIG. 4 is a connection diagram of a computing circuit according to an embodiment of the present invention.

[0030] like Figure 1 As shown, the operation circuit according to the embodiment of the present invention may include: a storage unit 10 , a DMA unit 20 and an operation unit 30 .

[0031] The storage unit 10 is connected to the bus and is used to store data. The DMA unit 20 is connected to the bus and is used to store data in the storage unit 10 or read data from the storage unit 10. The operation unit 30 is connected to the bus and is used to perform operations, and according to the working state of the storage unit 10, the operation unit 30 controls the DMA unit 20 or itself to store the operation data in the storage unit 10 or read the operation data from the storage unit 10.

[0032] The operation circuit can be arranged in a chip, and the storage unit 10 can directly use the SRAM (Static Random Access Memory) in the chip. When the SRAM in the chip is used, the storage address can be divided in advance to store the operation data through the pre-divided storage address. The operation data stored in the storage unit 10 may include the initial data used for the operation, the intermediate data generated during the operation, and the result output after the operation is completed, etc., which are not limited here. The DMA unit 20 is used to perform the DMA transmission function. After the DMA unit 20 is started, the bus control right is obtained, and the controller of the DMA unit 20 outputs the read and write commands to directly control the storage unit 10 and the I / O interface to perform DMA transmission. Therefore, when the DMA unit 20 performs data transmission, the chip's CPU (Central Processing Unit) does not need to participate in the reading and writing of the storage unit 10, thereby avoiding the influence of the data transfer process on the efficiency of the chip CPU. The operation unit 30 can be set based on the operation algorithm to be implemented, such as an operation unit that can implement a hash security algorithm, an operation unit that can implement an integer prime factor decomposition algorithm, etc. At the same time, a read-write functional unit that can directly interact with the storage unit 10 is set in the operation unit 30, and the operation unit 30 controls the read-write functional unit to send read-write instructions to the storage unit 10 to complete the read and write operations of data between the storage unit 10 and the operation unit 30. The read-write functional unit can be directly connected to the storage unit 10 through a data line or a separately provided bus to establish a data transmission channel between the storage unit 10 and the operation unit 30.

[0033] Specifically, before the operation starts, the initial data used in the operation is first written into the storage unit 10 through the CPU of the chip. After determining that the initial data is written, the CPU controls the operation unit 30 to start, and then executes the corresponding operation algorithm. During the operation of the operation unit 30, the DMA unit 20 or its own read and write functional unit is started according to the working state of the storage unit 10 to cooperate with the operation algorithm to complete the transfer of the operation data between the operation unit 30 and the storage unit 10, so as to ensure the stable operation of the operation process, and at the same time reduce the demand for the storage space of the operation unit 30, so as to reduce the layout area of ​​the storage device of the operation unit 30 and reduce the application cost of the operation unit 30.

[0034] When the operation unit 30 determines to perform data transfer work through the DMA unit 20 according to the working state of the storage unit 10, the operation unit 30 controls the DMA unit 20 to start, and the DMA unit 20 reads the operation data from the storage unit 10 and sends it to the operation unit 30 through the bus according to the corresponding instruction received, or transfers it from the operation unit 30 to the storage unit 10 for storage. In the process of the DMA unit 20 performing data transfer, the CPU of the chip does not need to participate, avoiding the impact on the working efficiency of the CPU. When the operation unit 30 determines to perform data transfer work through its own read-write function unit according to the working state of the storage unit 10, the operation unit 30 controls its own read-write function unit to start, and directly transfers data with the storage unit 10 through the read-write function unit to complete the corresponding operation process. Therefore, the operation data involved in the operation of the operation unit 30 is stored through the storage unit 10, which greatly reduces the demand for storage space of the operation unit 30 and reduces the application cost of the operation unit 30.

[0035] The working state of the storage unit 10 may include: read state, write state, idle state, etc., and then the corresponding data transfer path is selected according to the current state of the storage unit. For example, when the storage unit is in the read or write state, the data transfer between the storage unit 10 and the operation unit 30 can be performed through the DMA unit 20, and when the storage unit is not in the read or write state, the data transfer can be performed between the storage unit 10 and the operation unit 30 through the read and write function unit of the operation unit 30. In addition, the bus type can be selected according to the application requirements, for example, an AHB (Advanced High Performance Bus) bus can be used.

[0036] It should be noted that the working status of the above-mentioned storage unit 10 can be based on the sending of status signals by the bus connecting the storage unit 10 and the operation unit 30. For example, the storage unit 10 can feedback a high level to the operation unit 30 when performing read and write operations, thereby completing the working status feedback. The operation unit 30 determines that the storage unit 10 is in a busy state based on the received high level signal, thereby controlling the DMA unit 20 to start, so as to perform data transfer operations between the storage unit 10 and the operation unit 30 through the DMA unit 20.

[0037] In one embodiment of the present invention, the operation unit 30 is used to control itself to store the operation data into the storage unit 10 or read it from the storage unit 10 when the working state is an idle state; when the working state is a busy state, control the DMA unit 20 to start working to store the operation data into the storage unit 10 or read it from the storage unit 10.

[0038] Specifically, the idle state may be that the storage unit 10 is not currently accessed, that is, the storage unit 10 does not perform a read action or a write action, or that the storage unit 10 is not accessed by other modules within a preset time, for example, not accessed by a chip external device. The busy state may be that the storage unit 10 is currently being accessed, or that the storage unit 10 has been accessed a preset number of times within a preset time, and the judgment condition may be set specifically according to actual conditions.

[0039] When the storage unit 10 is in an idle state, it is considered that the current operation unit 30 can exclusively use the storage unit 10, and the operation unit 30 can transfer data between its own functional unit and the storage unit 10, that is, store the operation data to the storage unit 10 or read it from the storage unit 10. When the storage unit 10 is in a busy state, the operation unit 30 controls the DMA unit 20 to start, and performs data transfer through the DMA unit 20 to ensure the transfer effect of the operation data.

[0040] Reference Figure 2 As shown, in one embodiment of the present invention, the operation unit 30 includes a mutation transmission subunit 31, which is connected to the storage unit 10 through a data line. The operation unit 30 is used to control the mutation transmission subunit 31 to start working to store the operation data to the storage unit 10 or read it from the storage unit 10.

[0041] Specifically, the data line can be a data bus, such as an AHB bus, an AXI bus, etc., which is not limited here, and is used as a data channel between the mutation transmission subunit 31 and the storage unit 10. The mutation transmission subunit 30 is used to implement the Burst transmission function. Burst transmission can be translated as burst transmission or continuous transmission, which refers to the method of continuous data transmission between adjacent storage units in the same row. As long as the starting address and burst length are specified, the controller will automatically perform read / write operations on the same number of subsequent storage units in sequence, without the need for the controller to continuously provide column addresses. In other words, when the storage unit 10 is in an idle state, the operation unit 30 controls the mutation transmission subunit 31 to start, so as to start the Burst function to transfer data between the storage unit 10 and the operation unit 30. The number of continuous transfers can be flexibly configured to speed up the operation speed. After controlling the mutation transmission subunit 31 to start, the controller of the operation unit 30 directly performs read / write operations on the storage unit 10.

[0042] In one embodiment of the present invention, the operation circuit also includes a bus arbiter 40, which is arranged between the DMA unit 20 and the bus. The bus arbiter 40 is used to obtain the bus status of the bus, and the DMA unit 20 is used to store the operation data to the storage unit 10 or read it from the storage unit 10 according to the bus status.

[0043] That is to say, when the storage unit 10 is in a busy state, the operation unit 30 controls the DMA unit 20 to start, and data is transferred between the storage unit 10 and the operation unit 30 through the DMA unit 20 and the bus arbiter 50, which does not affect the normal efficiency of the chip CPU and reduces the chip cost.

[0044] In one embodiment of the present invention, the operation circuit also includes an identification unit 50, which is connected to the bus. The identification unit 50 is used to obtain the working status of the storage unit 10 and generate a corresponding signal to send to the operation unit 30. The operation unit 30 is also used to determine the working status of the storage unit 10 based on the signal.

[0045] That is to say, the working status of the storage unit 10 is monitored by the identification unit 50. For example, the identification unit 50 can read the bus transmission information and determine whether the information corresponds to the storage unit 10 according to the information flag. If so, a high-level signal is sent to the operation unit 30. The operation unit 30 determines that the storage unit 10 is currently in a busy state based on the received high-level signal.

[0046] In one embodiment of the present invention, the identification unit 50 is used to record the number of times the storage unit 10 is accessed by the processor 60 within a preset time, and determine the working state of the storage unit 10 according to the number of times.

[0047] That is, a counter is provided in the identification unit 50 to count the number of times the storage unit 10 is accessed by the memory 60 within a preset time, and when the count reaches a preset value, the counter overflows a high level, and determines that the storage unit 10 is in a busy state. The processor 60 may be an internal processor of the chip.

[0048] In addition, the recognition unit 50 can be Figure 2 It is shown as being arranged separately, but can also be set in the bus arbiter 20 or the processor 60, which is not limited here.

[0049] In one embodiment of the present invention, the operation includes a SHA256 operation, the operation data includes a hash value and a message, the message includes multiple message blocks, each message block includes multiple sub-message blocks, wherein the operation unit 30 is used to perform an iterative operation on each message block, and perform multiple loop operations during the iterative operation process, and in each loop operation process, read the corresponding sub-message block from the storage unit 10 for operation to obtain the calculated sub-message block, and store the calculated sub-message block in the storage unit 10; read the hash value obtained in the previous loop operation from the storage unit 10, and update the hash value obtained in the previous loop operation according to the calculated sub-message block to obtain the hash value of this loop operation, and store the hash value of this loop operation in the storage unit 10.

[0050] Specifically, the operation process of the SHA256 algorithm includes two loops. The variable of the outer loop, i.e., the iterative operation, is the sequence number i of the message block, and the variable of the inner loop, i.e., the cyclic operation, is the time sequence t. The entire operation process needs to go through 64×N times (N is the number of message blocks M). (i) number of) cycles.

[0051] The SHA256 algorithm includes the following steps: calculation of the message time coefficient Wt, initialization of the hash value, iterative calculation of the hash value, update of the hash value, and calculation of the message digest.

[0052] (1) Initialization of hash value

[0053] The SHA256 algorithm uses 8 sets of hash values, and the initial hash value can be recorded as:

[0054]

[0055]

[0056] (2) Calculation of message time coefficient Wt

[0057] The calculation formula of the message time coefficient Wt in the SHA256 algorithm is as follows:

[0058]

[0059] Wherein, 1≤i≤N, i represents the sequence number of the message block, and N is the number of the message blocks.

[0060] (3) Iterative calculation of hash values

[0061] For each message block M (i) , the SHA256 algorithm needs to perform 64 cycles, the loop variable is the time series t, and each cycle will calculate and update 8 hash values.

[0062]

[0063]

[0064] h=g

[0065] g=f

[0066] f=e

[0067] e=d+T 1

[0068] d=c

[0069] c=b

[0070] b=a

[0071] a=T 1 +T 2

[0072] Among them, K t It is the t-th element of a 32-bit constant array with a depth of 64, which can be pre-stored in the operation unit 30.

[0073] In addition, the initial value of the hash value must be updated after every 64 cycles. The update method is as follows:

[0074]

[0075]

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

[0082] (4) Calculation of message digest of SHA256 algorithm

[0083] After N rounds of iterations, a 256-bit message digest M (digest) is obtained, and the formula is as follows:

[0084]

[0085] Based on the operation process of the SH256 algorithm, before the operation circuit executes the algorithm operation, firstly, 8 groups of hash value initial values ​​(a0~h0) and the input message are written into the storage unit 10. After the CPU of the chip determines that the storage is completed, it controls the operation unit 30 to start and start the SHA256 operation. During the operation process of the SHA256 algorithm, the operation data such as the sub-message block and the hash value are written into the storage unit 10 or read out from the storage unit 10 through DMA or the operation unit 30 itself, and iterative calculation and update are repeated many times to finally obtain the message digest.

[0086] Based on the operation process of the SHA256 algorithm, the data transfer method in the operation process is illustrated with examples.

[0087] Assume that the message consists of N message blocks, each with M (0) 、M(1) ,……,M (N-1) To represent, take the first message block M (0) For example, it is split into 16 sub-message blocks. To express.

[0088] During the first loop operation of the first iterative operation, the operation unit 30 reads the sub-message block from the storage unit 10. Based on formula (1), the sub-message block M after operation is obtained. 0 , and then the sub-message block M after the operation 0 The message is transported back to the storage unit 10, and a preset hash value initial value is read from the storage unit, and the sub-message block M after the operation is calculated. 0 The hash value is updated to obtain the hash value of the first cycle operation, and the hash value of this cycle operation is stored back in the storage unit 10.

[0089] During the second cycle operation, the operation unit 30 reads the sub-message block from the storage unit 10. Perform the operation to obtain the sub-message block M after the operation 1 , and then the sub-message block M after the operation 1 The message is transported back to the storage unit 10, and the hash value obtained in the previous cycle operation, that is, the hash value obtained in the first cycle operation, is read from the storage unit, and the sub-message block M after the operation is calculated. 1 The hash value is updated, and the hash value of this cyclic operation is stored back in the storage unit 10.

[0090] And so on until 64 cycles are completed, the first message block M is determined (0) The iterative operation is completed, and so on until N iterations are completed, and the final message digest is calculated.

[0091] In one embodiment of the present invention, the storage unit 10 includes a first storage space, a second storage space and a third storage space, wherein the operation unit 30 is further used to, during each iterative operation, store the hash value obtained by the last loop operation in the first storage space, so as to serve as the initial value of the hash value of the first loop operation during the iterative operation of the next message block; store the calculated sub-message block obtained by each loop operation in the second storage space; and store the hash value obtained by each loop operation in the third storage space.

[0092] This embodiment divides the space of the storage unit 10, stores the initial value of the hash value in the first storage space, stores the sub-message blocks including the received message and the sub-message blocks obtained by calculation in the second storage space, and stores the hash value obtained in each cycle operation in the third storage space to facilitate data reading and writing during the operation process.

[0093] Before the SHA256 operation starts, the preset hash value initial value is first stored in the first storage space, and the input message M is stored in the second storage space.

[0094] To the message block M (0) Taking iterative operation as an example, in the first loop operation process, the operation unit 30 reads the sub-message block from the second storage space Perform the operation and convert the sub-message block M after the operation 0 Store it in the second storage space, read the initial value of the hash value from the first storage space, and combine it with the calculated sub-message block M 0 The initial value of the hash value is updated by operation, and the hash value obtained in the first cycle is stored in the third storage space; in the second cycle operation process, the operation unit 30 reads the sub-message block from the second storage space Perform the operation and convert the sub-message block M after the operation 1 The hash value obtained in the first cycle is stored in the second storage space, and the hash value obtained in the second cycle is read from the third storage space, and the hash value obtained in the second cycle is stored in the third storage space. Similarly, in the sixty-fourth cycle operation process, the hash value obtained in the sixty-fourth cycle is stored in the first storage space for the next iteration operation, that is, as the message block M (1) The initial hash value used in the first loop operation during the iterative operation.

[0095] It is understandable that in the first loop operation in the first iterative operation process, the initial value of the hash value stored in the first storage space is preset, and in the subsequent loop processes, the hash value obtained in the previous loop operation in each iterative operation process is used.

[0096] In one embodiment of the present invention, the second storage space includes multiple sub-storage spaces, each sub-storage space is used to store a message block, each sub-storage space includes multiple sub-storage space blocks, each sub-storage space block is used to store a sub-message block, wherein the operation unit 30 is also used to store the sub-message blocks after operation in a first-store-first-overwrite manner when the total number of loop operations in each iterative operation process is greater than the number of sub-storage space blocks.

[0097] Specifically, the message includes N message blocks, each of which is represented by M (0) 、M (1) ,……,M (N-1) Each message block is stored in a corresponding sub-storage space, and each message block is divided into 16 parts, with sub-message blocks M( 0 ) as an example, split into Each sub-message block is stored in a corresponding sub-storage space block.

[0098] Assuming that the number of sub-storage space blocks is equal to the number of sub-message blocks, when executing the message block M (0) In the first loop, first read from the second storage space Then the sub-message block M after the operation 0 Save to The sub-message block M is overwritten and updated for the storage bit, and so on. When the seventeenth cycle is executed, the sub-message block M after the operation is 16 Stored to the previous sub-message block M 0 The storage bits of the sub-message block M 0 The overwriting is performed, and so on, until the loop ends. Therefore, the first-store-first-overwrite method can realize the reuse of storage bits while ensuring the stable operation, thereby reducing the storage space requirement.

[0099] In summary, according to the operation circuit of the embodiment of the present invention, the storage unit is connected to the bus, the storage unit is used to store data, the DMA unit is connected to the bus, the DMA unit is used to store data in the storage unit or read from the storage unit, the operation unit is connected to the bus, the operation unit is used for operation, and according to the working state of the storage unit, the DMA unit is controlled or itself stores the operation data in the storage unit or reads from the storage unit. Therefore, the operation circuit stores the relevant data in the operation process through the storage unit, which greatly reduces the application of registers in the operation unit, reduces the area and application cost of the hardware implementation circuit of the operation unit, and at the same time, during the operation process, the operation unit can select the data transmission path for storing the operation data in the storage unit or reading from the storage unit according to the working state of the storage unit, thereby ensuring the stable operation of the operation process.

[0100] Corresponding to the above embodiment, the present invention also proposes a chip.

[0101] like Figure 3 As shown, the chip 100 according to the embodiment of the present invention includes the above-mentioned operation circuit 110 .

[0102] According to the chip of the embodiment of the present invention, based on the above-mentioned operation circuit, the relevant data in the operation process is stored through the storage unit, which greatly reduces the application of registers in the operation unit, reduces the area and application cost of the hardware implementation circuit of the operation unit, and at the same time, during the operation process, the operation unit can select the data transmission path for storing the operation data to the storage unit or reading from the storage unit according to the working state of the storage unit, thereby ensuring the stable operation of the operation process.

[0103] Corresponding to the above embodiment, the present invention further provides an electronic device.

[0104] like Figure 4 As shown, the electronic device 1000 of the embodiment of the present invention includes the above chip 100. It is understandable that the electronic device 1000 is an electrical device composed of microelectronic devices, and can be an air conditioner, a washing machine, a mobile phone, etc., which is not limited here.

[0105] The electronic device according to the embodiment of the present invention is based on the above-mentioned computing system, which ensures the stable operation of the electronic device.

[0106] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0107] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0109] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0110] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0111] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A computing circuit, characterized in that: include: A storage unit, connected to the bus and used for storing data; A DMA unit, the DMA unit is connected to the bus and is used to store data to the storage unit or read data from the storage unit; An operation unit is connected to the bus, and is used for operation. According to the working state of the storage unit, the operation unit controls the DMA unit or itself to store the operation data to the storage unit or read from the storage unit.

2. The operation circuit according to claim 1, characterized in that: The computing unit is used to: When the working state is an idle state, controlling itself to store the operation data into the storage unit or read the operation data from the storage unit; When the working state is a busy state, the DMA unit is controlled to start working so as to store the operation data into the storage unit or read the operation data from the storage unit.

3. The operation circuit according to claim 2, characterized in that: The operation unit includes a mutation transmission subunit, which is connected to the storage unit through a data line. The operation unit is used to control the mutation transmission subunit to start working so as to store operation data into the storage unit or read from the storage unit.

4. The operation circuit according to claim 2, characterized in that: The operation circuit also includes a bus arbiter, which is arranged between the DMA unit and the bus. The bus arbiter is used to obtain a bus state of the bus, and the DMA unit is used to store operation data in the storage unit or read from the storage unit according to the bus state.

5. The operation circuit according to claim 4, characterized in that: The operation circuit also includes an identification unit, which is connected to the bus. The identification unit is used to obtain the working status of the storage unit and generate a corresponding signal to send to the operation unit. The operation unit is also used to determine the working status of the storage unit based on the signal.

6. The operation circuit according to claim 5, characterized in that: The identification unit is used to record the number of times the storage unit is accessed by the processor within a preset time, and determine the working state of the storage unit according to the number of times.

7. The operation circuit according to claim 6, characterized in that: The identification unit is arranged in the bus arbiter or the processor.

8. The operation circuit according to any one of claims 1 to 7, characterized in that: The operation includes a SHA256 operation, the operation data includes a hash value and a message, the message includes a plurality of message blocks, each of the message blocks includes a plurality of sub-message blocks, wherein: The operation unit is used to perform an iterative operation for each message block, and perform multiple loop operations during the iterative operation process. In each loop operation process, Reading a corresponding sub-message block from the storage unit for operation to obtain a sub-message block after operation, and storing the sub-message block after operation in the storage unit; The hash value obtained in the last cycle operation is read from the storage unit, and the hash value obtained in the last cycle operation is updated according to the sub-message block after the operation to obtain the hash value of this cycle operation, and the hash value of this cycle operation is stored in the storage unit.

9. The operation circuit according to claim 8, characterized in that: The storage unit includes a first storage space, a second storage space and a third storage space, wherein the operation unit is further used for, in each iterative operation process, The hash value obtained by the last loop operation is stored in the first storage space so as to be used as the initial value of the hash value of the first loop operation in the iterative operation process of the next message block; The calculated sub-message blocks obtained by each cyclic calculation are stored in the second storage space; The hash value obtained in each cyclic operation is stored in the third storage space.

10. The operation circuit according to claim 9, characterized in that: The second storage space includes multiple sub-storage spaces, each of which is used to store one message block, and each of the sub-storage spaces includes multiple sub-storage space blocks, each of which is used to store one sub-message block, wherein the operation unit is also used to store the sub-message blocks after the operation in a first-store-first-overwrite manner when the total number of loop operations in each iterative operation process is greater than the number of sub-storage space blocks.

11. A chip, characterized in that: The method comprises the operation circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: Comprising the chip according to claim 11.

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