Semiconductor device and manufacturing method thereof

Abstract

According to the semiconductor device and the manufacturing method thereof, on the premise that cost and process complexity are not increased, while a DTI (second trench) is manufactured, one or more third trenches with smaller widths are additionally arranged between an MTI (first trench) and an internal device area, third trench isolation structures are filled, the third trenches with smaller widths are shallower in depth, and the third trenches with smaller widths are filled with third trench isolation structures. The third groove with the narrow width is filled with a third groove isolation structure-thermal silicon oxide layer, the voltage resistance performance is excellent, the isolation between the MTI and the internal device area can be effectively improved, the minimum design distance between the original MTI and the internal device area is shortened, no extra technology needs to be added, the chip cost is reduced, and the reliability of the chip is improved. And the chip competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and process technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the existing semiconductor device structure, the DTI with P-type polysilicon goes deep into the P-type substrate to electrically connect the P-type substrate to the device surface, and the MTI with N-type polysilicon goes deep into the N-type buried layer to electrically connect the N-type buried layer to the device surface. However, when the concentration of N-type polysilicon in the MTI is high, the N-type polysilicon in the MTI will have the problem of lateral diffusion. In order to ensure the withstand voltage and not affect the internal chip, the isolation distance between the MTI and the N-type well or P-type well with different voltages of the internal chip will be designed to be larger, which results in a larger area of ​​the overall device, which is not conducive to cost and leads to insufficient competitiveness.

[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can effectively solve the problems of the prior art.

[0005] To achieve the above-mentioned purpose, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer, wherein the second doping type is opposite to the first doping type; forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a second trench in the semiconductor body A trench and at least one third trench, wherein the second trench is located outside the area surrounded by the first trench, the second trench extends from the top surface of the epitaxial layer to the substrate, and at least one third trench is located in the area surrounded by the first trench, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, and the width of the third trench is smaller than the width of the second trench; a third trench isolation structure is formed in the third trench; a second trench structure is formed in the second trench, and the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; and a device region is formed in the epitaxial layer in the area surrounded by the third trench.

[0006] In one or more embodiments of the present invention, the third trench isolation structure completely fills the third trench.

[0007] In one or more embodiments of the present invention, a first trench is formed in the semiconductor body, comprising: forming a hard mask layer on the top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a first soft mask layer to form a first trench in the semiconductor body; and stripping the first soft mask layer.

[0008] In one or more embodiments of the present invention, forming the hard mask layer includes: depositing a first oxide layer on a top surface of the epitaxial layer; depositing a first nitride layer on the first oxide layer; and depositing a first dielectric layer on the first nitride layer.

[0009] In one or more embodiments of the present invention, forming the hard mask layer includes: depositing a first oxide layer and / or a first nitride layer on a top surface of the epitaxial layer.

[0010] In one or more embodiments of the present invention, forming a first trench structure in the first trench includes: growing a barrier layer on the sidewalls and bottom wall of the first trench; etching and removing the barrier layer on the bottom wall of the first trench; depositing a first conductive material having a second doping type so that the first conductive material fills the first trench; and removing the first conductive material on the hard mask layer and a portion of the hard mask layer.

[0011] In one or more embodiments of the present invention, the first conductive material is selected from polysilicon.

[0012] In one or more embodiments of the present invention, the barrier layer includes a second oxide layer.

[0013] In one or more embodiments of the present invention, the barrier layer includes a second oxide layer and a second nitride layer.

[0014] In one or more embodiments of the present invention, before the step of growing a barrier layer on the sidewalls and bottom wall of the first trench, the step further includes: growing a sacrificial oxide layer on the sidewalls and bottom wall of the first trench; and removing the sacrificial oxide layer by a wet method.

[0015] In one or more embodiments of the present invention, a second trench and at least one third trench are formed in the semiconductor body, including: depositing a third nitride layer on the hard mask layer, the third nitride layer covering the first trench structure in the first trench; etching the third nitride layer, the hard mask layer and the semiconductor body using a second soft mask layer to form a second trench and at least one third trench in the semiconductor body; and stripping the second soft mask layer.

[0016] In one or more embodiments of the present invention, the plurality of third grooves are all formed within a range surrounded by the first grooves.

[0017] In one or more embodiments of the present invention, forming a third trench isolation structure in the third trench includes: growing a third oxide layer in the third trench using a thermal oxidation process, wherein the third oxide is at least filled on the sidewalls and bottom wall of the third trench.

[0018] In one or more embodiments of the present invention, a second trench structure is formed in the second trench, including: growing a third oxide layer on the sidewalls and bottom wall of the second trench using a thermal oxidation process; depositing a second dielectric layer so that the second dielectric layer is formed on the sidewalls and bottom wall of the second trench; etching and removing the second dielectric layer and the third oxide layer on the bottom wall of the second trench; depositing a second conductive material having a first doping type so that the second conductive material fills the second trench; and removing the second conductive material, the second dielectric layer, and the hard mask layer on the top surface of the epitaxial layer.

[0019] In one or more embodiments of the present invention, the deposition of the second conductive material is performed twice; before the second deposition of the second conductive material, the first deposited second conductive material in the second trench is dry-etched back.

[0020] In one or more embodiments of the present invention, a third oxide layer is grown simultaneously in the third trench and on the side walls and bottom walls of the second trench using a thermal oxidation process; the third oxide layer is at least filled on the side walls and bottom walls of the third trench or is completely filled in the third trench to form the third trench isolation structure; a second dielectric layer is deposited on the side walls and bottom walls of the second trench; the second dielectric layer and the third oxide layer on the bottom wall of the second trench are etched and removed; a second conductive material having a first doping type is deposited so that the second conductive material fills the second trench; and the second conductive material, the second dielectric layer, and the hard mask layer on the top surface of the epitaxial layer are removed to form the second trench structure in the second trench.

[0021] In one or more embodiments of the present invention, before forming the device region in the epitaxial layer, the method further includes: forming a plurality of shallow trench isolation structures on the epitaxial layer, wherein the third trench partially overlaps with the shallow trench isolation structure.

[0022] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer, wherein the second doping type is opposite to the first doping type; forming a second trench and at least one third trench in the semiconductor body, wherein the second trench extends from a top surface of the epitaxial layer to the substrate, the third trench is located in an area surrounded by the first trench, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, and the width of the third trench is smaller than the width of the second trench; forming a third trench isolation structure in the third trench; forming a second trench structure in the second trench, the second trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer; forming a first trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer to the buried layer, the first trench being located within the area enclosed by the second trench and outside the area enclosed by at least one of the third trenches; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a device region in the epitaxial layer within the area enclosed by the third trench.

[0023] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer, wherein the second doping type is opposite to the first doping type; forming a first trench and at least one third trench in the semiconductor body, wherein at least one of the third trenches is located in a region surrounded by the first trench, wherein the first trench extends from a top surface of the epitaxial layer to the buried layer, and wherein the third trench extends from a top surface of the epitaxial layer to a region within the epitaxial layer or within the buried layer. layer, the width of the third trench is smaller than the width of the first trench; a first trench structure is formed in the first trench, and the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer; a third trench isolation structure is formed in the third trench; a second trench is formed in the semiconductor body, the second trench is located outside the area enclosed by the first trench, and the second trench extends from the top surface of the epitaxial layer to the substrate; a second trench structure is formed in the second trench, and the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; a device region is formed in the epitaxial layer within the area enclosed by the third trench.

[0024] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer, the second doping type being opposite to the first doping type; forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer; forming a second trench, at least one third trench, and a fourth trench in the semiconductor body, the second trench being located outside an area enclosed by the first trench, the second trench extending from the top surface of the epitaxial layer to the substrate, at least one third trench The third trench is located in the area surrounded by the first trench, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, the width of the third trench is smaller than the width of the second trench, the fourth trench is located between the second trench and the first trench, the fourth trench extends from the top surface of the epitaxial layer to the substrate, and the depth of the fourth trench is smaller than the depth of the second trench; a third trench isolation structure is formed in the third trench; a second trench structure is formed in the second trench, the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; a fourth trench isolation structure is formed in the fourth trench, the fourth trench isolation structure is configured to isolate the second trench structure from the first trench structure; and a device region is formed in the epitaxial layer in the area surrounded by the third trench.

[0025] In one or more embodiments of the present invention, before forming the first trench in the semiconductor body, the step of forming a hard mask layer on the top surface of the epitaxial layer is further included.

[0026] In one or more embodiments of the present invention, a third oxide layer is grown simultaneously in the third trench and on the side walls and bottom walls of the second trench and the side walls and bottom walls of the fourth trench using a thermal oxidation process; the third oxide layer is at least filled on the side walls and bottom walls of the third trench or completely filled in the third trench to form the third trench isolation structure; a second dielectric layer is deposited on the side walls and bottom walls of the second trench and the side walls and bottom walls of the fourth trench; the second dielectric layer and the third oxide layer on the bottom wall of the second trench are etched and removed; a second conductive material having a first doping type is deposited so that the second conductive material fills the second trench and the fourth trench; the second conductive material, the second dielectric layer and the hard mask layer on the top surface of the epitaxial layer are removed to form the second trench structure in the second trench and the fourth trench isolation structure in the fourth trench.

[0027] An embodiment of the present invention further provides a semiconductor device, including a semiconductor body, a first trench, a first trench structure, a second trench, a second trench structure, at least one third trench, and a third trench isolation structure. The semiconductor body includes a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having a first doping type disposed on the buried layer, wherein a device region is formed in the epitaxial layer, and the second doping type is opposite to the first doping type; the first trench extends from the top surface of the epitaxial layer to the buried layer; the first trench structure is disposed in the first trench, and the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer; the second trench is located outside the region enclosed by the first trench, and the second trench extends from the top surface of the epitaxial layer to the buried layer; The surface of the epitaxial layer extends to the substrate; the second trench structure is arranged in the second trench, and the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; the third trench is located in the area enclosed by the first trench and is located at the periphery of the device area, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer and does not penetrate the buried layer, and the width of the third trench is smaller than the width of the second trench; the third trench isolation structure is arranged in the third trench, and the third trench isolation structure is configured to isolate the first trench structure and the device area in the epitaxial layer.

[0028] In one or more embodiments of the present invention, a plurality of shallow trench isolation structures are formed in the epitaxial layer, and the third trench partially overlaps with the shallow trench isolation structure.

[0029] In one or more embodiments of the present invention, the first trench structure includes a first conductive material having a second doping type, and the first conductive material is selected from polysilicon.

[0030] In one or more embodiments of the present invention, the device includes a plurality of third trenches; the plurality of third trenches are all disposed in the region surrounded by the first trenches.

[0031] Another embodiment of the present invention further provides a semiconductor device, comprising: a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, a device region being formed in the epitaxial layer, the second doping type being opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer to the buried layer; a first trench structure disposed in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer; a second trench located outside an area enclosed by the first trench, the second trench extending from the top surface of the epitaxial layer to the substrate; a second trench structure disposed in the second trench, the second trench structure being configured to electrically connect the substrate to the buried layer; to the top surface of the epitaxial layer; a fourth trench located between the second trench and the first trench, the fourth trench extending from the top surface of the epitaxial layer to the substrate, the depth of the fourth trench being less than the depth of the second trench; a fourth trench isolation structure arranged in the fourth trench, the fourth trench isolation structure being configured to isolate the second trench structure from the first trench structure; at least one third trench located within the area enclosed by the first trench and at the periphery of the device area, the third trench extending from the top surface of the epitaxial layer into the epitaxial layer or the buried layer and not penetrating the buried layer, the width of the third trench being less than the width of the second trench; a third trench isolation structure arranged in the third trench, the third trench isolation structure being configured to isolate the first trench structure from the device area in the epitaxial layer.

[0032] In one or more embodiments of the present invention, the first trench structure includes a first conductive material having a second doping type, and the first conductive material is selected from polysilicon.

[0033] Compared with the prior art, the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, without increasing the cost and process complexity, while manufacturing the DTI (the second trench), one or more third trenches with narrower width are added between the MTI (the first trench) and the internal device area and filled with the third trench isolation structure. The third trench with narrower width has a shallower depth and will not affect the connection of the original N-type buried layer. Moreover, the third trench with narrower width will be completely filled with the third trench isolation structure-thermal silicon oxide layer, and has excellent withstand voltage performance, which can effectively improve the isolation between the MTI and the internal device area, and prevent the conductive material in the MTI from lateral diffusion and connection in the device area, affecting the device performance. At the same time, further, the minimum design distance between the original MTI and the internal device area can be reduced, and no additional process is required, thereby reducing chip costs and improving chip competitiveness.

[0034] The semiconductor device and its manufacturing method according to the embodiment of the present invention are based on the existing single deep trench isolation process structure, and utilize the theory of the correlation between the depth of the trench and the width of the trench: the smaller the width, the shallower the trench, to form two trench structures with different depths without increasing the cost; wherein, the newly added third trench with a narrower width is completely filled with a thermal silicon oxide layer, and the withstand voltage will be significantly improved compared with the shallow trench isolation (STI) of the original process.

[0035] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, an oxidation trench deeper than STI is added between MTI (first trench) and the internal device area, which is helpful for device isolation; and compared with existing devices, the space from MTI to the internal device area can be reduced, thereby saving area and cost; at the same time, the process is exactly the same as the original process, without any additional cost.

[0036] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, since the third oxide layer in the narrow third trench is grown by a thermal oxidation process, its quality is better than the deposited oxide; in addition, the depth of the new third trench is deeper than the depth of the STI trench; from these two aspects, the new semiconductor device structure can effectively improve the isolation, and at the same time can also reduce the chip size to reduce the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;

[0038] Figure 2a-2s is a process for manufacturing a semiconductor device according to a first embodiment of the present invention;

[0039] Figure 3 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;

[0040] Figure 4 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0041] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0042] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0043] As mentioned in the background technology, in the existing semiconductor device structure, the N-type polysilicon in the MTI will have the problem of lateral diffusion, which affects the internal chip and the voltage resistance of the device. In order to solve this problem, the industry usually adopts a solution of increasing the isolation distance between the MTI and the N-type well or P-type well with different voltages of the internal chip, but this solution will result in a larger area of ​​the overall device, which is not conducive to cost and lacks competitiveness.

[0044] In order to solve the above technical problems, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device. Under the premise of not increasing the cost and process complexity, while manufacturing the DTI (second trench), one or more third trenches with narrower width are added between the MTI (first trench) and the internal device area and filled with the third trench isolation structure. The third trench with narrower width has a shallower depth and will not affect the connection of the original N-type buried layer. Moreover, the third trench with narrower width will be completely filled with the third trench isolation structure-thermal silicon oxide layer, and has excellent withstand voltage performance, which can effectively improve the isolation between the MTI and the internal device area, and prevent the conductive material in the MTI from diffusing laterally to the device area and connecting to affect the device performance. At the same time, further, the minimum design distance between the original MTI and the internal device area can be reduced, without adding additional processes, reducing chip costs and improving chip competitiveness.

[0045] The semiconductor device and the method for manufacturing the semiconductor device of the present invention are described in detail below with reference to a plurality of specific embodiments and in conjunction with the accompanying drawings.

[0046] like Figure 1 As shown, a semiconductor device according to an embodiment of the present invention includes a semiconductor body 10. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having the first doping type disposed on the buried layer 12, wherein a device region 14 is formed in the epitaxial layer 13. The second doping type is opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. The p-type dopant may include boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0047] The first trench 20, the second trench 30 and the third trench 40 are all formed in the semiconductor body 10, wherein the third trench 40 is located between the first trench 20 and the device region 14. The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. The second trench 30 extends from the top surface of the epitaxial layer 13 to the substrate 11. The third trench 40 extends from the top surface of the epitaxial layer 13 to the inside of the epitaxial layer 13 or the buried layer 12. The maximum width of the third trench 40 is less than the maximum width of the second trench 30. The third trench 40 does not penetrate the buried layer 12. The third trench 40 and the first trench 20 can be formed in the same process; or, the third trench 40 and the second trench 30 can be formed in the same process, which will be described in detail below.

[0048] The first trench structure 50 is disposed in the first trench 20, and the first trench structure 50 is configured to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13. Figure 1 As shown, the first trench structure 50 includes a barrier layer 51 and a first conductive material 52 having a second doping type. The barrier layer 51 is formed on a portion of the sidewall and bottom wall of the first trench 20. In one embodiment, the barrier layer 51 may include a second oxide layer 511; or, the barrier layer 51 may include a second oxide layer 511 and a second nitride layer 512, and the second nitride layer 512 is located on the surface of the second oxide layer 511. The first conductive material 52 is filled in the first trench 20, that is, extends from the top surface of the epitaxial layer 13 to the bottom of the first trench 20 and contacts the buried layer 12. With this arrangement, the first conductive material 52 can be used as a pickup structure of the buried layer 12 to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13. In this embodiment, the first conductive material 52 is polysilicon.

[0049] The second trench structure 60 is disposed in the second trench 30, and the second trench structure 60 is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. Figure 1 As shown, the second trench structure 60 includes a third oxide layer 61, a second dielectric layer 62, and a second conductive material 63 having a first doping type. The third oxide layer 61 is formed on the sidewalls and a portion of the bottom wall of the second trench 30. The second dielectric layer 62 is formed on the third oxide layer 61 and is also located on the sidewalls and a portion of the bottom wall of the second trench 30. In one embodiment, the second dielectric layer 62 includes a TEOS mask layer. The second conductive material 63 is filled in the second trench 30, that is, extends from the top surface of the epitaxial layer 13 to the bottom of the second trench 30 and contacts the substrate 11. With this arrangement, the second conductive material 63 can be used as a pickup structure of the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. In one embodiment, the second conductive material 63 is polysilicon.

[0050] The third trench isolation structure 70 is filled in the third trench 40 to isolate the first trench structure 50 from the device region 14 in the epitaxial layer 13. In one embodiment, the third trench isolation structure 70 includes a third oxide layer 61, and the third oxide layer 61 can completely fill the third trench 40. The third oxide layer 61 in the third trench 40 can be formed when the third oxide layer 61 is formed in the second trench 30, and because the width of the third trench 40 is much smaller than that of the second trench 30, the depth of the third trench 40 is much shallower than that of the second trench 30, so that when the third oxide layer 61 is formed on the sidewall and bottom wall of the second trench 30, the third oxide layer 61 can be fully grown inside the third trench 40. Since the third trench isolation structure 70 is located between the first trench 20 and the device region 14, and the depth of the third trench isolation structure 70 is greater than the depth of the device region 14, it can well block the first conductive material that may diffuse laterally in the first trench structure 50, thereby reducing the distance between the first trench structure 50 and the device region 14 during device manufacturing, thereby reducing the area of ​​the device, ensuring device quality while reducing costs. The third isolation structure 70 and the third trench 40 have a certain depth but do not penetrate the buried layer 12, because the third isolation structure 70 needs to isolate the first trench structure 50 from the device region 14, and cannot affect the electrical connection of the buried layer 12.

[0051] In other embodiments, the third trench isolation structure 70 may also include a third oxide layer 61 and a second dielectric layer 62 , and the third oxide layer 61 and the second dielectric layer 62 may completely fill the third trench 40 .

[0052] The shallow trench isolation structure 80 is formed in the epitaxial layer 13 of the semiconductor body 10, and is used to isolate different devices on the epitaxial layer 13 of the semiconductor body 10. The depth of the third trench 40 is much greater than the depth of the shallow trench isolation structure 80, and the third trench 40 partially overlaps with the shallow trench isolation structure 80. Since the depth of the third trench 40 is deeper than the depth of the shallow trench isolation structure 80, the isolation degree can be further effectively improved.

[0053] Figure 2a to Figure 2s A process of manufacturing a semiconductor device according to a first embodiment of the present application is shown. Figure 2a to Figure 2s The process shown can be used to make Figure 1 The semiconductor device shown in the above Figure 1 The description of the semiconductor device may be incorporated herein.

[0054] like Figure 2aAs shown, a semiconductor body 10 is provided. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having a first doping type disposed on the buried layer 12. The thickness of the epitaxial layer 13 is about 8-13 μm. A device region 14 (refer to Figure 1 As shown). The second doping type is opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. The p-type dopant may include boron (B), aluminum (Al), indium (In) or a combination thereof, while the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. The buried layer 12 may have a blanket structure having substantially the same horizontal extension as the substrate 11, laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure. The epitaxial layer 13 may be used to form different device regions.

[0055] like Figure 2b As shown, a hard mask layer 15 is formed on the top surface of the epitaxial layer 13. Forming the hard mask layer 15 may include: growing or depositing a first oxide layer 151 on the top surface of the epitaxial layer 13, the thickness of the first oxide layer 151 is 100A to 200A; depositing a first nitride layer 152 on the first oxide layer 151, the thickness of the first nitride layer 152 is 1000A to 2000A; depositing a first dielectric layer 153 on the first nitride layer 152, the thickness of the first dielectric layer 153 is 2000A to 3000A, and the first dielectric layer 153 is preferably a TEOS mask layer. In other embodiments, the hard mask layer 15 may have other structures, for example, a structure in which a first oxide layer 151 is grown or deposited on the top surface of the epitaxial layer 13, and a first nitride layer 152 is deposited on the first oxide layer 151. In some embodiments, the substrate 11 , the buried layer 12 , and the epitaxial layer 13 are formed of silicon material, the first oxide layer 151 is formed of silicon dioxide, and the first nitride layer 152 is formed of silicon nitride.

[0056] like Figure 2c As shown, the hard mask layer 15 and the semiconductor body 10 can be etched once using the first soft mask layer to form a first trench 20 in the hard mask layer 15 and the semiconductor body 10 that penetrates the hard mask layer 15 and goes deep into the semiconductor body 10. The first trench 20 extends from the top surface of the epitaxial layer 13 to the buried layer 12. In some embodiments, the first soft mask layer can be a photoresist. After the first trench 20 is etched, the first soft mask layer is stripped.

[0057] like Figure 2dAs shown, a barrier layer 51 is grown on the sidewalls and bottom wall of the first trench 20. The barrier layer 51 may include a combined layer structure of a second oxide layer 511 and a second nitride layer 512, or may be a simple second oxide layer 511. Exemplarily, a thin layer of oxidation is first performed on the sidewalls and bottom wall of the first trench 20 to form a second oxide layer 511, and the thickness of the second oxide layer 511 is about 100A to 200A; then a thin second nitride layer 512 is formed on the second oxide layer 511 in the first trench 20, and the thickness of the second nitride layer 512 is about 100A to 300A. Alternatively, the second oxide layer 511 is directly formed on the sidewalls and bottom wall of the first trench 20, and the thickness of the second oxide layer 512 is 300A to 1000A, so as to achieve better isolation.

[0058] Optionally, before growing the barrier layer 51 on the sidewalls and bottom wall of the first trench 20, a sacrificial oxide layer 110A may be grown on the sidewalls and bottom wall of the first trench 20, and then removed by wet stripping. By stripping the sacrificial oxide layer, damage on the sidewalls and bottom wall generated during the etching process can be removed, the sidewalls of the first trench 20 can be smoothed, and the opening width of the second trench 20 on the top surface of the epitaxial layer 13 can be further widened by stripping the sacrificial oxide layer.

[0059] like Figure 2e As shown, the barrier layer 51 at the bottom of the first trench 20 is etched away by dry etching. The first trench 20 is directly connected to the buried layer 12 of the semiconductor body 10, so that the subsequent first conductive material 52 is electrically connected to the buried layer 12. It should be noted that during dry etching, the first dielectric layer 153 in the hard mask layer 15 may have a loss of several hundred Å, depending on the dry etching selectivity.

[0060] like Figure 2f As shown, the deposition of the first conductive material 52 having the second doping type is performed so that the first conductive material 52 fills the first trench 20. In some embodiments, the first conductive material 52 is deposited so that the first conductive material 52 covers the top surface of the first dielectric layer 153. Other types of first conductive materials 52 are also feasible. The first conductive material 52 is selected from polysilicon.

[0061] like Figure 2gAs shown, the excess first conductive material 52 can be removed by a chemical mechanical polishing (CMP) process, for example, the first conductive material 52 on the first dielectric layer 153 can be removed. The chemical mechanical polishing (CMP) can stop at the first dielectric layer 153 or the first nitride layer 152, depending on the selectivity rate of the polishing. Since part of the first conductive material 52 may also be deposited on the substrate 11 of the semiconductor body 10 when the first conductive material 52 is deposited, the first conductive material 52 on the substrate 11 of the semiconductor body 10 is removed while the first conductive material 52 on the first dielectric layer 153 is removed.

[0062] like Figure 2h As shown, the first conductive material 52 is subjected to a dry etching etch-back process. By etching back, the top surface of the first conductive material 52 is kept at the same level as the first nitride layer 152. This step can ensure that no excess first conductive material 52 remains on the top surface of the first dielectric layer 153. The first dielectric layer 153 and the first nitride layer 152 can serve as a protective layer during the etch-back. In some embodiments, the chemical mechanical polishing process may not be performed, and the etch-back process may be performed directly. The etch-back process can more effectively remove the excess first conductive material 52. The barrier layer 51 and the first conductive material 52 in the first trench 20 form a first trench structure 50. Since the first conductive material 52 extends from the top surface of the epitaxial layer 13 to the bottom of the first trench 20 and contacts the buried layer 13, the first conductive material 52 can be used as a pick-up structure of the buried layer 12 to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13. In addition, since the barrier layer 51 disposed in the first trench 20 extends from the top surface of the epitaxial layer 13 to the bottom of the trench, different device regions can be isolated to a certain extent, thereby enhancing isolation performance.

[0063] like Figure 2i As shown, the first dielectric layer 153 is removed.

[0064] like Figure 2j As shown, a third nitride layer 16 is deposited on the first nitride layer 152, and the third nitride layer 16 covers the first conductive material 52 in the first trench 20. Exemplarily, the thickness of the third nitride layer 16 is 500A to 1000A. The third nitride layer 16 can protect the first trench 20 and the first trench structure 50 during the subsequent formation of the second trench 30 and the third trench 40.

[0065] like Figure 2kAs shown, the third nitride layer 16, the hard mask layer 15 and the semiconductor body 10 can be etched once using the second soft mask layer to form a second trench 30 and at least one third trench 40 penetrating the third nitride layer 16, the hard mask layer 15 and the semiconductor body 10. The second trench 30 is formed outside the area surrounded by the first trench structure 50, and the third trench 40 is formed in the area surrounded by the first trench structure 50. The width of the third trench 40 is much smaller than the width of the second trench 30. Therefore, when performing simultaneous etching, the second trench 30 extends from the top surface of the epitaxial layer 13 to the substrate 11, and the third trench 40 extends from the top surface of the epitaxial layer 13 to the epitaxial layer 13 or the buried layer 12. It can be understood that the depth of the trench is related to the width of the trench. The smaller the width, the shallower the depth. For example, the second groove 30 uses a width of 2 μm, so the depth of the second groove 30 is about 30 μm. The third groove 40 uses a width of 0.5 μm, so the depth of the third groove 40 is only about 8.5 μm. Since the third groove 40 and the structure therein play an isolation role for the first groove structure 50 and the device area 14 located within the first groove structure 50, the depth of the third groove 40 should be as deep as possible in the epitaxial layer 13, and can even penetrate the buried layer 12, but cannot penetrate the buried layer 12 to affect the electrical connection in the buried layer 12. Therefore, when etching the second groove 30 and the third groove 40, it is necessary to control the width of the third groove 40 and the etching rate. In this etching process, only the second soft mask layer is consumed, and the third nitride layer 16 will not be lost. In some embodiments, the second soft mask layer can be a photoresist. After the second groove 30 and the third groove 40 are etched, the second soft mask layer is stripped.

[0066] like Figure 2l As shown, a third oxide layer 61 is grown on the sidewalls and bottom wall of the second trench 30 and in the third trench 40. Exemplarily, the sidewalls and bottom wall of the second trench 30 are oxidized by a thermal oxidation process, and the thickness of the third oxide layer 61 is about 3000A to 5000A. Since the width of the third trench 40 is relatively small, while the third oxide layer 61 with a thickness of 3000A to 5000A is formed on the sidewalls and bottom wall of the second trench 30, the third trench 40 is naturally filled with thermal oxide to form a third trench isolation structure 70. At this time, the second trench 30 is still in an open state, and there is a large space therein that is not filled. Since the third trench isolation structure 70 has a depth that penetrates into the bottom of the epitaxial layer 13 or even the buried layer 12 (deeper than the device region 14 inside the device), and the third trench isolation structure 70 is located between the first trench structure 50 and the device region 14 inside the device, it can effectively achieve an isolation effect.

[0067] In other embodiments, if the width of the third trench 40 is relatively wide, while the side walls and bottom walls of the second trench 30 are oxidized by a thermal oxidation process, the bottom wall and side walls of the third trench 40 are covered by thermal oxide, and the middle is still in an open state. There is a certain amount of space that is not filled, and the entire space can be subsequently filled by depositing the second dielectric layer 62 to form a third trench isolation structure 70.

[0068] like Figure 2m As shown, a second dielectric layer 62 is deposited in the second trench 30 so that the second dielectric layer 62 is formed on the sidewalls and bottom wall of the second trench 30. Exemplarily, a high aspect ratio process (HARP) can be used to chemically vapor deposit the second dielectric layer 62. The thickness of the second dielectric layer 62 on the sidewall of the second trench 30 can be 5000A to 6000A. At this time, there is still a space of 0.4μm to 0.8μm in the second trench 30, and the second dielectric layer 62 is only deposited on the top of the third trench 40. In one embodiment, the second dielectric layer 62 can be a TEOS mask layer.

[0069] like Figure 2n As shown, the second dielectric layer 62 and the third oxide layer 61 in the second trench 30 are anisotropically etched to remove the second dielectric layer 62 and the third oxide layer 61 on the bottom wall of the second trench 30, and open the bottom of the second trench 30. Since the third trench 40 is completely filled with thermal oxide, only the second dielectric layer 62 on the surface can be etched. The etching process will form a V-shape at the top of the second trench 30, which has a better effect on the subsequent filling of the second conductive material 63. The third nitride layer 16 on the top will be used as an etching stop layer or a protective layer, and its loss during etching may be less than 500A.

[0070] Optionally, after forming the second dielectric layer 62 , an annealing process may be performed to densify the second dielectric layer 62 and / or the third oxide layer 61 to achieve a better isolation effect.

[0071] like Figure 2o As shown, the second conductive material 63 having the first doping type is deposited so that the second conductive material 63 fills the second trench 30. The second conductive material 63 is in full contact with the substrate 11 and is electrically connected. Since the width of the second trench 30 is relatively wide, when the second conductive material 63 is deposited in the second trench 30, a narrow gap may be formed in the middle of the second trench 30. However, since the depth of the gap in the second trench 30 is very deep, there is no possibility of opening the gap in the subsequent process, so the gap has no effect on the performance of the device.

[0072] Optionally, in order to better realize the electrical extraction of the substrate 11, the second conductive material 63 can be deposited in the second trench 30 in two steps. For example, after the first deposition of the second conductive material 63, the second conductive material 63 can be dry-etched back to further widen the opening width at the top of the second trench 30, thereby obtaining better filling of the second conductive material 63 and reducing the gap in the second trench 30. In some embodiments, the second conductive material 63 is deposited so that the second conductive material 63 covers the top surface of the third nitride layer 16. Other types of second conductive materials 63 are also feasible. The second conductive material 63 is preferably polysilicon.

[0073] like Figure 2p As shown, the excess second conductive material 63 can be removed by a chemical mechanical polishing (CMP) process, for example, the second conductive material 63 on the third nitride layer 16 is removed. The third nitride layer 16 serves as a stop layer for chemical mechanical polishing (CMP). The loss of the third nitride layer 16 depends on the selectivity rate of the polishing, and the normal loss is less than 500A. Since part of the second conductive material 63 may also be deposited on the substrate 11 of the semiconductor body 10 when the second conductive material 63 is deposited, the second conductive material 63 on the substrate 11 of the semiconductor body 10 is removed while the second conductive material 63 on the third nitride layer 16 is removed to obtain better wafer warpage and less stress.

[0074] like Figure 2q As shown, the hard mask layer 15 is used as an etching protection layer, and anisotropic plasma dry etching is performed on the second conductive material 63 and the first conductive material 52 to perform an etch-back process. Through the etch-back, the top surface of the second conductive material 63 and the top surface of the first conductive material 52 are kept on the same horizontal line as the epitaxial layer 13. At this time, the second conductive material 63 at the top of the third trench 40 will be completely removed. Anisotropic plasma dry etching can ensure that no excess second conductive material 63 remains on the top surface of the third nitride layer 16. In some embodiments, the chemical mechanical polishing process can be omitted, and the etch-back process can be directly performed. The etch-back process can more effectively remove the excess second conductive material 63.

[0075] like Figure 2rAs shown, the third nitride layer 16 on the surface of the epitaxial layer 13 and the first nitride layer 152 in the hard mask layer 15 are removed by a wet process using H3PO4. Then, the first oxide layer 151 in the hard mask layer 15 is removed by a wet process using diluted HF. The third oxide layer 61, the second dielectric layer 62, and the second conductive material 63 in the second trench 30 can form a second trench structure 60. Since the second conductive material 63 extends from the top surface of the epitaxial layer 13 to the bottom of the second trench 30 and contacts the substrate 11, the second conductive material 63 can be used as a pickup structure of the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. In addition, since the third oxide layer 61 and the second dielectric layer 62 disposed in the second trench 30 extend from the top surface of the epitaxial layer 13 to the bottom of the trench, different device regions can be isolated to a certain extent, thereby enhancing isolation performance.

[0076] like Figure 2s As shown, a shallow trench isolation structure 80, a device region, and a device region 14 may be formed in the epitaxial layer 13. For illustrative purposes, reference is made to Figure 2s As shown, the normal processes of subsequent CMOS devices can be carried out: STI (shallow trench isolation structure 80), LOCOS, well injection, gate, LDD injection, spacer formation, source / drain injection, silicide formation, ILD (interlayer dielectric layer), contact formation, BEoL metal layer and passivation, etc. Since the above structures can be manufactured using existing processes and are not the innovation of this application, they will not be elaborated in detail here.

[0077] However, it should be noted that when the shallow trench isolation structure 80 is fabricated, it is preferred to fabricate one of the shallow trench isolation structures 80 at the location of the third trench isolation structure 70, and because during the etching of the shallow trench isolation structure 80, the oxide layer grown in the third trench isolation structure 70 will block the etching of the STI and then form a bump profile. Therefore, the third trench isolation structure 70 inside the STI will be higher in the shallow trench isolation structure 80.

[0078] Since the oxide layer in the third trench isolation structure 70 is a thermal oxide grown by a thermal oxidation process or a combination of a thermal oxide grown by a thermal oxidation process and a TEOS mask layer or an oxide layer, its quality is better than that of a deposited oxide. Secondly, the depth of the third trench isolation structure 70 is deeper than that of the STI trench. Therefore, the third trench isolation structure 70 can effectively improve the isolation degree, and can also reduce the device size to reduce the cost.

[0079] It can be understood that in this embodiment, the first trench 20 and the first trench structure 50 are first fabricated, and then the second trench 30, the third trench 40, the second trench structure 60 and the third trench isolation structure 70 are fabricated. In other embodiments, the order can be reversed, that is, the second trench 30, the third trench 40, the second trench structure 60 and the third trench isolation structure 70 are first fabricated, and then the first trench 20 and the first trench structure 50 are fabricated. The fabrication method of this embodiment can be referred to in the attached Figure 2a ~Attached Figure 2s , only the order is changed, and the method and the process of forming each structure do not change much, so they will not be elaborated in detail here.

[0080] It is understandable that the third trench 40 and the third trench isolation structure 70 can also be manufactured simultaneously when the first trench 20 and the first trench structure 50 are manufactured. However, the disadvantage of this manufacturing method is that the third trench 40 will be filled with the first conductive material, which may also introduce lateral outward diffusion of the first conductive material. At the same time, the bottom of the first conductive material may be connected to the buried layer, and the isolation effect is not as good as when the second trench 30 and the second trench structure 60 are manufactured simultaneously.

[0081] refer to Figure 3 As shown, Figure 3 1 is a schematic diagram of the structure of a semiconductor device according to a second embodiment of the present invention. In this embodiment, a plurality of third trenches 40 and third trench isolation structures 70 are provided, and are all located between the first trench structure 50 and the internal device region 14. The provision of a plurality of third trench isolation structures 70 can further improve the isolation. In other embodiments, a third trench 40 and a third trench isolation structure 70 can also be provided between the second trench structure 60 and the first trench structure 50.

[0082] refer to Figure 4 As shown, Figure 4 Schematic diagram of the structure of a semiconductor device according to a third embodiment of the present invention. Figure 1 The difference between the semiconductor device in the first embodiment shown is that, in this embodiment, a narrower fourth trench 90 is further formed between the second trench structure 60 and the first trench structure 50, and the width of the fourth trench 90 is smaller than the width of the second trench 60, and the depth is smaller than the depth of the second trench 60. The fourth trench 90 extends from the top surface of the epitaxial layer 13 to the substrate 11. A fourth trench isolation structure 95 is disposed in the fourth trench 90. The fourth trench isolation structure 95 is configured to isolate the second trench structure 60 from the first trench structure 50. In one embodiment, as Figure 4As shown, the fourth trench isolation structure 95 includes a third oxide layer 61, a second dielectric layer 62, and a second conductive material 63 having a first doping type. The third oxide layer 61 is formed on the sidewalls and bottom wall of the second trench 30. The second dielectric layer 62 is formed on the third oxide layer 61, and is also located on the sidewalls and bottom wall of the second trench 30. In the fourth trench 90, the third oxide layer 61 and the second dielectric layer 62 are completely deposited on the sidewalls and bottom wall of the trench, so the second conductive material 63 does not make electrical contact with the substrate 11. The fourth trench isolation structure 95 thus formed does not have the function of electrical extraction, and it only serves as an isolation function. In one embodiment, the second dielectric layer 62 includes a TEOS mask layer. The second conductive material 63 is filled in the fourth trench 90. In one embodiment, the second conductive material 63 is polysilicon.

[0083] The fourth trench 90 and the fourth trench isolation structure 95 are provided to isolate the first trench structure 50 from the second trench structure 60. Specifically, the electric field between the first trench structure 50 and the second trench structure 60 can be changed, so that the voltage of the point most likely to be broken down between the two can be changed, thereby preventing the breakdown between the two and improving the breakdown voltage.

[0084] Figure 4 The method for manufacturing the semiconductor device is Figure 1 The manufacturing method of the semiconductor device shown is similar, the only difference is that, while forming the second trench 30 and the third trench 40, a fourth trench 90 is also formed; and, while forming the second trench structure 60 in the second trench 30 and the third trench isolation structure 50 in the third trench 40, a fourth trench isolation structure 95 is also formed in the fourth trench 90.

[0085] The previous step (the step to complete the first trench structure) is due to Figure 1 The manufacturing method of the semiconductor device shown is the same and will not be elaborated here. This application elaborates on the subsequent manufacturing steps.

[0086] Exemplary, reference Figure 4As shown, after forming the first trench structure 50, the third nitride layer 16, the hard mask layer 15 and the semiconductor body 10 can be etched once using the second soft mask layer to form a second trench 30, a fourth trench 90 and at least one third trench 40 penetrating the third nitride layer 16, the hard mask layer 15 and the semiconductor body 10. The width of the fourth trench 90 is smaller than the width of the second trench 30, and the width of the third trench 40 is much smaller than the width of the second trench 30. Therefore, when performing simultaneous etching, the second trench 30 extends from the top surface of the epitaxial layer 13 to the substrate 11, the fourth trench 90 extends from the top surface of the epitaxial layer 13 to the substrate 11, but the bottom is higher than the bottom of the second trench 30, and the third trench 40 extends from the top surface of the epitaxial layer 13 to the epitaxial layer 13 or the buried layer 12. It is understandable that the depth of the groove is related to the width of the groove, and the smaller the width, the shallower the depth. For example, the second groove 30 uses a width of 2μm, so the depth of the second groove 30 is about 30μm. The width of the fourth groove 90 is 1.1μm-1.2μm, so the depth of the fourth groove 90 is about 25μm, and it can also penetrate the buried layer 12 to reach the substrate 11. The third groove 40 uses a width of 0.5μm, so the depth of the third groove 40 is only about 8.5μm. In this etching process, only the second soft mask layer is consumed, and the loss of the third nitride layer 16 will not be caused. In some embodiments, the second soft mask layer can be a photoresist. After the second groove 30, the fourth groove 90 and the third groove 40 are etched, the second soft mask layer is stripped.

[0087] A third oxide layer 61 is grown on the sidewalls and bottom wall of the second trench 30, on the sidewalls and bottom wall of the fourth trench 90, and in the third trench 40. Exemplarily, the sidewalls and bottom wall of the second trench 30, and the sidewalls and bottom wall of the fourth trench 90 are oxidized by a thermal oxidation process, and the thickness of the third oxide layer 61 is about 3000A to 5000A. Since the width of the third trench 40 is relatively small, while the third oxide layer 61 with a thickness of 3000A to 5000A is formed on the sidewalls and bottom wall of the second trench 30, the third trench 40 is naturally filled with thermal oxide to form a third trench isolation structure 70. At this time, the second trench 30 and the fourth trench 90 are still in an open state, and there is a large space therein that is not filled. Therefore, since the third trench isolation structure 70 has a depth that penetrates into the bottom of the epitaxial layer 13 or even the buried layer 12 (deeper than the device region 14 inside the device), and the third trench isolation structure 70 is located between the first trench structure 50 and the device region 14 inside the device, the isolation effect can be effectively achieved.

[0088] It is understandable that in other embodiments, if the width of the third trench 40 is relatively wide, while the side walls and bottom walls of the second trench 30 and the fourth trench 90 are oxidized by a thermal oxidation process, only the bottom wall and the side walls of the third trench 40 are covered by thermal oxide, and the middle is still in an open state, with a certain amount of space therein that is not filled. The entire space can then be filled by depositing the second dielectric layer 62 to form a third trench isolation structure 70.

[0089] A second dielectric layer 62 is deposited in the second trench 30 and the fourth trench 90 so that the second dielectric layer 62 is formed on the sidewall and bottom wall of the second trench 30 and on the sidewall and bottom wall of the fourth trench 90. Exemplarily, a high aspect ratio process (HARP) can be used for chemical vapor deposition of the second dielectric layer 62. The thickness of the second dielectric layer 62 on the sidewall of the second trench 30 can be 5000A to 6000A. At this time, there is still 0.4μm to 0.8μm of space in the second trench 30. Because the width of the fourth trench 90 is smaller than that of the second trench 30, the second dielectric layer 62 will be closed at the top of the fourth trench 90. The second dielectric layer 62 is only deposited on the top of the third trench 40. In one embodiment, the second dielectric layer 62 can be a TEOS mask layer or an oxide layer.

[0090] The second dielectric layer 62 and the third oxide layer 61 in the second trench 30 are anisotropically etched to remove the second dielectric layer 62 and the third oxide layer 61 on the bottom wall of the second trench 30 and open the bottom of the second trench 30. Since the top of the fourth trench 90 is closed by the second dielectric layer 62, it is difficult for the etching solution to enter the fourth trench 90 because it is impossible to etch through the second dielectric layer 62 and the third oxide layer 61 at the bottom of the fourth trench 90. Since the third trench 40 is completely filled with thermal oxide, only the second dielectric layer 62 on the surface can be etched. The etching process will form a V-shape at the top of the second trench 30, which has a better effect on the subsequent filling of the second conductive material 63 and can also etch the second dielectric layer 62 at the top of the fourth trench 90. The third nitride layer 16 on the top will be used as an etching stop layer or a protective layer, and its loss during etching may be less than 500A.

[0091] Optionally, after forming the second dielectric layer 62 , an annealing process may be performed to densify the second dielectric layer 62 and / or the third oxide layer 61 to achieve a better isolation effect.

[0092] The second conductive material 63 having the first doping type is deposited so that the second conductive material 63 fills the second trench 30 and the fourth trench 90. The second conductive material 63 in the second trench 30 is in full contact with the substrate 11 and electrically connected. Since the width of the second trench 30 is relatively wide, when the second conductive material 63 is deposited in the second trench 30, a narrow gap may be formed in the middle of the second trench 30. However, since the depth of the gap in the second trench 30 is very deep, there is no possibility of opening the gap in the subsequent process, so the gap has no effect on the performance of the device. As for the fourth trench 90, since the second dielectric layer 62 and the third oxide layer 61 are still retained at the bottom, the second conductive material 63 therein is not in contact with the substrate 11. The second dielectric layer 62, the third oxide layer 61 and the second conductive material 63 in the fourth trench 90 constitute a fourth trench isolation structure 95. The setting of the fourth trench isolation structure 95 improves the isolation and pressure resistance of the device.

[0093] Optionally, in order to better realize the electrical extraction of the substrate 11, the second conductive material 63 can be deposited in the second trench 30 in two steps. For example, after the first deposition of the second conductive material 63, the second conductive material 63 can be dry-etched back to further widen the opening width at the top of the second trench 30, thereby obtaining better filling of the second conductive material 63 and reducing the gap in the second trench 30. In some embodiments, the second conductive material 63 is deposited so that the second conductive material 63 covers the top surface of the third nitride layer 16. Other types of second conductive materials 63 are also feasible. The second conductive material 63 is preferably polysilicon.

[0094] Excess second conductive material 63 may be removed by chemical mechanical polishing (CMP) process, for example, second conductive material 63 on third nitride layer 16 is removed. Third nitride layer 16 serves as a stop layer for chemical mechanical polishing (CMP). The loss of third nitride layer 16 depends on the selectivity rate of polishing, and normal loss is less than 500A. Since part of second conductive material 63 may also be deposited on substrate 11 of semiconductor body 10 when second conductive material 63 is deposited, second conductive material 63 on substrate 11 of semiconductor body 10 is removed while removing second conductive material 63 on third nitride layer 16, so as to obtain better wafer warpage and less stress.

[0095] Using the hard mask layer 15 as an etching protection layer, anisotropic plasma dry etching is performed on the second conductive material 63 and the first conductive material 52 to perform an etch-back process. Through the etch-back, the top surface of the second conductive material 63 and the top surface of the first conductive material 52 are kept at the same level as the epitaxial layer 13. At this time, the second conductive material 63 at the top of the third trench 40 will be completely removed. Anisotropic plasma dry etching can ensure that no excess second conductive material 63 remains on the top surface of the third nitride layer 16. In some embodiments, the chemical mechanical polishing process can be omitted and the etch-back process can be directly performed. The etch-back process can more effectively remove the excess second conductive material 63.

[0096] The third nitride layer 16 on the surface of the epitaxial layer 13 and the first nitride layer 152 in the hard mask layer 15 are removed by a wet process using H3PO4. The first oxide layer 151 in the hard mask layer 15 is then removed by a wet process using diluted HF. The third oxide layer 61, the second dielectric layer 62, and the second conductive material 63 in the second trench 30 can form a second trench structure 60. Since the second conductive material 63 extends from the top surface of the epitaxial layer 13 to the bottom of the second trench 30 and contacts the substrate 11, the second conductive material 63 can be used as a pickup structure of the substrate 11 to electrically connect the substrate 11 to the top surface of the epitaxial layer 13. In addition, since the third oxide layer 61 and the second dielectric layer 62 disposed in the second trench 30 extend from the top surface of the epitaxial layer 13 to the bottom of the trench, different device regions can be isolated to a certain extent, thereby enhancing isolation performance.

[0097] A shallow trench isolation structure 80 and a device region 14 may be formed in the epitaxial layer 13. For illustrative purposes, reference is made to Figure 2s As shown, the normal processes of subsequent CMOS devices can be carried out: STI (shallow trench isolation structure 80), LOCOS, well injection, gate, LDD injection, spacer formation, source / drain injection, silicide formation, ILD (interlayer dielectric layer), contact formation, BEoL metal layer and passivation, etc. Since the above structures can be manufactured using existing processes and are not the innovation of this application, they will not be elaborated in detail here.

[0098] However, it should be noted that when the shallow trench isolation structure 80 is fabricated, it is preferred to fabricate one of the shallow trench isolation structures 80 at the location of the third trench isolation structure 70, and because during the etching of the shallow trench isolation structure 80, the oxide layer grown in the third trench isolation structure 70 will block the etching of the STI and then form a bump profile. Therefore, the third trench isolation structure 70 inside the STI will be higher in the shallow trench isolation structure 80.

[0099] Since the oxide layer in the third trench isolation structure 70 is a thermal oxide grown by a thermal oxidation process or a combination of a thermal oxide grown by a thermal oxidation process and a TEOS mask layer or an oxide layer, its quality is better than that of a deposited oxide. Secondly, the depth of the third trench isolation structure 70 is deeper than that of the STI trench. Therefore, the third trench isolation structure 70 can effectively improve the isolation degree, and can also reduce the device size to reduce the cost.

[0100] It is understandable that in all the above embodiments, in order to save process costs, the third trench 40 is etched synchronously with the second trench 30 or the first trench 20. In other embodiments, a separate process may be used to manufacture the third trench 40 and the third trench isolation structure 70, which can more effectively control the morphology and depth of the third trench 30, but the disadvantage is that it will increase costs to a certain extent.

[0101] Compared with the prior art, the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, without increasing the cost and process complexity, while manufacturing the DTI (the second trench), one or more third trenches with narrower width are added between the MTI (the first trench) and the internal device area and filled with the third trench isolation structure. The third trench with narrower width has a shallower depth and will not affect the connection of the original N-type buried layer. Moreover, the third trench with narrower width will be completely filled with the third trench isolation structure-thermal silicon oxide layer, and has excellent withstand voltage performance, which can effectively improve the isolation between the MTI and the internal device area, and prevent the conductive material in the MTI from lateral diffusion and connection in the device area, affecting the device performance. At the same time, further, the minimum design distance between the original MTI and the internal device area can be reduced, and no additional process is required, thereby reducing chip costs and improving chip competitiveness.

[0102] The semiconductor device and its manufacturing method according to the embodiment of the present invention are based on the existing single deep trench isolation process structure, and utilize the theory of the correlation between the depth of the trench and the width of the trench: the smaller the width, the shallower the trench, to form two trench structures with different depths without increasing the cost; wherein, the newly added third trench with a narrower width is completely filled with a thermal silicon oxide layer, and the withstand voltage will be significantly improved compared with the shallow trench isolation (STI) of the original process.

[0103] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, an oxidation trench deeper than STI is added between MTI (first trench) and the internal device area, which is helpful for device isolation; and compared with existing devices, the space from MTI to the internal device area can be reduced, thereby saving area and cost; at the same time, the process is exactly the same as the original process, without any additional cost.

[0104] According to the semiconductor device and its manufacturing method of the embodiment of the present invention, since the third oxide layer in the narrow third trench is grown by a thermal oxidation process, its quality is better than the deposited oxide; in addition, the depth of the new third trench is deeper than the depth of the STI trench; from these two aspects, the new semiconductor device structure can effectively improve the isolation, and at the same time can also reduce the chip size to reduce the cost.

[0105] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, the second doping type being opposite to the first doping type; forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; forming a second trench and at least one third trench in the semiconductor body, wherein the second trench is located outside the region surrounded by the first trench, the second trench extends from the top surface of the epitaxial layer to the substrate, and at least one third trench is located in the region surrounded by the first trench, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, and the width of the third trench is smaller than the width of the second trench; forming a third trench isolation structure in the third trench; forming a second trench structure in the second trench, the second trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; A device region is formed in the epitaxial layer in a region enclosed by the third trench.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The third trench isolation structure fully fills the third trench.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: forming a first trench in the semiconductor body, comprising: forming a hard mask layer on a top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a first soft mask layer to form a first trench in the semiconductor body; The first soft mask layer is stripped off.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: Forming the hard mask layer includes: depositing a first oxide layer on a top surface of the epitaxial layer; depositing a first nitride layer on the first oxide layer; and A first dielectric layer is deposited on the first nitride layer.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: Forming the hard mask layer includes: A first oxide layer and / or a first nitride layer is deposited on a top surface of the epitaxial layer.

6. The method for manufacturing a semiconductor device according to claim 3, wherein: Forming a first trench structure in the first trench includes: growing a barrier layer on the sidewalls and bottom wall of the first trench; Etching and removing the barrier layer on the bottom wall of the first trench; Depositing a first conductive material having a second doping type so that the first conductive material fills the first trench; The first conductive material on the hard mask layer and a portion of the hard mask layer are removed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first conductive material is selected from polysilicon.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The barrier layer comprises a second oxide layer; or, The barrier layer includes a second oxide layer and a second nitride layer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: Before the step of growing a barrier layer on the sidewalls and bottom wall of the first trench, the method further includes: growing a sacrificial oxide layer on the sidewalls and bottom wall of the first trench; The sacrificial oxide layer is removed by wet method.

10. The method for manufacturing a semiconductor device according to claim 3, wherein: forming a second trench and at least one third trench in the semiconductor body, comprising: Depositing a third nitride layer on the hard mask layer, wherein the third nitride layer covers the first trench structure in the first trench; etching the third nitride layer, the hard mask layer, and the semiconductor body using a second soft mask layer to form a second trench and at least one third trench in the semiconductor body; The second soft mask layer is stripped off.

11. The method for manufacturing a semiconductor device according to claim 3, wherein: A third trench isolation structure is formed in the third trench, comprising: A third oxide layer is grown in the third trench by using a thermal oxidation process, and the third oxide layer at least fills the sidewalls and the bottom wall of the third trench.

12. The method for manufacturing a semiconductor device according to claim 3, wherein: forming a second trench structure in the second trench, comprising: growing a third oxide layer on the sidewalls and bottom wall of the second trench by a thermal oxidation process; Depositing a second dielectric layer so that the second dielectric layer is formed on the sidewalls and bottom wall of the second trench; Etching and removing the second dielectric layer and the third oxide layer on the bottom wall of the second trench; Depositing a second conductive material having a first doping type so that the second conductive material fills the second trench; The second conductive material, the second dielectric layer, and the hard mask layer on the top surface of the epitaxial layer are removed.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Depositing the second conductive material twice; Before depositing the second conductive material for the second time, the second conductive material deposited for the first time in the second trench is dry-etched back.

14. The method for manufacturing a semiconductor device according to claim 3, wherein: Growing a third oxide layer in the third trench and on the sidewalls and bottom walls of the second trench simultaneously by a thermal oxidation process; The third oxide layer is filled at least on the sidewalls and the bottom wall of the third trench or is completely filled in the third trench to form the third trench isolation structure; depositing a second dielectric layer on the sidewalls and bottom wall of the second trench; Etching and removing the second dielectric layer and the third oxide layer on the bottom wall of the second trench; Depositing a second conductive material having a first doping type so that the second conductive material fills the second trench; The second conductive material, the second dielectric layer, and the hard mask layer on the top surface of the epitaxial layer are removed to form the second trench structure in the second trench.

15. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a device region in the epitaxial layer, the method further comprises: A plurality of shallow trench isolation structures are formed on the epitaxial layer, and the third trench partially overlaps with the shallow trench isolation structure.

16. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, the second doping type being opposite to the first doping type; forming a first trench and at least one third trench in the semiconductor body, wherein the first trench extends from the top surface of the epitaxial layer to the buried layer, and at least one third trench is located in a region surrounded by the first trench, and the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, and the width of the third trench is smaller than the width of the first trench; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; forming a third trench isolation structure in the third trench; forming a second trench in the semiconductor body, the second trench being located outside a region enclosed by the first trench, the second trench extending from a top surface of the epitaxial layer to the substrate; forming a second trench structure in the second trench, the second trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; A device region is formed in the epitaxial layer in a region enclosed by the third trench.

17. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, the second doping type being opposite to the first doping type; forming a first trench in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; forming a first trench structure in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; forming a second trench, at least one third trench, and a fourth trench in the semiconductor body, wherein the second trench is located outside the region surrounded by the first trench, the second trench extends from the top surface of the epitaxial layer to the substrate, at least one third trench is located in the region surrounded by the first trench, the third trench extends from the top surface of the epitaxial layer to the epitaxial layer or the buried layer, the width of the third trench is smaller than the width of the second trench, the fourth trench is located between the second trench and the first trench, the fourth trench extends from the top surface of the epitaxial layer to the substrate, and the depth of the fourth trench is smaller than the depth of the second trench; forming a third trench isolation structure in the third trench; forming a second trench structure in the second trench, the second trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; forming a fourth trench isolation structure in the fourth trench, the fourth trench isolation structure being configured to isolate the second trench structure from the first trench structure; A device region is formed in the epitaxial layer in a region enclosed by the third trench.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: Before forming the first trench in the semiconductor body, the method further includes forming a hard mask layer on a top surface of the epitaxial layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Using a thermal oxidation process to simultaneously grow a third oxide layer in the third trench, on the sidewalls and bottom wall of the second trench, and on the sidewalls and bottom wall of the fourth trench; The third oxide layer is filled at least on the sidewalls and the bottom wall of the third trench or is completely filled in the third trench to form the third trench isolation structure; Depositing a second dielectric layer on the sidewalls and bottom wall of the second trench and the sidewalls and bottom wall of the fourth trench; Etching and removing the second dielectric layer and the third oxide layer on the bottom wall of the second trench; Depositing a second conductive material having a first doping type so that the second conductive material fills the second trench and the fourth trench; The second conductive material, the second dielectric layer, and the hard mask layer on the top surface of the epitaxial layer are removed to form the second trench structure in the second trench and to form the fourth trench isolation structure in the fourth trench.

20. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, wherein a device region is formed in the epitaxial layer, the second doping type being opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer to the buried layer; a first trench structure disposed in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; A second trench, located outside the area surrounded by the first trench, the second trench extending from the top surface of the epitaxial layer to the substrate; a second trench structure disposed in the second trench, the second trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; at least one third trench, located in the area surrounded by the first trench and at the periphery of the device area, the third trench extending from the top surface of the epitaxial layer into the epitaxial layer or the buried layer and not penetrating the buried layer, and the width of the third trench being smaller than the width of the second trench; A third trench isolation structure is disposed in the third trench, and the third trench isolation structure is configured to isolate the first trench structure from a device region in the epitaxial layer.

21. The semiconductor device according to claim 20, characterized in that A plurality of shallow trench isolation structures are formed in the epitaxial layer, and the third trench partially overlaps with the shallow trench isolation structure.

22. The semiconductor device according to claim 20, wherein: The first trench structure includes a first conductive material having a second doping type, and the first conductive material is selected from polysilicon.

23. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a substrate having a first doping type, a buried layer having a second doping type disposed on the substrate, and an epitaxial layer having the first doping type disposed on the buried layer, wherein a device region is formed in the epitaxial layer, the second doping type being opposite to the first doping type; a first trench extending from a top surface of the epitaxial layer to the buried layer; a first trench structure disposed in the first trench, the first trench structure being configured to electrically connect the buried layer to a top surface of the epitaxial layer; A second trench, located outside the area surrounded by the first trench, the second trench extending from the top surface of the epitaxial layer to the substrate; a second trench structure disposed in the second trench, the second trench structure being configured to electrically connect the substrate to a top surface of the epitaxial layer; a fourth trench, located between the second trench and the first trench, the fourth trench extending from the top surface of the epitaxial layer to the substrate, and a depth of the fourth trench being less than a depth of the second trench; a fourth trench isolation structure disposed in the fourth trench, wherein the fourth trench isolation structure is configured to isolate the second trench structure from the first trench structure; at least one third trench, located in the area surrounded by the first trench and at the periphery of the device area, the third trench extending from the top surface of the epitaxial layer into the epitaxial layer or the buried layer and not penetrating the buried layer, and the width of the third trench being smaller than the width of the second trench; A third trench isolation structure is disposed in the third trench, and the third trench isolation structure is configured to isolate the first trench structure from a device region in the epitaxial layer.

24. The semiconductor device according to claim 23, characterized in that The first trench structure includes a first conductive material having a second doping type, and the first conductive material is selected from polysilicon.

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