Wafer scale package structure and method of forming same

Abstract

The invention provides a wafer scale packaging structure and a forming method thereof, the wafer scale packaging structure comprises a plurality of discrete first chip modules mounted on the upper surface of a substrate, and the first chip modules are electrically connected with a first wiring layer; the first plastic package layer covers the first chip module and the upper surface of the substrate, and the first plastic package layer exposes the surface, away from the substrate, of the first chip module; the first heat dissipation plate is attached to the upper surface of the first plastic package layer; a plurality of discrete second chip modules mounted on the lower surface of the substrate, wherein the second chip modules are electrically connected with the second wiring layer; the second plastic package layer covers the second chip module and the lower surface of the substrate, and the second plastic package layer exposes the surface, away from the substrate, of the second chip module; and the second heat dissipation plate is attached to the lower surface of the second plastic package layer. The heat dissipation problem of the wafer scale packaging structure is improved, and the electrical performance of the wafer scale packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a wafer-scale packaging structure and a method for forming the same. Background Art

[0002] System in Package (SiP) integrates chips with various functions such as optoelectronics, digital / logic, radio frequency, storage, etc. into a package in the form of chip stacking or package stacking, thereby realizing a system that can realize multiple functions.

[0003] The demand for data computing in today's emerging fields (servers, mobile devices, artificial intelligence, automotive electronics, data storage, etc.) is growing exponentially. In order to meet the needs of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, the existing system-level packaging is expanding towards wafer scale, that is, integrating multiple semiconductor chips with different functions on a silicon wafer to form a wafer-scale system-level packaging structure. The heat dissipation problem of the existing wafer-scale packaging structure still needs to be improved, and its performance still needs to be enhanced. Summary of the invention

[0004] The problem to be solved by the present application is to provide a wafer-scale packaging structure and a method for forming the same, so as to improve the heat dissipation problem of the wafer-scale packaging structure and enhance the performance of the wafer-scale packaging structure.

[0005] To solve the above problems, the present application provides a wafer scale packaging structure, including: A substrate, the substrate comprising an upper surface and a lower surface opposite to each other, the upper surface having a first wiring layer, and the lower surface having a second wiring layer; A plurality of discrete first chip modules mounted on the upper surface of the substrate, wherein the first chip modules are electrically connected to the first wiring layer; a first plastic encapsulation layer covering the first chip module and the upper surface of the substrate, wherein the first plastic encapsulation layer exposes a surface of the first chip module away from the substrate; A first heat dissipation plate mounted on the upper surface of the first plastic sealing layer; A plurality of discrete second chip modules mounted on the lower surface of the substrate, wherein the second chip modules are electrically connected to the second wiring layer; a second plastic encapsulation layer covering the second chip module and the lower surface of the substrate, wherein the second plastic encapsulation layer exposes a surface of the second chip module away from the substrate; A second heat dissipation plate is mounted on the lower surface of the second plastic packaging layer.

[0006] In an optional embodiment, it further includes: an interface module, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module and the second chip module.

[0007] In an optional embodiment, the interface module includes an interface and a power component electrically connected to the interface, the interface is electrically connected to the external power supply end via a cable, and the power component is used to reduce the external voltage input through the interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module and the second chip module.

[0008] In an optional embodiment, the interface module is arranged outside the substrate, and the power component in the interface module is electrically connected to an external interface installed on the substrate through a connecting cable, and the external interface is electrically connected to the first wiring layer and the second wiring layer.

[0009] In an optional embodiment, there are one or more interface modules, the power component is embedded in the substrate, the interface is exposed outside the substrate, and the power component is also electrically connected to the first wiring layer and the second wiring layer.

[0010] In an optional embodiment, there are two interface modules, including a first interface module and a second interface module, the first interface module is used to supply power to the first chip module, the first interface module includes a first interface and a first power component electrically connected to the first interface, the first interface is electrically connected to the external power supply end through a first cable, the first power component is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module; the second interface module is used to supply power to the second chip module, the second interface module includes a second interface and a second power component electrically connected to the second interface, the second interface is electrically connected to the external power supply end through a second cable, the second power component is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding second chip module.

[0011] In an optional embodiment, the first power component and the second power component are embedded in the substrate, the first interface is exposed outside the upper surface of the substrate, and the second interface is exposed outside the lower surface of the substrate.

[0012] In an optional embodiment, each of the power components includes an electrically connected first part and multiple second parts, the first part is embedded in the substrate, the interface is electrically connected to the first part, and each of the second parts is located in the corresponding first chip module and second chip module.

[0013] In an optional embodiment, the first heat sink and the second heat sink are liquid-cooled heat sinks, the first heat sink has a first heat sink passage for the flow of refrigerant, and the second heat sink has a second heat sink passage for the flow of refrigerant.

[0014] In an optional embodiment, it also includes: a third heat sink mounted on the side of the wafer-scale packaging structure, the third heat sink is an integral structure with the first heat sink and the second heat sink, the third heat sink has a coolant inlet channel and a coolant outflow channel, the coolant inlet channel is connected to the inlet end of the first heat dissipation channel and the second heat dissipation channel respectively, and the coolant outflow channel is connected to the outlet end of the first heat dissipation channel and the second heat dissipation channel respectively.

[0015] In an optional embodiment, the first wiring layer includes a first passivation layer and a plurality of discrete first wirings located in the first passivation layer; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings located in the second passivation layer.

[0016] In an optional embodiment, the first wiring layer and the second wiring layer are electrically connected or not electrically connected; when the first wiring layer and the second wiring layer are electrically connected, the first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through a third wiring located in the substrate, thereby interconnecting the first chip module and the corresponding second chip module.

[0017] In an optional embodiment, the first chip module and the second chip module each have one or more semiconductor chips.

[0018] On the other hand, the present application also provides a method for forming a wafer scale packaging structure, comprising: Providing a substrate, the substrate comprising an upper surface and a lower surface opposite to each other, the upper surface being formed with a first wiring layer, and the lower surface being formed with a second wiring layer; Mounting a plurality of discrete first chip modules on the upper surface of the substrate, wherein the first chip modules are electrically connected to the first wiring layer; forming a first plastic encapsulation layer covering the first chip module and the upper surface of the substrate, wherein the first plastic encapsulation layer exposes a surface of the first chip module away from the substrate; Mounting a plurality of discrete second chip modules on the lower surface of the substrate, wherein the second chip modules are electrically connected to the second wiring layer; forming a second plastic encapsulation layer covering the second chip module and the lower surface of the substrate, wherein the second plastic encapsulation layer exposes a surface of the second chip module away from the substrate; Mounting a first heat sink on the upper surface of the first plastic packaging layer; A second heat sink is mounted on the lower surface of the second plastic packaging layer.

[0019] In an optional embodiment, it further includes: providing an interface module, wherein the interface module is electrically connected to an external power supply terminal and is used to at least supply power to the first chip module and the second chip module.

[0020] In an optional embodiment, the interface module includes an interface and a power component electrically connected to the interface, the interface is electrically connected to the external power supply end via a cable, and the power component is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module and the second chip module; before the first chip module is mounted on the surface of the substrate, the power component is embedded in the substrate, and the interface is exposed outside the substrate.

[0021] In an optional embodiment, there are two interface modules, including a first interface module and a second interface module, the first interface module is used to supply power to the first chip module, the first interface module includes a first interface and a first power component electrically connected to the first interface, the first interface is electrically connected to the external power supply end through a first cable, the first power component is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module; the second interface module is used to supply power to the second chip module, the second interface module includes a second interface and a second power component electrically connected to the second interface, the second interface is electrically connected to the external power supply end through a second cable, the second power component is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding second chip module.

[0022] In an optional embodiment, before mounting the first chip module on the upper surface of the substrate, the first power component and the second power component are respectively embedded in the substrate, the first interface is exposed outside the upper surface of the substrate, and the second interface is exposed outside the lower surface of the substrate.

[0023] In an optional embodiment, the first heat sink and the second heat sink are liquid-cooled heat sinks, the first heat sink has a first heat sink channel for the flow of refrigerant, and the second heat sink has a second heat sink channel for the flow of refrigerant; the first heat sink and the second heat sink are respectively attached to the upper surface of the first plastic sealing layer and the lower surface of the second plastic sealing layer by sealant.

[0024] In an optional embodiment, it also includes: a third heat sink mounted on the side of the wafer-scale packaging structure, the third heat sink is an integral structure with the first heat sink and the second heat sink, the third heat sink has a coolant inlet channel and a coolant outflow channel, the coolant inlet channel is connected to the inlet end of the first heat dissipation channel and the second heat dissipation channel respectively, and the coolant outflow channel is connected to the outlet end of the first heat dissipation channel and the second heat dissipation channel respectively.

[0025] The advantages of the technical solution of this application are: In the present application, several of the first chip modules and the second chip modules are respectively mounted on the upper surface and the lower surface of a substrate. The several first chip modules can operate independently (there is no interconnection between the first wiring layer and the second wiring layer) or can operate collaboratively (there is interconnection between the first wiring layer and the second wiring layer) to meet different packaging requirements. While improving the electrical performance of the wafer-scale packaging structure, the volume of the wafer-scale packaging structure can be reduced. The front and back sides of the wafer-scale packaging structure can be cooled by the first heat sink and the second heat sink at the same time, so that the heat generated by the first chip module and the second chip module can be quickly dissipated or released, thereby improving the heat dissipation problem of the wafer-scale packaging structure and further improving the electrical performance of the wafer-scale packaging structure.

[0026] Furthermore, in one embodiment, the wafer-scale packaging structure further includes: an interface module, the interface module is electrically connected to an external power supply terminal, and is used to supply power to at least the first chip module and the second chip module. The power supply problem of the wafer-scale packaging structure is solved by providing the interface module.

[0027] Further, in one embodiment, the interface module is two, including a first interface module and a second interface module, the first interface module is used to supply power to the first chip module, the first interface module includes a first interface and a first power component electrically connected to the first interface, the first interface is electrically connected to the external power supply end through a first cable, the first power component is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module; the second interface module is used to supply power to the second chip module, the second interface module includes a second interface and a second power component electrically connected to the second interface, the second interface is electrically connected to the external power supply end through a second cable, the second power component is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding second chip module. Improve the efficiency and speed of supplying power to a number of the first chip modules and a number of the second chip modules.

[0028] Furthermore, in one embodiment, each of the power components includes an electrically connected first part and a plurality of second parts, the first part is embedded in the substrate, the interface is electrically connected to the first part, and each of the second parts is located in the corresponding first chip module and the second chip module. The aforementioned integral power component is split into the first part and the second part, and the first part and the second part respectively implement different functions of the power component, thereby reducing the volume of the first part, which is conducive to embedding the first part in the substrate, and each second part can independently power the corresponding first chip module or the second chip module, thereby improving the speed and efficiency of power supply.

[0029] Further, in one embodiment, the first wiring layer is electrically connected to the second wiring layer or not; when the first wiring layer is electrically connected to the second wiring layer, the first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through a third wiring located in the substrate, thereby interconnecting the first chip module with the corresponding second chip module.

[0030] Furthermore, in one embodiment, it also includes: a third heat sink mounted on the side of the wafer-scale packaging structure, the third heat sink is an integral structure with the first heat sink and the second heat sink, the third heat sink has a coolant inlet channel and a coolant outlet channel, the coolant inlet channel is connected to the inlet end of the first heat dissipation channel and the second heat dissipation channel respectively, and the coolant outflow channel is connected to the outlet end of the first heat dissipation channel and the second heat dissipation channel respectively, while realizing the function of simultaneously dissipating heat on the front and back sides of the wafer-scale packaging structure, the first heat sink and the second heat sink can share a coolant inlet channel. The third heat sink is an integral structure with the first heat sink and the second heat sink, that is, the first heat sink, the third heat sink and the second heat sink are in a "U"-shaped structure as a whole, and most of the wafer-scale packaging structure is located in the opening of the "U"-shaped structure, so that the first heat sink and the second heat sink are pressed against the wafer-scale packaging structure from above and below the wafer-scale packaging structure, which is beneficial to prevent the wafer-scale packaging structure (especially the large-sized wafer-scale packaging structure) from warping or deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic structural diagram of a wafer scale packaging structure in one embodiment of the present application; Figure 2 A schematic structural diagram of a wafer scale packaging structure in another embodiment of the present application; Figure 3 A schematic structural diagram of a wafer scale packaging structure in another embodiment of the present application; Figure 4 A schematic structural diagram of a wafer scale packaging structure in another embodiment of the present application; Figure 5 A schematic structural diagram of a wafer scale packaging structure in another embodiment of the present application; Figure 6 A schematic structural diagram of a wafer scale packaging structure in another embodiment of the present application; Figure 7 A schematic structural diagram of a wafer-scale packaging structure in another embodiment of the present application. DETAILED DESCRIPTION

[0032] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0033] On the one hand, the present application first provides a wafer-scale packaging structure. The wafer-scale packaging structure of the present application is described in detail below with reference to the accompanying drawings.

[0034] An embodiment of the present application provides a wafer scale packaging structure, referring to Figure 1 The wafer scale packaging structure comprises: A substrate 101, wherein the substrate 101 comprises an upper surface and a lower surface opposite to each other, wherein the upper surface has a first wiring layer (not shown in the figure), and the lower surface has a second wiring layer (not shown in the figure); A plurality of discrete first chip modules 201 mounted on the upper surface of the substrate 101, wherein the first chip modules 201 are electrically connected to the first wiring layer; a first plastic encapsulation layer 102 covering the first chip module 201 and the upper surface of the substrate 101 , wherein the first plastic encapsulation layer 102 exposes the surface of the first chip module 201 away from the substrate 101 ; A first heat dissipation plate 401 mounted on the upper surface of the first plastic packaging layer 102; A plurality of discrete second chip modules 202 mounted on the lower surface of the substrate 101, wherein the second chip modules 202 are electrically connected to the second wiring layer; a second plastic encapsulation layer 103 covering the second chip module 202 and the lower surface of the substrate 101 , wherein the second plastic encapsulation layer 103 exposes a surface of the second chip module 202 away from the substrate 101 ; A second heat dissipation plate 402 is mounted on the lower surface of the second plastic packaging layer 103 .

[0035] Specifically, the substrate 101 is used as a support carrier and a connection carrier of a wafer scale packaging structure. In one embodiment, the substrate 101 may be a silicon substrate, an RDL substrate (Re-distribution Layer), a resin substrate, a printed circuit board (PCB), a ceramic substrate or a glass substrate. In one embodiment, the substrate may be a single-layer board or a multi-layer board.

[0036] The substrate 101 includes an upper surface and a lower surface relative to each other, the upper surface has a first wiring layer (not shown in the figure), and the lower surface has a second wiring layer (not shown in the figure), the first wiring layer is electrically connected to the first chip module 201, and the second wiring layer is electrically connected to the second chip module 202.

[0037] In one embodiment, the first wiring layer includes a first passivation layer and a plurality of discrete first wirings in the first passivation layer, and adjacent first chip modules 201 can be interconnected through part of the first wirings; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings in the second passivation layer, and adjacent second chip modules 202 can be interconnected through part of the first wirings. In one embodiment, the first wiring and the second wiring can include one or more of a metal layer, a connection plug, a through silicon via connection structure (TSV), a via connection structure, and a metal conductive column, and the first passivation layer and the second passivation layer can be an inorganic insulating material or an organic insulating material, and the inorganic insulating material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the inorganic insulating material can be a high molecular polymer, such as polyimide. In one embodiment, the first wiring and the second wiring can be a single layer or a stacked structure, and the corresponding first passivation layer and the second passivation layer can also be a single layer or a multi-layer stacked structure.

[0038] In one embodiment, the substrate 101 may have a larger size. When the substrate 101 is circular, the diameter of the substrate 101 may be 300 mm ± 10 mm, 450 ± 15 mm. When the substrate 101 is square, the diagonal size of the substrate 101 may be 300 mm ± 15 mm, 450 ± 20 mm.

[0039] In one embodiment, the first chip module 201 includes a front side and a back side opposite to each other, and the front side of the first chip module 201 has a plurality of first welding protrusions 203. When the first chip module 201 is mounted on the upper surface of the substrate 101, the front side of the first chip module 201 faces the upper surface of the substrate, and the first welding protrusions 203 on the front side of the first chip module 201 are welded together with the first wiring corresponding to the upper surface of the substrate 101. The second chip module 202 includes a front side and a back side opposite to each other, and the front side of the second chip module 202 has a plurality of second welding protrusions 204. When the second chip module 202 is mounted on the lower surface of the substrate 101, the front side of the second chip module 202 faces the lower surface of the substrate 101, and the second welding protrusions 204 on the front side of the second chip module 202 are welded together with the second wiring corresponding to the lower surface of the substrate 101.

[0040] The first chip module 201 and the second chip module 202 may be chip modules with the same or different functions. Several of the first chip modules 201 and the second chip modules 202 are mounted on the upper surface and the lower surface of a substrate 101, respectively. The several first chip modules 201 and the several chip modules 202 may operate independently (there is no interconnection between the first wiring layer and the second wiring layer) or may operate in coordination (there is interconnection between the first wiring layer and the second wiring layer) to meet different packaging requirements, and while improving the electrical performance of the wafer-scale packaging structure, the volume of the wafer-scale packaging structure can be reduced. In one embodiment, the first chip module 201 and the second chip module 202 each have one or more semiconductor chips. In one embodiment, when the first chip module 201 and the second chip module 202 each have multiple semiconductor chips, the functions of the multiple semiconductor chips are the same or different. In a specific embodiment, when the first chip module 201 and the second chip module 202 each have one or more semiconductor chips, the multiple semiconductor chips may include a logic chip and a storage chip electrically connected to the logic chip, the storage chip is used to store data, and the logic chip is used to control and manage the storage chip. The logic chip includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP) or other known electronic circuits used as processors, and the memory chip includes but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase-change memory (PRAM), and a resistive random access memory (RRAM).

[0041] The first plastic sealing layer 102 covers the first chip module 201 and the upper surface of the substrate 101, and the first plastic sealing layer 102 exposes the surface of the first chip module 201 away from the substrate 101, so as to facilitate mounting the first heat sink 401 on the upper surface of the first plastic sealing layer 102. The second plastic sealing layer 103 covers the second chip module 202 and the lower surface of the substrate 101, and the second plastic sealing layer 103 exposes the surface of the second chip module 202 away from the substrate 101, so as to facilitate mounting the second heat sink 402 on the lower surface of the second plastic sealing layer 103.

[0042] In one embodiment, the material of the first plastic encapsulation layer 102 and the second plastic encapsulation layer 103 may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing fillers; or may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing fillers. In some embodiments, the filler may be an inorganic filler or an organic filler.

[0043] The first heat sink 401 is used to dissipate or release the heat generated by the first chip modules 201, and the second heat sink 402 is used to dissipate or release the heat generated by the second chip modules 202, that is, the front and back sides of the wafer-scale packaging structure can be cooled by the first heat sink 401 and the second heat sink 402 at the same time, so that the heat generated by the first chip module 201 and the second chip module 202 can be quickly dissipated or released, thereby improving the heat dissipation problem of the wafer-scale packaging structure and further improving the electrical performance of the wafer-scale packaging structure. In one embodiment, the material of the first heat sink 401 and the second heat sink 402 is a material with high thermal conductivity, and the material with high thermal conductivity includes metal, such as copper, aluminum, gold, nickel, steel or stainless steel.

[0044] In one embodiment, the first heat sink 401 and the second heat sink 402 are liquid-cooled heat sinks, the first heat sink 401 has a first heat sink channel for the flow of refrigerant, and the second heat sink 402 has a second heat sink channel for the flow of refrigerant. When the refrigerant flows in the first heat sink channel and the second heat sink channel, it can quickly take away the heat in the first heat sink 401 and the second heat sink 402 to further improve the heat dissipation efficiency.

[0045] In one embodiment, the first heat sink 401 and the second heat sink 402 are respectively attached to the upper surface of the first plastic sealing layer 102 and the lower surface of the second plastic sealing layer 103 by means of sealant.

[0046] In one embodiment, continue to refer to Figure 1 The first heat sink 401 and the second heat sink 402 are independent heat sinks, which are respectively mounted on the upper surface of the first plastic sealing layer 102 and the lower surface of the second plastic sealing layer 103 .

[0047] In other embodiments, reference Figure 7 , further comprising: a third heat sink 403 mounted on the side of the wafer scale packaging structure portion, the third heat sink 403 is an integral structure with the first heat sink 401 and the second heat sink 402 (for edge distinction, Figure 7 The third heat sink 403 is divided by dotted lines), and has a coolant inlet channel and a coolant outflow channel. The coolant inlet channel is connected to the inlet ends of the first heat dissipation channel and the second heat dissipation channel respectively, and the coolant outflow channel is connected to the outlet ends of the first heat dissipation channel and the second heat dissipation channel respectively. While realizing the function of simultaneously dissipating heat from the front and back sides of the wafer-scale packaging structure, the first heat sink 401 and the second heat sink 402 can share a coolant inlet channel and a coolant outflow channel, thereby simplifying the interface setting during liquid cooling and reducing the risk of leakage. And cost is saved, and because the third heat sink 403 is an integrated structure with the first heat sink 401 and the second heat sink 402, that is, the first heat sink 401, the third heat sink 403 and the second heat sink 402 are in a "U" shape as a whole, and most of the wafer-scale packaging structure is located in the opening of the "U"-shaped structure, so that the first heat sink 401 and the second heat sink 402 are pressed against the wafer-scale packaging structure from above and below the wafer-scale packaging structure, which is beneficial to prevent the wafer-scale packaging structure (especially the large-sized wafer-scale packaging structure) from warping or deformation.

[0048] In one embodiment, continue to refer to Figure 1 The wafer-scale packaging structure further includes an interface module 301, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module 201 and the second chip module 202. The interface module 301 is provided to solve the power supply problem of the wafer-scale packaging structure.

[0049] In one embodiment, the interface module 301 includes an interface 303 and a power component 302 electrically connected to the interface 303, the interface 303 is electrically connected to the external power supply end through the cable 11, and the power component 302 is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface 303 to one voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module 201 and the second chip module 202. In a specific embodiment, the interface 303 and the power component 302 are an integrated structure packaged together. In other embodiments, the interface 303 and the power component 302 can also be separate structures, and the two are interconnected through wiring located in the substrate 101. Specifically, the interface 303 is mounted on the upper surface or lower surface of the edge area of ​​the substrate, and the power component 302 is embedded in the substrate 101. The power component 302 is electrically connected to the interface 303 through part of the first wiring in the first wiring layer and part of the second wiring in the second wiring layer.

[0050] In one embodiment, the interface module 301 can be used for data transmission in addition to power supply. The interface 303 includes various types of interfaces. In addition to being a power supply interface, the interface 303 can also be used as an input / output interface (I / O) for data transmission. The connection between the interface and the outside can be connected by wired and / or wireless means, the wired means include cables or data lines, and the wireless means include optical waves or electromagnetic waves.

[0051] In one embodiment, the external voltage supplied by the external power supply terminal may be greater than or equal to 48 V, 24 V-48 V or 5 V-24 V. The voltage reduced by the power component 302 may be 0.5 V-12 V, specifically 0.5 V, 0.7 V, 1 V, 1.8 V, 2 V, 2.5 V, 3 V, 3.5 V, 4 V, 5 V, 6 V, 7 V, 8 V, 9 V, 10 V, 11 V, 12 V.

[0052] In one embodiment, continue to refer to Figure 1 The interface module 301 is one, the interface 303 and the power component 302 are also one, one power component 302 is embedded in the substrate 101, and the interface 302 is exposed outside the substrate 101.

[0053] In one embodiment, the substrate 101 includes a middle area and an edge area surrounding the middle area, and the first plastic encapsulation layer 102 and the second plastic encapsulation layer 103 may expose part or all of the edge area, or may also cover the edge area. In one embodiment, the power component 302 may be embedded in the edge area of ​​the substrate 101. In another embodiment, the power component 302 may be embedded in the middle area of ​​the substrate 101.

[0054] In another embodiment, reference Figure 2 There is one interface module 301, there is one interface 303, one interface 303 is exposed outside the substrate 101, there are multiple power components 302, multiple power components 302 are electrically connected to one interface 303, and multiple power components 302 are embedded in the substrate 101. Specifically, multiple power components 302 can be embedded in the edge area or the middle area of ​​the substrate 101, and multiple power components 302 are electrically connected to the first wiring layer and the second wiring layer. One of the power components 302 can supply the reduced voltage to the corresponding one or more first chip modules 201, or to the corresponding one or more second chip modules 202. Figure 2 The number of the power components 302 is two, and the two power components 302 are embedded in the edge area of ​​the substrate 101 only as an example, which should not limit the protection scope of the present application.

[0055] In another embodiment, the interface module 301 may be multiple, specifically two or more, and each of the interface modules 301 may simultaneously power multiple first chip modules 201 or multiple second chip modules 202 to improve the efficiency and rate of power supply.

[0056] In yet another embodiment, reference Figure 3There are two interface modules, including a first interface module 301a and a second interface module 301b. The first interface module 301a is used to supply power to the first chip module 201. The first interface module 301a includes a first interface 303a and a first power component 302a electrically connected to the first interface 303a. The second power component 302a is embedded in the substrate 101 (specifically, it can be embedded in the edge area or the middle area of ​​the substrate 101). The first interface 303a is exposed outside the upper surface of the substrate 101. The first interface 303a is electrically connected to the external power supply end through the first cable 11a. The first power component 302a is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface 303a to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module 201. In a specific embodiment, there is one first interface 11a, and there may be one or more first power components 302a. When there are multiple first power components 302a, multiple first power components 302a are electrically connected to one first interface 11a, and each first power component 302a is used to supply the reduced voltage to the corresponding one or more first chip modules 201, so as to improve the efficiency and rate of supplying power to the multiple first chip modules 201, and improve the working stability and performance of the multiple first chip modules 201. The second interface module 301b is used to supply power to the second chip module 202, and the second interface module 301b includes a second interface 303b and a second power component 302b electrically connected to the second interface 303b, the second interface 303b is electrically connected to the external power supply terminal through a second cable 11b, and the second power component 302b is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface 303b to one voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module 202. In a specific embodiment, there is one second interface 11b, and there may be one or more second power components 302b. When there are multiple second power components 302b, multiple second power components 302b are electrically connected to one second interface 11b, and each second power component 302b is used to supply the reduced voltage to the corresponding one or more second chip modules 202, so as to improve the efficiency and rate of power supply to the multiple second chip modules 202, and improve the working stability and performance of the multiple second chip modules 202.

[0057] In another embodiment, each of the power components includes an electrically connected first part and multiple second parts, the first part is embedded in the substrate 101, the interface 303 is electrically connected to the first part, and each of the second parts is located in the corresponding first chip module and the second chip module, and the aforementioned integral power component is split into the first part and the second part, and the first part and the second part respectively implement different functions of the power component, so that the volume of the first part can be reduced, which is conducive to the embedding of the first part in the substrate 101, and each second part can independently supply power to the corresponding first chip module 201 or the second chip module 202, thereby improving the speed and efficiency of power supply. In a specific embodiment, the first part is used to reduce the external voltage input by the interface 303 to an initial voltage, and the initial voltage is less than the external voltage. The second part is used to reduce the initial voltage to a terminal voltage, and the terminal voltage is less than the initial voltage. The terminal voltage is supplied to the corresponding first chip module 201 and the second chip module 202. Specifically, refer to Figure 4 The first interface module 301a includes a first interface 303a electrically connected to a first power component, the first power component includes a first part 302a1 and a plurality of second parts 302a2 electrically connected to the first part 302a1, the first part 302a1 of the first power component is embedded in the substrate 101, and each of the second parts 302a2 of the first power component is located in a corresponding first chip module 201. The second interface module 301b includes a second interface 303b electrically connected to a second power component, the second power component includes a first part 302b1 and a plurality of second parts 302b2 electrically connected to the first part 302b1, the first part 302b1 of the second power component is embedded in the substrate 101, and each of the second parts 302b2 of the second power component is located in a corresponding second chip module 202.

[0058] In one embodiment, there is no interconnection or electrical connection between the first wiring in the first wiring layer and the second wiring in the second wiring layer, that is, there is no communication and / or data transmission between the first chip module 201 on the upper surface of the substrate 101 and the second chip module 202 on the lower surface of the substrate 101, and they operate independently.

[0059] In another embodiment, reference Figure 5, the first wiring in the first wiring layer is interconnected or electrically connected with the second wiring in the second wiring layer, and the first wiring in the first wiring layer is electrically connected with the corresponding second wiring in the second wiring layer through the third wiring 104 located in the substrate 101, so that the first chip module 201 is interconnected with the corresponding second chip module 202, so that the first chip module 201 on the upper surface of the substrate 101 and the second chip module 202 on the lower surface of the substrate 101 can communicate and / or transmit data, that is, the first chip module 201 and the second chip module 202 can operate simultaneously, which greatly improves the performance of the wafer-scale packaging structure (such as improving computing power, etc.).

[0060] In yet another embodiment, reference Figure 6 An external interface 304 is installed on the upper surface of the substrate 101, and the external interface 304 is electrically connected to the corresponding first chip module 201 and the second chip module 202 through the first wiring layer and the second wiring layer. The interface module 301 is arranged outside the substrate 101, and the interface 303 in the interface module 301 is electrically connected to the external power supply end through the cable 11. The power component 303 in the interface module 301 is electrically connected to the external interface 304 through the connecting cable 305. The power component 302 reduces the external voltage input through the interface 303 to one voltage or multiple voltages of different sizes, and transmits the reduced voltage to the external interface 304 through the connecting cable 305. The external interface 304 supplies the reduced voltage to the corresponding first chip module 201 and the second chip module 202 through the first wiring layer and the second wiring layer.

[0061] It should be noted that the same or similar parts in the aforementioned embodiments of the present application are not repeated in each embodiment, and can be referenced or referred to each other.

[0062] The present application also provides a method for forming a wafer scale packaging structure. In one embodiment, reference Figure 1 , the forming method comprises: Providing a substrate 101, the substrate 101 includes an upper surface and a lower surface opposite to each other, the upper surface is formed with a first wiring layer (not shown in the figure), and the lower surface is formed with a second wiring layer (not shown in the figure); A plurality of discrete first chip modules 201 are mounted on the surface of the substrate 101, and the first chip modules 201 are electrically connected to the first wiring layer; forming a first plastic encapsulation layer 102 covering the first chip module 201 and the upper surface of the substrate 101 , wherein the first plastic encapsulation layer 102 exposes the surface of the first chip module 201 away from the substrate 101 ; A plurality of discrete second chip modules 202 are mounted on the lower surface of the substrate 101, and the second chip modules 202 are electrically connected to the second wiring layer; forming a second plastic encapsulation layer 103 covering the second chip module 202 and the lower surface of the substrate 101, wherein the second plastic encapsulation layer 103 exposes a surface of the second chip module away from the substrate; A first heat sink 401 is mounted on the upper surface of the first plastic packaging layer 102; A second heat sink 402 is mounted on the lower surface of the second plastic packaging layer 103 .

[0063] In one embodiment, it further includes: providing an interface module 301 , wherein the interface module 301 is electrically connected to an external power supply terminal and is at least used to supply power to the first chip module 201 and the second chip module 202 .

[0064] In one embodiment, the interface module 301 includes an interface 303 and a power component 302 electrically connected to the interface 303, the interface 303 is electrically connected to the external power supply end through a cable 11, and the power component 302 is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module 201 and the second chip module 202; before the first chip module 201 is mounted on the surface of the substrate 101, the power component 302 is embedded in the substrate 101, and the interface 303 is exposed outside the substrate 101.

[0065] In one embodiment, there are one or more interface modules.

[0066] In one embodiment, there are two interface modules, see Figure 3, including a first interface module 301a and a second interface module 301b. The first interface module 301a is used to supply power to the first chip module 201, the first interface module 301a includes a first interface 303a and a first power component 302a electrically connected to the first interface 303a, the second power component 302a is embedded in the substrate 101 (specifically, it can be embedded in the edge area or the middle area of ​​the substrate 101), the first interface 303a is exposed outside the upper surface of the substrate 101, the first interface 303a is electrically connected to the external power supply end through the first cable 11a, the first power component 302a is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface 303a to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module 201. In a specific embodiment, there is one first interface 11a, and there may be one or more first power components 302a. When there are multiple first power components 302a, multiple first power components 302a are electrically connected to one first interface 11a, and each first power component 302a is used to supply the reduced voltage to the corresponding one or more first chip modules 201, so as to improve the efficiency and rate of supplying power to the multiple first chip modules 201, and improve the working stability and performance of the multiple first chip modules 201. The second interface module 301b is used to supply power to the second chip module 202, and the second interface module 301b includes a second interface 303b and a second power component 302b electrically connected to the second interface 303b, the second interface 303b is electrically connected to the external power supply terminal through a second cable 11b, and the second power component 302b is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface 303b to one voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module 202. In a specific embodiment, there is one second interface 11b, and there may be one or more second power components 302b. When there are multiple second power components 302b, multiple second power components 302b are electrically connected to one second interface 11b, and each second power component 302b is used to supply the reduced voltage to the corresponding one or more second chip modules 202, so as to improve the efficiency and rate of power supply to the multiple second chip modules 202, and improve the working stability and performance of the multiple second chip modules 202.

[0067] In one embodiment, before mounting the first chip module 201 on the upper surface of the substrate, the first power component 302a and the second power component 302b are respectively embedded in the substrate 101, the first interface 303a is exposed outside the upper surface of the substrate 101, and the second interface 303b is exposed outside the lower surface of the substrate 101.

[0068] In one embodiment, the first heat sink 401 and the second heat sink 402 are liquid-cooled heat sinks, the first heat sink 401 has a first heat dissipation channel for the flow of refrigerant, and the second heat sink 402 has a second heat dissipation channel for the flow of refrigerant; the first heat sink 401 and the second heat sink 402 are respectively attached to the upper surface of the first plastic sealing layer 102 and the lower surface of the second plastic sealing layer 103 by sealant.

[0069] In one embodiment, reference Figure 7 , also includes: a third heat sink 403 mounted on the side of the wafer-scale packaging structure part, the third heat sink 403 is an integrated structure with the first heat sink 401 and the second heat sink 402, the first heat sink 401, the second heat sink 402 and the third heat sink 403 are mounted at the same time, and the third heat sink 403 has a coolant inlet channel and a coolant outflow channel, the coolant inlet channel is respectively connected to the inlet end of the first heat dissipation channel and the second heat dissipation channel, and the coolant outflow channel is respectively connected to the outlet end of the first heat dissipation channel and the second heat dissipation channel.

[0070] It should be noted that the parts in this embodiment (formation method of wafer-scale packaging structure) that are the same or similar to those in the aforementioned embodiment (wafer-scale packaging structure) are no longer repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiment for details.

[0071] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A wafer scale packaging structure, characterized in that: include: A substrate, the substrate comprising an upper surface and a lower surface opposite to each other, the upper surface having a first wiring layer, and the lower surface having a second wiring layer; A plurality of discrete first chip modules mounted on the upper surface of the substrate, wherein the first chip modules are electrically connected to the first wiring layer; a first plastic encapsulation layer covering the first chip module and the upper surface of the substrate, wherein the first plastic encapsulation layer exposes a surface of the first chip module away from the substrate; A first heat dissipation plate mounted on the upper surface of the first plastic sealing layer; A plurality of discrete second chip modules mounted on the lower surface of the substrate, wherein the second chip modules are electrically connected to the second wiring layer; a second plastic encapsulation layer covering the second chip module and the lower surface of the substrate, wherein the second plastic encapsulation layer exposes a surface of the second chip module away from the substrate; A second heat dissipation plate is mounted on the lower surface of the second plastic packaging layer.

2. The wafer scale packaging structure according to claim 1, characterized in that: Also includes: An interface module, the interface module is electrically connected to an external power supply terminal and is at least used to supply power to the first chip module and the second chip module.

3. The wafer scale packaging structure according to claim 2, wherein: The interface module includes an interface and a power component electrically connected to the interface, the interface is electrically connected to the external power supply end via a cable, and the power component is used to reduce the external voltage input through the interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module and the second chip module.

4. The wafer scale packaging structure according to claim 3, characterized in that: The interface module is arranged outside the substrate, and the power component in the interface module is electrically connected to an external interface installed on the substrate through a connecting cable, and the external interface is electrically connected to the first wiring layer and the second wiring layer.

5. The wafer scale packaging structure according to claim 3, characterized in that: There are one or more interface modules, the power component is embedded in the substrate, the interface is exposed outside the substrate, and the power component is also electrically connected to the first wiring layer and the second wiring layer.

6. The wafer scale packaging structure according to claim 5, characterized in that: There are two interface modules, including a first interface module and a second interface module, the first interface module is used to supply power to the first chip module, the first interface module includes a first interface and a first power component electrically connected to the first interface, the first interface is electrically connected to the external power supply end through a first cable, the first power component is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module; The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply end through a second cable. The second power component is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding second chip module.

7. The wafer scale packaging structure according to claim 6, characterized in that: The first power component and the second power component are embedded in the substrate, the first interface is exposed outside the upper surface of the substrate, and the second interface is exposed outside the lower surface of the substrate.

8. The wafer scale packaging structure according to claim 5 or 6, characterized in that: Each of the power components includes an electrically connected first part and a plurality of second parts, the first part is embedded in the substrate, the interface is electrically connected to the first part, and each of the second parts is located in a corresponding first chip module and a second chip module.

9. The wafer scale packaging structure according to claim 1, wherein: The first heat sink and the second heat sink are liquid-cooled heat sinks. The first heat sink has a first heat sink passage for the flow of refrigerant, and the second heat sink has a second heat sink passage for the flow of refrigerant.

10. The wafer scale packaging structure according to claim 9, wherein: Also includes: A third heat sink mounted on the side of the wafer-scale packaging structure portion, the third heat sink is an integral structure with the first heat sink and the second heat sink, the third heat sink has a coolant inlet channel and a coolant outflow channel, the coolant inlet channel is respectively connected to the inlet ends of the first heat dissipation channel and the second heat dissipation channel, and the coolant outflow channel is respectively connected to the outlet ends of the first heat dissipation channel and the second heat dissipation channel.

11. The wafer scale packaging structure according to claim 1, wherein: The first wiring layer includes a first passivation layer and a plurality of discrete first wirings located in the first passivation layer; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings located in the second passivation layer.

12. The wafer scale packaging structure according to claim 11, wherein: The first wiring layer is electrically connected to the second wiring layer or not; when the first wiring layer is electrically connected to the second wiring layer, the first wiring in the first wiring layer is electrically connected to the corresponding second wiring in the second wiring layer through the third wiring located in the substrate, thereby interconnecting the first chip module with the corresponding second chip module.

13. The wafer scale packaging structure according to claim 12, wherein: The first chip module and the second chip module each have one or more semiconductor chips.

14. A method for forming a wafer scale packaging structure, characterized in that: include: Providing a substrate, the substrate comprising an upper surface and a lower surface opposite to each other, the upper surface being formed with a first wiring layer, and the lower surface being formed with a second wiring layer; Mounting a plurality of discrete first chip modules on the upper surface of the substrate, wherein the first chip modules are electrically connected to the first wiring layer; forming a first plastic encapsulation layer covering the first chip module and the upper surface of the substrate, wherein the first plastic encapsulation layer exposes a surface of the first chip module away from the substrate; Mounting a plurality of discrete second chip modules on the lower surface of the substrate, wherein the second chip modules are electrically connected to the second wiring layer; forming a second plastic encapsulation layer covering the second chip module and the lower surface of the substrate, wherein the second plastic encapsulation layer exposes a surface of the second chip module away from the substrate; Mounting a first heat sink on the upper surface of the first plastic packaging layer; A second heat sink is mounted on the lower surface of the second plastic packaging layer.

15. The method for forming a wafer scale packaging structure according to claim 14, wherein: Also includes: An interface module is provided, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module and the second chip module.

16. The method for forming a wafer scale packaging structure according to claim 15, wherein: The interface module includes an interface and a power component electrically connected to the interface, the interface is electrically connected to the external power supply end through a cable, and the power component is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module and the second chip module; before the first chip module is mounted on the surface of the substrate, the power component is embedded in the substrate, and the interface is exposed outside the substrate.

17. The method for forming a wafer scale packaging structure according to claim 16, wherein: There are two interface modules, including a first interface module and a second interface module, the first interface module is used to supply power to the first chip module, the first interface module includes a first interface and a first power component electrically connected to the first interface, the first interface is electrically connected to the external power supply end through a first cable, the first power component is also electrically connected to the first wiring layer, and is used to reduce the external voltage input through the first interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding first chip module; The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply end through a second cable. The second power component is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface to one voltage or multiple voltages of different sizes, and supply the reduced voltage to the corresponding second chip module.

18. The method for forming a wafer scale packaging structure according to claim 17, wherein: Before mounting the first chip module on the upper surface of the substrate, the first power component and the second power component are respectively embedded in the substrate, the first interface is exposed outside the upper surface of the substrate, and the second interface is exposed outside the lower surface of the substrate.

19. The method for forming a wafer scale packaging structure according to claim 14, wherein: The first heat sink and the second heat sink are liquid-cooled heat sinks, the first heat sink has a first heat sink passage for the flow of refrigerant, and the second heat sink has a second heat sink passage for the flow of refrigerant; the first heat sink and the second heat sink are respectively attached to the upper surface of the first plastic sealing layer and the lower surface of the second plastic sealing layer by sealant.

20. The method for forming a wafer scale packaging structure according to claim 19, wherein: Also includes: A third heat sink mounted on the side of the wafer-scale packaging structure portion, the third heat sink is an integral structure with the first heat sink and the second heat sink, the third heat sink has a coolant inlet channel and a coolant outflow channel, the coolant inlet channel is respectively connected to the inlet ends of the first heat dissipation channel and the second heat dissipation channel, and the coolant outflow channel is respectively connected to the outlet ends of the first heat dissipation channel and the second heat dissipation channel.

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