Double-sided heat dissipation power module with plane mosaic structure

Abstract

The invention relates to a double-sided heat dissipation power module with a plane mosaic structure. The double-sided heat dissipation power module comprises a first substrate with a first conductive metal layer, a second substrate with a second conductive metal layer and a plurality of power chips, the first conductive metal layer comprises an AC conductive metal layer and a plurality of upper DC-conductive metal layers; the second conductive metal layer comprises a DC + conductive metal layer and a plurality of lower DC-conductive metal layers; the plurality of power chips comprise a plurality of upper tube power chips and a plurality of lower tube power chips; the plurality of lower tube power chips are arranged on the AC conductive metal layer, are staggered with the plurality of upper tube power chips, and are connected with the plurality of lower DC-conductive metal layers in a one-to-one correspondence manner; an independent power loop exists between each upper tube power chip and the adjacent lower tube power chip, and mutual inductance of the two opposite power loops is offset in the vertical direction and the horizontal direction. According to the power module, the mutual inductance offset effect is improved by increasing the number of current paths.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power modules, and in particular relates to a double-sided heat dissipation power module with a planar mosaic structure. Background Art

[0002] Power devices are the core devices for power conversion. Compared with silicon devices, silicon carbide devices have low leakage current, high withstand voltage, high operating temperature, strong radiation resistance, and high switching speed. Compared with Si devices of the same voltage level, they have lower on-resistance, good heat dissipation characteristics, and a high theoretical maximum operating temperature. In order to meet high-power applications, high-current silicon carbide devices are required. Silicon carbide power modules often connect multiple silicon carbide power chips in parallel, but there are large parasitic parameters, such as parasitic inductance. Due to the high switching speed characteristics of silicon carbide power chips, the parasitic parameters caused by the package may cause greater switching losses, voltage stress, and EMI noise. In addition, the imbalance of the package parasitic inductance may cause electrothermal stress and unbalanced power loss, resulting in local overheating and uneven aging of parallel devices, which is not conducive to the normal operation of parallel devices.

[0003] Therefore, it is necessary to reduce the package parasitic inductance inside the silicon carbide power chip module and optimize the heat dissipation path. Traditional module design ideas, such as copper interconnect technology, flip-chip technology, and dual-terminal technology, reduce self-inductance by shortening the loop path, or use the current reversal in adjacent paths to achieve mutual inductance cancellation, thereby reducing the parasitic inductance inside the power module. However, due to the limitations of module layout and component location, these methods can only achieve mutual inductance reduction on some paths. In traditional power modules, parallel upper tube chips and parallel lower tube chips usually share a power loop. This design limits the realization of mutual inductance cancellation, and cannot fully utilize mutual inductance cancellation to minimize parasitic inductance, making it difficult to further reduce parasitic inductance, thereby limiting the improvement of module performance. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a double-sided heat dissipation power module with a planar mosaic structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] An embodiment of the present invention provides a double-sided heat dissipation power module with a planar mosaic structure, comprising: a first substrate with a first conductive metal layer, a second substrate with a second conductive metal layer, and a plurality of power chips, wherein the first conductive metal layer and the second conductive metal layer are parallel and opposite to each other, wherein:

[0006] The first conductive metal layer includes an AC conductive metal layer and a plurality of upper DC-conductive metal layers, wherein the plurality of upper DC-conductive metal layers are embedded in the AC conductive metal layer;

[0007] The second conductive metal layer includes a DC+ conductive metal layer and a plurality of lower DC- conductive metal layers; the opposite sides of the DC+ conductive metal layer form a square sawtooth structure, and the plurality of sawtooths of the square sawtooth structure are arranged in a staggered manner; the plurality of lower DC- conductive metal layers are arranged in a one-to-one correspondence in the plurality of grooves of the square sawtooth structure, and two diagonally adjacent lower DC- conductive metal layers are connected through the upper DC- conductive metal layer, and / or two diagonally adjacent lower DC- conductive metal layers are connected through a metal clip;

[0008] The plurality of power chips include a plurality of upper tube power chips and a plurality of lower tube power chips; the plurality of upper tube power chips are arranged on the plurality of saw teeth of the square sawtooth structure in a one-to-one correspondence and connected to the AC conductive metal layer; the plurality of lower tube power chips are arranged on the AC conductive metal layer, staggered with the plurality of upper tube power chips, and connected to the plurality of lower DC-conductive metal layers in a one-to-one correspondence;

[0009] An independent power loop exists between each of the upper tube power chips and the adjacent lower tube power chip, and the two power loops are mutually inducted in both the vertical and horizontal directions.

[0010] In one embodiment of the present invention, the first substrate further comprises a first insulating layer and a first heat dissipation metal layer, wherein the first conductive metal layer, the first insulating layer and the first heat dissipation metal layer are stacked in sequence;

[0011] The second substrate further includes a second insulating layer and a second heat dissipation metal layer, wherein the second conductive metal layer, the second insulating layer and the second heat dissipation metal layer are stacked in sequence;

[0012] The first heat dissipation metal layer and the second heat dissipation metal layer are used to set an external heat sink.

[0013] In one embodiment of the present invention, the AC conductive metal layer is provided with a first AC terminal and a second AC terminal on opposite sides;

[0014] Each sawtooth of the DC+ conductive metal layer is connected to a DC+ terminal;

[0015] Each of the lower DC-conductive metal layers is connected with a DC-terminal.

[0016] In one embodiment of the present invention, it further comprises a plurality of metal blocks, wherein:

[0017] Each of the upper tube power chips is connected to the AC conductive metal layer through the metal block;

[0018] Each of the lower tube power chips is connected to the corresponding lower DC-conductive metal layer through the metal block;

[0019] The two diagonally adjacent lower DC-conductive metal layers are connected to the upper DC-conductive metal layer through the metal block.

[0020] In one embodiment of the present invention, the power chip comprises a silicon carbide MOSFET power chip, and the silicon carbide MOSFET power chip comprises a gate, a power source, a Kelvin source and a drain, wherein:

[0021] The power source electrode, the Kelvin source electrode, and the gate electrode are all arranged on a first side surface of the silicon carbide MOSFET power chip;

[0022] The drain electrode is arranged on a second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface;

[0023] The drain electrode of the upper tube power chip is arranged on the surface of the DC+ conductive metal layer, and the power source electrode is connected to the AC conductive metal layer;

[0024] The drain electrode of the lower tube power chip is arranged on the surface of the AC conductive metal layer, and the power source electrode is connected to the corresponding lower DC-conductive metal layer.

[0025] In one embodiment of the present invention, a Kelvin source terminal and a gate terminal are provided near each power chip as the conductive metal layer driving terminal, and the Kelvin source terminal and the gate terminal are close to each other and are provided on the insulating layer of the substrate;

[0026] The Kelvin source terminal is connected to the Kelvin source, and the gate terminal is connected to the gate.

[0027] In one embodiment of the present invention, the first conductive metal layer comprises an AC conductive metal layer, a first DC-conductive metal layer and a second DC-conductive metal layer, wherein the first DC-conductive metal layer and the second DC-conductive metal layer are embedded in the AC conductive metal layer;

[0028] The second conductive metal layer includes a DC+ conductive metal layer, a third DC- conductive metal layer, a fourth DC- conductive metal layer, a fifth DC- conductive metal layer and a sixth DC- conductive metal layer, wherein the opposite sides of the DC+ conductive metal layer form a square sawtooth structure with four sawtooths, and the four sawtooths are staggered, the third DC- conductive metal layer, the fourth DC- conductive metal layer, the fifth DC- conductive metal layer and the sixth DC- conductive metal layer are distributed in grooves opposite to each sawtooth, the third DC- conductive metal layer is diagonally arranged with the fourth DC- conductive metal layer and connected to each other through the first DC- conductive metal layer, the fourth DC- conductive metal layer is diagonally arranged with the fifth DC- conductive metal layer and connected to each other through a copper clip, and the fifth DC- conductive metal layer is diagonally arranged with the sixth DC- conductive metal layer and connected to each other through the second DC- conductive metal layer.

[0029] In one embodiment of the present invention, the plurality of upper tube power chips include: a first upper tube power chip, a second upper tube power chip, a third upper tube power chip and a fourth upper tube power chip, wherein the first upper tube power chip, the second upper tube power chip, the third upper tube power chip and the fourth upper tube power chip are arranged on the four sawtooths of the square sawtooth structure in a one-to-one correspondence, and are all connected to the AC conductive metal layer;

[0030] The plurality of down tube power chips include: a first down tube power chip, a second down tube power chip, a third down tube power chip and a fourth down tube power chip, wherein the first down tube power chip, the second down tube power chip, the third down tube power chip and the fourth down tube power chip are distributed on the AC conductive metal layer, and correspond to the third DC-conductive metal layer, the fourth DC-conductive metal layer, the fifth DC-conductive metal layer and the sixth DC-conductive metal layer, respectively.

[0031] In one embodiment of the present invention, a first power loop is formed between the first upper tube power chip, the first lower tube power chip, and the third DC-conductive metal layer; a second power loop is formed between the first upper tube power chip, the second lower tube power chip, and the fourth DC-conductive metal layer;

[0032] A third power loop is formed between the second upper tube power chip, the first lower tube power chip and the third DC-conductive metal layer; a fourth power loop is formed between the second upper tube power chip, the second lower tube power chip and the fourth DC-conductive metal layer; a fifth power loop is formed between the second upper tube power chip, the third lower tube power chip and the fifth DC-conductive metal layer;

[0033] A sixth power loop is formed between the third upper tube power chip, the second lower tube power chip and the fourth DC-conductive metal layer; a seventh power loop is formed between the third upper tube power chip, the third lower tube power chip and the fifth DC-conductive metal layer; an eighth power loop is formed between the third upper tube power chip, the fourth lower tube power chip and the sixth DC-conductive metal layer;

[0034] A ninth power loop is formed between the fourth upper tube power chip, the third lower tube power chip and the fifth DC-conductive metal layer; a tenth power loop is formed between the fourth upper tube power chip, the fourth lower tube power chip and the sixth DC-conductive metal layer;

[0035] The mutual inductance between the first power circuit and the fourth power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the fourth power circuit and the seventh power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the seventh power circuit and the tenth power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the second power circuit and the third power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the fifth power circuit and the sixth power circuit cancels out in the vertical and horizontal directions, and the mutual inductance between the eighth power circuit and the ninth power circuit cancels out in the vertical and horizontal directions.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The double-sided heat dissipation power module of the planar mosaic structure of the present invention is designed with an AC conductive metal layer, a DC+ conductive metal layer, a lower DC- conductive metal layer, and a plurality of upper tube power chips and a plurality of lower tube power chips, so that each power chip in the module has multiple power circuits, and there is an independent power circuit between each upper tube power chip and the adjacent lower tube power chip, and the mutual inductance of the two power circuits in the vertical direction and the horizontal direction are offset. By increasing the number of power circuits, the current can flow from the parallel upper tube chip through any adjacent parallel lower tube chip to form a commutation circuit, thereby increasing the number of current paths; based on the principle of magnetic flux cancellation, the current directions of the relative commutation circuits in the vertical and horizontal directions are opposite, thereby achieving mutual inductance cancellation, reducing the parasitic inductance inside the module, and effectively reducing the switching loss and electrical stress generated by the power module during high-speed switching;

[0038] 2. The power module of the present invention can effectively avoid the current concentration phenomenon in some chips and local areas inside the module by increasing the number of power loops and optimizing the current path. This design can balance the heat distribution and avoid excessive temperature of the module, thereby improving the performance and reliability of the module; uniform current distribution helps to reduce the formation of hot spots inside the module, reduce the thermomechanical stress of the module, and extend the service life of the module;

[0039] 3. The power module of the present invention alternately places the upper tube power chip and the lower tube power chip to optimize the heat dissipation path, avoid local overheating, ensure uniform heat distribution and efficient heat conduction, and reduce thermal coupling between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the overall structure of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention;

[0041] Figure 2 A front view of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention;

[0042] Figure 3 A side view of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention;

[0043] Figure 4 A first substrate layout diagram provided in an embodiment of the present invention, Figure 5 A second substrate layout diagram provided in an embodiment of the present invention;

[0044] Figure 6 A schematic diagram of a connection method between a first substrate, a second substrate and a power chip provided in an embodiment of the present invention;

[0045] Figure 7 A connection diagram of a DC+conductive metal layer provided in an embodiment of the present invention;

[0046] Figure 8 A connection diagram of an AC conductive metal layer provided by an embodiment of the present invention;

[0047] Fig. 9 A connection diagram of a DC-conductive metal layer provided in an embodiment of the present invention;

[0048] Fig.10 A schematic diagram of a power circuit of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention;

[0049] Fig.11 A schematic diagram of the structure of a power chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0051] Embodiment 1

[0052] In order to reduce the internal parasitic inductance of the silicon carbide power chip module, this embodiment provides a double-sided heat dissipation power module with a planar mosaic structure, which is suitable for a high-current power module with multiple power chips in parallel. There is an independent power loop between each upper tube chip and its nearest adjacent lower tube chip, and the mutual inductance cancellation effect is improved by increasing the number of current paths.

[0053] See also Figure 1-Figure 10 , Figure 1 The overall structural diagram of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention is as follows: Figure 2 A front view of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention, Figure 3 A side view of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention, Figure 4 A first substrate layout diagram provided in an embodiment of the present invention, Figure 5 A second substrate layout diagram provided in an embodiment of the present invention, Figure 6 A schematic diagram of a connection method between a first substrate, a second substrate and a power chip provided in an embodiment of the present invention, Figure 7 A connection diagram of a DC+conductive metal layer provided in an embodiment of the present invention, Figure 8 A connection diagram of an AC conductive metal layer provided in an embodiment of the present invention, Fig. 9 A connection diagram of a DC-conductive metal layer provided in an embodiment of the present invention, Fig.10 A schematic diagram of a power circuit of a double-sided heat dissipation power module with a planar mosaic structure provided by an embodiment of the present invention.

[0054] Please combine Figure 1 , Figure 2 and Figure 3 The double-sided heat dissipation power module with a planar mosaic structure provided in this embodiment includes: a first substrate 100 with a first conductive metal layer 101, a second substrate 200 with a second conductive metal layer 201 and a plurality of power chips 701 to 708, wherein the first conductive metal layer 101 and the second conductive metal layer 201 are parallel to each other.

[0055] Please combine Figure 4 and Figure 8 The first conductive metal layer 101 includes an AC conductive metal layer 301 and a plurality of upper DC conductive metal layers 302 ˜ 303 . The plurality of upper DC conductive metal layers 302 ˜ 303 are embedded in the AC conductive metal layer 301 .

[0056] Please combine Figure 5 , Figure 7 and Fig. 9The second conductive metal layer 201 includes a DC+ conductive metal layer 501 and a plurality of lower DC- conductive metal layers 502 to 505. The opposite sides of the DC+ conductive metal layer 501 form a square sawtooth structure, and the sawtooth structures are staggered; the plurality of lower DC- conductive metal layers 502 to 505 are distributed in a plurality of grooves of the square sawtooth structure in a one-to-one correspondence, and two diagonally adjacent lower DC- conductive metal layers are connected through an upper DC- conductive metal layer, and / or two diagonally adjacent lower DC- conductive metal layers are connected through a metal clip.

[0057] Please combine Figure 4 , Figure 5 , Figure 6 and Fig.10 , the plurality of power chips include a plurality of upper power chips 701-704 and a plurality of lower power chips 705-708. The plurality of upper power chips 701-704 are arranged one by one on the plurality of saw teeth of the square sawtooth structure and are connected to the AC conductive metal layer 301; the plurality of lower power chips 705-708 are arranged on the AC conductive metal layer 301, staggered with the plurality of upper power chips 701-704, and are connected one by one to the plurality of lower DC-conductive metal layers 502-505. There is an independent power loop between each upper power chip and the adjacent lower power chip, and the mutual inductance of the two power loops is offset in the vertical and horizontal directions.

[0058] Specifically, the first substrate 100 is an upper direct copper-clad ceramic substrate, and the second substrate 200 is a lower direct copper-clad ceramic substrate. The two substrates are arranged parallel to each other, and the power chip is arranged between the inner surfaces of the two substrates. The AC conductive metal layer 301 and several upper DC-conductive metal layers 302~303 form the first conductive metal layer 101 and serve as the upper conductive metal layer, and the DC+ conductive metal layer 501 and several lower DC-conductive metal layers 502~505 form the second conductive metal layer 102 and serve as the lower conductive metal layer. Several lower DC-conductive metal layers are diagonally adjacent, and the diagonally adjacent lower DC-conductive metal layers can be connected through the upper DC-conductive metal layer, or through metal clips, such as copper clips. Exemplarily, the diagonally adjacent lower DC-conductive metal layers located on both sides are connected through the upper DC-conductive metal layer, and the diagonally adjacent lower DC-conductive metal layers located in the middle are connected through metal clips, such as Figure 5 As shown; alternatively, multiple pairs of diagonally adjacent lower DC-conductive metal layers are connected via an upper DC-conductive metal layer.

[0059] The two opposite sides of the DC+ conductive metal layer 501 form a square sawtooth structure, which includes sawtooth and groove. For any side of the DC+ conductive metal layer 501, the sawtooth and groove are alternately distributed in sequence, and are staggered with the sawtooth and groove of the other side, and a lower DC-conductive metal layer is correspondingly arranged in each groove. An upper tube power chip is correspondingly arranged on each sawtooth, and a lower tube power chip is arranged at a position corresponding to the AC conductive metal layer 301 and the lower DC-conductive metal layer, so that the upper tube power chip and the lower tube power chip are staggered, and a power loop is generated between the upper tube power chip and the adjacent lower tube power chip. The current of each power loop flows from the upper tube power chip of the second substrate 200 to the lower tube power chip of the first substrate 100, and then flows to the corresponding lower DC-conductive metal layer. The mutual inductance of the two power loops with opposite current directions is offset in the vertical direction and the horizontal direction.

[0060] Please combine Figure 1 , Figure 2 and Figure 3 The first substrate 100 and the second substrate 200 are a sandwich structure, each including a conductive metal layer, an insulating layer and a heat dissipation metal layer.

[0061] Specifically, the first substrate 100 includes a first conductive metal layer 101, a first insulating layer 102, and a first heat dissipation metal layer 103, wherein the first conductive metal layer 101, the first insulating layer 102, and the first heat dissipation metal layer 103 are stacked in sequence. The second substrate 200 includes a second conductive metal layer 201, a second insulating layer 202, and a second heat dissipation metal layer 203, wherein the second conductive metal layer 201, the second insulating layer 202, and the second heat dissipation metal layer 203 are stacked in sequence, and the first conductive metal layer 101 and the second conductive metal layer 201 are parallel to each other. The first heat dissipation metal layer 103 and the second heat dissipation metal layer 203 are used to set an external heat sink to achieve double-sided heat dissipation, which is conducive to heat dissipation.

[0062] Please combine Figure 4 , Figure 5 , Figure 6 and Fig. 9 The double-sided heat dissipation power module with a planar mosaic structure also includes a plurality of metal blocks 801 to 812, wherein each upper tube power chip is connected to the AC conductive metal layer 301 through a metal block; each lower tube power chip is connected to the corresponding lower DC-conductive metal layer through a metal block; and two diagonally adjacent lower DC-conductive metal layers are connected to the upper DC-conductive metal layer through a metal block.

[0063] Specifically, the metal block is a molybdenum compound metal block.

[0064] In this embodiment, the upper power chip is vertically connected to the AC conductive metal layer 301 through a metal block, and the lower power chip is vertically connected to the corresponding lower DC-conductive metal layer. The molybdenum metal block and the copper clip are used to achieve the connection of the power circuit with the same potential.

[0065] Please combine Figure 4 and Figure 5 A first AC terminal 401 and a second AC terminal 402 are provided on opposite sides of the AC conductive metal layer 301; each sawtooth of the DC+ conductive metal layer 501 is connected to a DC+ terminal, and multiple sawtooths correspond one-to-one to multiple DC+ terminals 601~604; each lower DC- conductive metal layer is connected to a DC- terminal, and multiple lower DC- conductive metal layers 502~505 correspond one-to-one to multiple DC- terminals 605~608.

[0066] See also Fig.11 , Fig.11 A schematic diagram of the structure of a power chip provided by an embodiment of the present invention. The power chip includes a silicon carbide MOSFET power chip, and the silicon carbide MOSFET power chip includes a gate, a power source, a Kelvin source, and a drain, wherein the power source, the Kelvin source, and the gate are all arranged on the first side surface of the silicon carbide MOSFET power chip; the drain is arranged on the second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface; the drain of the upper tube power chip is arranged on the surface of the DC+ conductive metal layer 501, and the power source is connected to the AC conductive metal layer 301; the drain of the lower tube power chip is arranged on the surface of the AC conductive metal layer 301, and the power source is connected to the corresponding lower DC- conductive metal layer.

[0067] Furthermore, the power source of the upper power chip is connected to the AC conductive metal layer 301 through a metal block, and the power source of the lower power chip is connected to the corresponding lower DC-conductive metal layer through a metal block.

[0068] Please combine Figure 4 and Figure 5 A Kelvin source terminal and a gate terminal are provided near each power chip as conductive metal layer driving terminals. The Kelvin source terminal and the gate terminal are close to each other and are provided on the insulating layer of the substrate. The Kelvin source terminal is connected to the Kelvin source through a bonding wire, and the gate terminal is connected to the gate through a bonding wire. Figure 4 403 to 410 are upper conductive metal layer drive terminals. Figure 5 In the figure, 609 to 616 are lower conductive metal layer driving terminals.

[0069] In this embodiment, a double-sided heat dissipation power module with a planar mosaic structure is formed by a first conductive metal layer 101, a second conductive metal layer 201, a plurality of power chips, a plurality of metal blocks, a first AC terminal 401, a second AC terminal 402, a plurality of DC+ terminals, a plurality of DC- terminals, and a plurality of conductive metal layer drive terminals. The number of power chips is not limited to Figure 1-Figure 10 The specific number can be set according to device requirements.

[0070] Taking the number of power chips as 8, which are 4 upper silicon carbide MOSFET power chips and 4 lower silicon carbide MOSFET power chips as an example, the specific structure of the double-sided heat dissipation power module with a planar mosaic structure is as follows:

[0071] See also Figure 4 and Figure 8 The first conductive metal layer 101 includes an AC conductive metal layer 301, a first DC-conductive metal layer 302 and a second DC-conductive metal layer 303, wherein the first DC-conductive metal layer 302 and the second DC-conductive metal layer 303 are embedded in the AC conductive metal layer 301 to form an upper DC-conductive metal layer.

[0072] See also Figure 5 , Figure 7 and Fig. 9 The second conductive metal layer 201 includes a DC+ conductive metal layer 501, a third DC- conductive metal layer 502, a fourth DC- conductive metal layer 503, a fifth DC- conductive metal layer 504 and a sixth DC- conductive metal layer 505, wherein the opposite sides of the DC+ conductive metal layer 501 form a square sawtooth structure with four sawtooths, and the four sawtooths are staggered, the third DC- conductive metal layer 502, the fourth DC- conductive metal layer 503, the fifth DC- conductive metal layer 504 and the sixth DC- conductive metal layer 505 are distributed in the grooves opposite to each sawtooth, the third DC- conductive metal layer 502 and the fourth DC- conductive metal layer 503 are diagonally arranged and connected to each other through the first DC- conductive metal layer 302, the fourth DC- conductive metal layer 503 and the fifth DC- conductive metal layer 504 are diagonally arranged and connected to each other through the copper clip, and the fifth DC- conductive metal layer 504 and the sixth DC- conductive metal layer 505 are diagonally arranged and connected to each other through the second DC- conductive metal layer 303.

[0073] It can be understood that the shape of the AC conductive metal layer 301 is approximately a horizontally placed figure 8, and the shape of the first DC-conductive metal layer 302 and the second DC-conductive metal layer 303 is approximately a rectangle, which is inlaid in the left and right gaps of the figure 8, such as Figure 8 The shape of the first DC+ conductive metal layer 501 is approximately a rectangle with four adjacent right angles connected in sequence, as shown in FIG. Figure 7 As shown, the third DC-conductive metal layer 502, the fourth DC-conductive metal layer 503, the fifth DC-conductive metal layer 504 and the sixth DC-conductive metal layer 505 are approximately rectangular in shape and are inlaid in the remaining area of ​​the lower conductive metal layer, such as Fig. 9 As shown, the double-sided heat dissipation power module as a whole has a planar mosaic structure.

[0074] See also Fig. 9 In this embodiment, molybdenum-based metal blocks 809-812 and copper clips 813 are used to achieve the connection of the power circuits with the same potential. Specifically, the molybdenum-based metal block 809 connects the first DC-conductive metal layer 302 and the third DC-conductive metal layer 502, the molybdenum-based metal block 810 connects the first DC-conductive metal layer 302 and the fourth DC-conductive metal layer 503, the copper clip 813 connects the fourth DC-conductive metal layer 503 and the fifth DC-conductive metal layer 504, the molybdenum-based metal block 811 connects the second DC-conductive metal layer 303 and the fifth DC-conductive metal layer 504, and the molybdenum-based metal block 812 connects the second DC-conductive metal layer 303 and the sixth DC-conductive metal layer 505.

[0075] See also Figure 7 , Figure 8 and Fig. 9 , the first AC terminal 401 and the second AC terminal 402 are welded on the left and right sides of the AC conductive metal layer 301; the first DC+ terminal 601, the second DC+ terminal 602, the third DC+ terminal 603, and the fourth DC+ terminal 604 are welded on the four serrations on the DC+ conductive metal layer 501 in sequence; the first DC-terminal 605, the second DC-terminal 606, the third DC-terminal 607, and the fourth DC-terminal 608 are welded on the third DC-conductive metal layer 502, the fourth DC-conductive metal layer 503, the fifth DC-conductive metal layer 504, and the sixth DC-conductive metal layer 505, respectively.

[0076] Specifically, the plurality of upper tube power chips include: a first upper tube power chip 701, a second upper tube power chip 702, a third upper tube power chip 703 and a fourth upper tube power chip 704, wherein the first upper tube power chip 701, the second upper tube power chip 702, the third upper tube power chip 703 and the fourth upper tube power chip 704 are arranged one by one on the four sawtooths of the square sawtooth structure, and are all connected to the AC conductive metal layer 301.

[0077] The plurality of down tube power chips include: a first down tube power chip 705, a second down tube power chip 706, a third down tube power chip 707 and a fourth down tube power chip 708, wherein the first down tube power chip 705, the second down tube power chip 706, the third down tube power chip 707 and the fourth down tube power chip 708 are distributed on the AC conductive metal layer 301, and correspond to the third DC-conductive metal layer 502, the fourth DC-conductive metal layer 503, the fifth DC-conductive metal layer 504 and the sixth DC-conductive metal layer 505 respectively, and are vertically connected up and down.

[0078] The plurality of metal blocks include molybdenum metal blocks 801 to 812. The first conductive metal layer 101 and the second conductive metal layer 201 each include four groups of driving terminals, and the upper conductive metal layer driving terminals 403 to 410 and the lower conductive metal layer driving terminals 609 to 616 are both composed of gate terminals and Kelvin source terminals close to each other.

[0079] Specifically, the drain of the first upper tube power chip 701 is set at the first rectangular position from left to right of the DC+ conductive metal layer 501, the power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 805, and the Kelvin source and gate are connected to the lower conductive metal layer drive terminals 613 and 614 through bonding wires.

[0080] The drain of the second upper tube power chip 702 is set at the second rectangular position from left to right of the DC+ conductive metal layer 501, and the power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 807, and the Kelvin source and gate are connected to the lower conductive metal layer drive terminals 609 and 610 through bonding wires.

[0081] The drain of the third upper tube power chip 703 is set at the third rectangular position from left to right of the DC+ conductive metal layer 501, and the power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 806, and the Kelvin source and gate are connected to the lower conductive metal layer drive terminals 615 and 616 through bonding wires.

[0082] The drain of the fourth upper tube power chip 704 is set at the fourth rectangular position from left to right of the DC+ conductive metal layer 501, and the power source is connected to the AC conductive metal layer 301 through the molybdenum metal block 808, and the Kelvin source and gate are connected to the lower conductive metal layer drive terminals 611 and 612 through bonding wires.

[0083] The drain of the first lower tube power chip 705 is arranged at the first AC conductive metal layer 301 at the lower left corner of the first DC-conductive metal layer 302, and the power source is connected to the third DC-conductive metal layer 502 through the molybdenum metal block 801, and the Kelvin source and gate are connected to the upper conductive metal layer drive terminals 407 and 408 through bonding wires.

[0084] The drain of the second lower tube power chip 706 is arranged at the first AC conductive metal layer 301 at the upper right corner of the first DC-conductive metal layer 302, and the power source is connected to the fourth DC-conductive metal layer 503 and the fifth DC-conductive metal layer 504 through the molybdenum oxide metal block 803, and the Kelvin source and gate are connected to the upper conductive metal layer driving terminals 403 and 404 through bonding wires.

[0085] The drain of the third lower tube power chip 707 is arranged at the first AC conductive metal layer position 301 at the lower left corner of the second DC-conductive metal layer 303, and the power source is connected to the fifth DC-conductive metal layer 504 through the molybdenum oxide metal block 802, and the Kelvin source and gate are connected to the upper conductive metal layer drive terminals 409 and 410 through bonding wires.

[0086] The drain of the fourth lower tube power chip 708 is arranged at the first AC conductive metal layer 301 in the upper right corner of the second DC-circuit 303 area, and the power source is connected to the sixth DC-conductive metal layer 505 through the molybdenum metal block 804, and the Kelvin source and gate are connected to the upper conductive metal layer drive terminals 405 and 406 through bonding wires.

[0087] See also Fig.10 In this embodiment, eight power chips are used to form ten power loops, and each upper silicon carbide chip has multiple power loops.

[0088] A first power loop is formed between the first upper tube power chip 701 and the first lower tube power chip 705 and the third DC-conductive metal layer 502 ; a second power loop is formed between the first upper tube power chip 701 and the second lower tube power chip 706 and the fourth DC-conductive metal layer 503 .

[0089] Specifically, the current flows in from the first DC+ terminal 601, flows through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the first upper tube power chip 701, flows out from the power source and passes through the molybdenum metal block 805 to the upper plate. If the current flows through the AC conductive metal layer 301 to the drain at the bottom of the first lower tube power chip 705, then flows through the molybdenum metal block 801 to the third DC-conductive metal layer 502 of the lower plate, and finally flows out from the first DC-terminal 605, a first power loop is formed; if the current flows through the first AC conductive metal layer 301 to the drain at the bottom of the second lower tube power chip 706, then flows through the molybdenum metal block 803 to the fourth DC-conductive metal layer 503 of the lower plate, and finally flows out from the second DC-terminal 606, a second power loop is formed.

[0090] A third power loop is formed between the second upper tube power chip 702, the first lower tube power chip 705, and the third DC-conductive metal layer 502; a fourth power loop is formed between the second upper tube power chip 702, the second lower tube power chip 706, and the fourth DC-conductive metal layer 503; and a fifth power loop is formed between the second upper tube power chip 702, the third lower tube power chip 707, and the fifth DC-conductive metal layer 504.

[0091] Specifically, the current flows in from the second DC+ terminal 602, flows through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the second upper tube power chip 702, flows out from the power source and passes through the molybdenum metal block 807 to the upper plate. If the current flows through the AC conductive metal layer 301 to the drain at the bottom of the first lower tube power chip 705, then passes through the molybdenum metal block 801 to the third DC- conductive metal layer 502 of the lower plate, and finally flows out from the first DC- terminal 605, a third power loop is formed; if the current flows through the A The fourth power loop is formed if the current flows through the C conductive metal layer 301 to the drain at the bottom of the second lower tube power chip 706, then passes through the molybdenum oxide metal block 803 to the fourth DC-conductive metal layer 503 of the lower plate, and finally flows out from the second DC-terminal 606. If the current flows through the AC conductive metal layer 301 to the drain at the bottom of the third lower tube power chip 707, then passes through the molybdenum oxide metal block 802 to the fifth DC-conductive metal layer 504 of the lower plate, and finally flows out from the third DC-terminal 607, then the fifth power loop is formed.

[0092] A sixth power loop is formed between the third upper tube power chip 703, the second lower tube power chip 706 and the fourth DC-conductive metal layer 503; a seventh power loop is formed between the third upper tube power chip 703, the third lower tube power chip 707 and the fifth DC-conductive metal layer 504; and an eighth power loop is formed between the third upper tube power chip 703, the fourth lower tube power chip 708 and the sixth DC-conductive metal layer 505.

[0093] Specifically, the current flows in from the third DC+ terminal 603, flows through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the third upper tube power chip 703, flows out from the power source and passes through the molybdenum metal block 806 to the upper plate. If the current flows through the AC conductive metal layer 301 to the drain at the bottom of the second lower tube power chip 706, then passes through the molybdenum metal block 803 to the fourth DC- conductive metal layer 503 of the lower plate, and finally flows out from the second DC- terminal 606, a sixth power loop is formed; if the current flows through the A The C conductive metal layer 301 reaches the drain at the bottom of the third lower tube power chip 707, then passes through the molybdenum oxide metal block 802 to the fifth DC-conductive metal layer 504 of the lower plate, and finally flows out from the third DC-terminal 607, thus forming the seventh power loop. If the AC conductive metal layer 301 reaches the drain at the bottom of the fourth lower tube power chip 708, then passes through the molybdenum oxide metal block 804 to the sixth DC-conductive metal layer 505 of the lower plate, and finally flows out from the fourth DC-terminal 608, then forming the eighth power loop.

[0094] A ninth power loop is formed between the fourth upper tube power chip 704 , the third lower tube power chip 707 and the fifth DC-conductive metal layer 504 ; a tenth power loop is formed between the fourth upper tube power chip 704 , the fourth lower tube power chip 708 and the sixth DC-conductive metal layer 505 .

[0095] Specifically, the current flows in from the fourth DC+ terminal 604, flows through the lower plate DC+ conductive metal layer 501 to the drain at the bottom of the fourth upper tube power chip 704, flows out from the power source and passes through the molybdenum metal block 808 to the upper plate. If the current flows through the AC conductive metal layer 301 to the drain at the bottom of the third lower tube power chip 707, then passes through the molybdenum metal block 802 to the fifth DC-conductive metal layer 504 of the lower plate, and finally flows out from the third DC-terminal 607, then a ninth power loop is formed; if the current flows through the AC conductive metal layer 301 to the drain at the bottom of the fourth lower tube power chip 708, then passes through the molybdenum metal block 804 to the sixth DC-conductive metal layer 505 of the lower plate, and finally flows out from the fourth DC-terminal 608, then a tenth power loop is formed.

[0096] The above ten power circuits have short absolute lengths, small self-inductance of the power commutation circuits, and small size of the power modules. In addition, there are multiple pairs of mutual inductance cancellation paths between the power circuits, such as: the mutual inductance between the first power circuit and the fourth power circuit is cancelled in the vertical and horizontal directions, the mutual inductance between the fourth power circuit and the seventh power circuit is cancelled in the vertical and horizontal directions, the mutual inductance between the seventh power circuit and the tenth power circuit is cancelled in the vertical and horizontal directions, the mutual inductance between the second power circuit and the third power circuit is cancelled in the vertical and horizontal directions, the mutual inductance between the fifth power circuit and the sixth power circuit is cancelled in the vertical and horizontal directions, and the mutual inductance between the eighth power circuit and the ninth power circuit is cancelled in the vertical and horizontal directions. By canceling the mutual inductance between the above power circuits in the vertical and horizontal directions, the parasitic inductance of the power module is greatly reduced to 0.8nH. The power module is suitable for high current and high power density application scenarios.

[0097] The double-sided heat dissipation power module of the planar mosaic structure of the present embodiment is designed with an AC conductive metal layer, a DC+ conductive metal layer, a DC- conductive metal layer, and a plurality of upper tube power chips and a plurality of lower tube power chips, so that each power chip in the module has multiple power circuits, and there is an independent power circuit between each upper tube power chip and the adjacent lower tube power chip, and the mutual inductance of the two power circuits in the vertical direction and the horizontal direction are offset. By increasing the number of power circuits, the current can flow from the parallel upper tube chips through any adjacent parallel lower tube chips to form a commutation circuit, thereby increasing the number of current paths; based on the principle of magnetic flux cancellation, the current directions of the relative commutation circuits in the vertical and horizontal directions are opposite, thereby achieving mutual inductance cancellation, reducing the parasitic inductance inside the module, and effectively reducing the switching loss and electrical stress generated by the power module during high-speed switching.

[0098] The power module of this embodiment can effectively avoid the current concentration phenomenon in some chips and local areas inside the module by increasing the number of power circuits and optimizing the current path. This design can balance the heat distribution and avoid excessive module temperature, thereby improving the performance and reliability of the module; the uniform current distribution helps to reduce the formation of hot spots inside the module, reduce the thermal mechanical stress of the module, and extend the service life of the module.

[0099] The power module structure of this embodiment adopts double-sided heat dissipation, and the upper tube power chip and the lower tube power chip are placed alternately, which optimizes the heat dissipation path, avoids local overheating, ensures uniform heat distribution and efficient heat conduction, and reduces thermal coupling between chips.

[0100] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A double-sided heat dissipation power module with a planar mosaic structure, characterized in that: include: A first substrate (100) having a first conductive metal layer (101), a second substrate (200) having a second conductive metal layer (201), and a plurality of power chips, wherein the first conductive metal layer (101) and the second conductive metal layer (201) are parallel and opposite to each other, wherein: The first conductive metal layer (101) comprises an AC conductive metal layer (301) and a plurality of upper DC-conductive metal layers, wherein the plurality of upper DC-conductive metal layers are embedded in the AC conductive metal layer (301); The second conductive metal layer (201) comprises a DC+ conductive metal layer (501) and a plurality of lower DC- conductive metal layers; the opposite sides of the DC+ conductive metal layer (501) form a square sawtooth structure, and the plurality of sawtooths of the square sawtooth structure are arranged in a staggered manner; the plurality of lower DC- conductive metal layers are arranged in a one-to-one correspondence in the plurality of grooves of the square sawtooth structure, and two diagonally adjacent lower DC- conductive metal layers are connected via the upper DC- conductive metal layer, and / or two diagonally adjacent lower DC- conductive metal layers are connected via a metal clip; The plurality of power chips include a plurality of upper tube power chips and a plurality of lower tube power chips; the plurality of upper tube power chips are arranged one-to-one on the plurality of saw teeth of the square sawtooth structure and are connected to the AC conductive metal layer (301); the plurality of lower tube power chips are arranged on the AC conductive metal layer (301), are arranged in an alternating manner with the plurality of upper tube power chips, and are connected one-to-one with the plurality of lower DC-conductive metal layers; An independent power loop exists between each of the upper tube power chips and the adjacent lower tube power chip, and the two power loops are mutually inducted in both the vertical and horizontal directions.

2. The double-sided heat dissipation power module with a planar mosaic structure according to claim 1, characterized in that: The first substrate (100) further comprises a first insulating layer (102) and a first heat dissipation metal layer (103), wherein the first conductive metal layer (101), the first insulating layer (102) and the first heat dissipation metal layer (103) are stacked in sequence; The second substrate (200) further comprises a second insulating layer (202) and a second heat dissipation metal layer (203), wherein the second conductive metal layer (201), the second insulating layer (202) and the second heat dissipation metal layer (203) are stacked in sequence; The first heat dissipation metal layer (103) and the second heat dissipation metal layer (203) are used to set up an external heat sink.

3. The double-sided heat dissipation power module with a planar mosaic structure according to claim 1, characterized in that: A first AC terminal (401) and a second AC terminal (402) are provided on opposite sides of the AC conductive metal layer (301); Each sawtooth of the DC+ conductive metal layer (501) is connected to a DC+ terminal; Each of the lower DC-conductive metal layers is connected with a DC-terminal.

4. The double-sided heat dissipation power module with a planar mosaic structure according to claim 1, characterized in that: Also included are several metal blocks, among which, Each of the upper tube power chips is connected to the AC conductive metal layer (301) via the metal block; Each of the lower tube power chips is connected to the corresponding lower DC-conductive metal layer through the metal block; The two diagonally adjacent lower DC-conductive metal layers are connected to the upper DC-conductive metal layer through the metal block.

5. The double-sided heat dissipation power module with a planar mosaic structure according to claim 1, characterized in that: The power chip comprises a silicon carbide MOSFET power chip, and the silicon carbide MOSFET power chip comprises a gate, a power source, a Kelvin source and a drain, wherein: The power source electrode, the Kelvin source electrode, and the gate electrode are all arranged on a first side surface of the silicon carbide MOSFET power chip; the drain electrode is arranged on a second side surface of the silicon carbide MOSFET power chip, and the second side surface is opposite to the first side surface; The drain electrode of the upper tube power chip is arranged on the surface of the DC+ conductive metal layer (501), and the power source electrode is connected to the AC conductive metal layer (301); The drain electrode of the lower tube power chip is arranged on the surface of the AC conductive metal layer (301), and the power source electrode is connected to the corresponding lower DC-conductive metal layer.

6. The double-sided heat dissipation power module with a planar mosaic structure according to claim 5, characterized in that: A Kelvin source terminal and a gate terminal are provided near each power chip as conductive metal layer driving terminals, and the Kelvin source terminal and the gate terminal are close to each other and are provided on the insulating layer of the substrate; The Kelvin source terminal is connected to the Kelvin source, and the gate terminal is connected to the gate.

7. The double-sided heat dissipation power module with a planar mosaic structure according to claim 1, characterized in that: The first conductive metal layer (101) comprises an AC conductive metal layer (301), a first DC-conductive metal layer (302) and a second DC-conductive metal layer (303), wherein the first DC-conductive metal layer (302) and the second DC-conductive metal layer (303) are embedded in the AC conductive metal layer (301); The second conductive metal layer (201) comprises a DC+ conductive metal layer (501), a third DC- conductive metal layer (502), a fourth DC- conductive metal layer (503), a fifth DC- conductive metal layer (504) and a sixth DC- conductive metal layer (505), wherein opposite sides of the DC+ conductive metal layer (501) form a square sawtooth structure with four sawtooths, and the four sawtooths are arranged in a staggered manner, and the third DC- conductive metal layer (502), the fourth DC- conductive metal layer (503), the fifth DC- conductive metal layer (504) and the sixth DC- conductive metal layer (505) are arranged in a staggered manner. - a conductive metal layer (505) is distributed in each groove opposite to the sawtooth, the third DC-conductive metal layer (502) and the fourth DC-conductive metal layer (503) are arranged diagonally and connected to each other through the first DC-conductive metal layer (302), the fourth DC-conductive metal layer (503) and the fifth DC-conductive metal layer (504) are arranged diagonally and connected to each other through a copper clip, and the fifth DC-conductive metal layer (504) and the sixth DC-conductive metal layer (505) are arranged diagonally and connected to each other through the second DC-conductive metal layer (303).

8. The double-sided heat dissipation power module with a planar mosaic structure according to claim 7, characterized in that: The plurality of upper tube power chips include: a first upper tube power chip (701), a second upper tube power chip (702), a third upper tube power chip (703) and a fourth upper tube power chip (704), wherein the first upper tube power chip (701), the second upper tube power chip (702), the third upper tube power chip (703) and the fourth upper tube power chip (704) are arranged on four saw teeth of the square sawtooth structure in a one-to-one correspondence, and are all connected to the AC conductive metal layer (301); The plurality of down tube power chips include: a first down tube power chip (705), a second down tube power chip (706), a third down tube power chip (707) and a fourth down tube power chip (708), wherein the first down tube power chip (705), the second down tube power chip (706), the third down tube power chip (707) and the fourth down tube power chip (708) are distributed on the AC conductive metal layer (301), and correspond to the third DC-conductive metal layer (502), the fourth DC-conductive metal layer (503), the fifth DC-conductive metal layer (504) and the sixth DC-conductive metal layer (505), respectively.

9. The double-sided heat dissipation power module with a planar mosaic structure according to claim 8, characterized in that: A first power loop is formed between the first upper tube power chip (701), the first lower tube power chip (705) and the third DC-conductive metal layer (502); a second power loop is formed between the first upper tube power chip (701), the second lower tube power chip (706) and the fourth DC-conductive metal layer (503); A third power loop is formed between the second upper tube power chip (702), the first lower tube power chip (705) and the third DC-conductive metal layer (502); a fourth power loop is formed between the second upper tube power chip (702), the second lower tube power chip (706) and the fourth DC-conductive metal layer (503); and a fifth power loop is formed between the second upper tube power chip (702), the third lower tube power chip (707) and the fifth DC-conductive metal layer (504); A sixth power loop is formed between the third upper tube power chip (703), the second lower tube power chip (706) and the fourth DC-conductive metal layer (503); a seventh power loop is formed between the third upper tube power chip (703), the third lower tube power chip (707) and the fifth DC-conductive metal layer (504); and an eighth power loop is formed between the third upper tube power chip (703), the fourth lower tube power chip (708) and the sixth DC-conductive metal layer (505); A ninth power loop is formed between the fourth upper tube power chip (704), the third lower tube power chip (707) and the fifth DC-conductive metal layer (504); a tenth power loop is formed between the fourth upper tube power chip (704), the fourth lower tube power chip (708) and the sixth DC-conductive metal layer (505); The mutual inductance between the first power circuit and the fourth power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the fourth power circuit and the seventh power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the seventh power circuit and the tenth power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the second power circuit and the third power circuit cancels out in the vertical and horizontal directions, the mutual inductance between the fifth power circuit and the sixth power circuit cancels out in the vertical and horizontal directions, and the mutual inductance between the eighth power circuit and the ninth power circuit cancels out in the vertical and horizontal directions.

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