Display device

Abstract

According to one aspect of the present disclosure, a display device includes: a first substrate in which a plurality of sub-pixels including at least one defective sub-pixel and a plurality of normal sub-pixels are defined; a light emitting diode disposed in each of the plurality of sub-pixels; a driving transistor having a source connected to the first electrode of the light emitting diode; and a capacitor including a plurality of capacitor electrodes connected to the gate and source of the driving transistor. The plurality of capacitor electrodes are in contact with each other in the defective sub-pixel. Accordingly, in a defective sub-pixel, capacitor electrodes are connected to each other to connect a gate and a source of a driving transistor, and the defective sub-pixel can be easily darkened.

Description

[0001] This application is a divisional application of the invention patent application with the application date of February 26, 2024, application number 202410208411.3, and invention name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the priority of Korean Patent Application No. 10-2023-0026730 filed on February 28, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0005] As display devices used for displays of computers, televisions, mobile phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0006] The application range of the display device is widely applied to personal digital assistants as well as displays of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0007] In addition, recently, a display device including a light emitting diode (LED) has attracted much attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its lifespan longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast lighting speed, excellent luminous efficiency, and strong impact resistance, so it has excellent stability and can display images with high brightness. Summary of the invention

[0008] One object to be achieved by the present disclosure is to provide a display device that easily dims a malfunctioning sub-pixel.

[0009] Another object to be achieved by the present disclosure is to provide a display device that dims a failed sub-pixel through only one welding process.

[0010] Another object to be achieved by the present disclosure is to provide a display device that can darken defective sub-pixels again through only one cutting process.

[0011] Another object to be achieved by the present disclosure is to provide a display device which reduces damage of the periphery of a welding region by easily performing a welding process using a low-power laser.

[0012] Another object to be achieved by the present disclosure is to provide a display device in which a light emitting diode of a dimmed sub-pixel is connected to a pixel circuit of a normal sub-pixel through a single welding process.

[0013] Another object to be achieved by the present disclosure is to provide a display device that easily connects a light emitting diode connected to a defective pixel circuit to a normally driven pixel circuit using a reflection plate.

[0014] Another object to be achieved by the present disclosure is to provide a display device that reduces a defect in which reflection plates are connected to each other due to static electricity.

[0015] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0016] According to one aspect of the present disclosure, a display device includes: a first substrate, in which a plurality of sub-pixels including at least one defective sub-pixel and a plurality of normal sub-pixels are defined; a light emitting diode, disposed in each of the plurality of sub-pixels; a plurality of transistors, disposed in each of the plurality of sub-pixels and including a driving transistor, the driving transistor having a source connected to a first electrode of the light emitting diode; a capacitor, including a plurality of capacitor electrodes connected to a gate and a source of the driving transistor; and a reflective plate, disposed in each of the plurality of sub-pixels and electrically connected to the first electrode. The plurality of capacitor electrodes of the capacitor are in contact with each other in the defective sub-pixel. Therefore, in the defective sub-pixel, the capacitor electrodes are connected to each other so that the gate and the source of the driving transistor are connected, and the defective sub-pixel can be easily darkened.

[0017] Additional details of example embodiments are included in the detailed description and accompanying drawings.

[0018] According to the present disclosure, a defective sub-pixel is darkened through only two welding processes, and a repair process can be performed.

[0019] According to the present disclosure, a defective sub-pixel can be simply dimmed again through a one-time cutting process.

[0020] According to the present disclosure, a soldering process is performed on a capacitor connected to a driving transistor to darken a defective pixel circuit.

[0021] According to the present disclosure, a light emitting diode of a defective sub-pixel can be easily connected to a pixel circuit of a normal sub-pixel using a reflective plate.

[0022] According to the present disclosure, the intensity of laser light irradiated during repair is reduced to minimize damage to the periphery of the area where the laser light is irradiated.

[0023] According to the present disclosure, a short circuit failure generated in the first connection pattern and the second connection pattern for connecting the reflection plate due to static electricity can be reduced.

[0024] According to the present disclosure, a repair process is performed using a reflection plate and a capacitor without requiring a separate structure only for the repair process, so that the structure of the display device can be simplified.

[0025] The effects according to the present disclosure are not limited to the contents exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 4 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0032] Figure 5 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 6 is a plan view of a pixel region of a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 is a circuit diagram for explaining a repair process of a sub-pixel according to an exemplary embodiment of the present disclosure;

[0036] Fig.9A and Fig. 9B is a cross-sectional view of a second capacitor of a display device according to an exemplary embodiment of the present disclosure;

[0037] Fig.10is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure; and

[0038] Fig.11A and Fig. 11B It is along Fig.10 A cross-sectional view taken along line XI-XI'. DETAILED DESCRIPTION

[0039] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0040] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, the detailed description of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to be able to add other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0041] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0042] When terms such as "on," "above," "below," and "adjacent" are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately" or "directly."

[0043] When an element or a layer is disposed “on” another element or layer, the another layer or the another element may be directly interposed on the another element or between them.

[0044] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0045] Throughout the specification, like reference numerals generally refer to like elements.

[0046] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0047] The features of the various embodiments of the present disclosure may be attached or combined with each other in part or in whole, and may be technically interconnected and operated in various ways, and these embodiments may be performed independently of each other or in association with each other.

[0048] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure. Figure 1 In the present invention, for convenience of description, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0050] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD supplying various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0051] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 2 shows that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0052] The data driver DD converts the image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0053] The timing controller TC aligns image data input from the outside to supply the image data to the data driver DD. The timing controller TC may generate a gate control signal and a data control signal using synchronization signals (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. The timing controller TC may supply the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0054] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may also be connected to a high potential power line VL1, a low potential power line VL2, a reference line RL, etc.

[0055] In the display panel PN, a display area AA and a non-display area NA surrounding the display area AA may be defined.

[0056] The display area AA is an area where an image is displayed in the display device 100. In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the smallest units constituting the display area AA, and n sub-pixels SP may form one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode 130, a thin film transistor for driving the light-emitting diode 130, and the like may be provided. The plurality of light-emitting diodes 130 may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel PN, the light-emitting diode 130 may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0057] In the display area AA, a plurality of wirings for transmitting various signals to a plurality of sub-pixels SP are provided. For example, the plurality of wirings may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP, a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL extend in one direction in the display area AA and are connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the display area AA and are connected to the plurality of sub-pixels SP. In addition, in the display area AA, a low potential power line VL2, a high potential power line VL1, and the like may be further provided, but are not limited thereto.

[0058] The non-display area NA is an area where no image is displayed, and thus the non-display area NA may be defined as an area extending from the display area AA. In the non-display area NA, a connection line for transmitting a signal to a sub-pixel SP, a pad electrode, or a driving IC (e.g., a gate driver IC or a data driver IC) of the display area AA may be disposed.

[0059] Meanwhile, the non-display area NA may be located on the rear surface of the display panel PN (ie, a surface where the sub-pixels SP are not disposed) or the non-display area NA may be omitted and is not limited to that shown in the drawings.

[0060] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the display area AA in a gate-in-display area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards. The data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0061] If the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the non-display area NA, the area of ​​the non-display area NA for disposing the gate driver GD and the pad electrode needs to be larger than a predetermined level. Therefore, the bezel may be increased.

[0062] On the contrary, when the gate driver GD is installed in the display area AA in a GIA manner and the side lines SRL connecting the signal lines on the front of the display panel PN to the pad electrodes on the back of the display panel PN are formed to bond the flexible film and the printed circuit board to the back of the display panel PN, the non-display area NA on the front of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame with substantially no frame can be achieved.

[0063] Specifically, refer to Figure 2A and Figure 2B In the non-display area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are provided. For example, in the non-display area NA on the front side of the display panel PN, a first pad electrode PAD1 for transmitting signals to a plurality of sub-pixels SP is provided. In the non-display area NA on the back side of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component (e.g., a flexible film and a printed circuit board) is provided. That is, on the front side of the display panel PN displaying an image, only the pad area of ​​the non-display area NA where the first pad electrode PAD1 is provided may be formed minimally.

[0064] In this case, although not shown in the drawings, various signal lines (eg, scan lines SL or data lines DL) connected to the plurality of sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0065] The side line SRL is disposed along the side of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front of the display panel PN and the second pad electrode PAD2 on the back of the display panel PN. Therefore, a signal from a driving component on the back of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front to the side and back of the display panel PN to minimize the area of ​​the non-display region NA on the front of the display panel PN.

[0066] Reference Figure 2B , a spliced ​​display device TD with a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the spliced ​​display device TD is implemented using the display device 100 with a minimized frame, the seam area between the display devices 100 where no image is displayed is minimized, thereby improving the display quality.

[0067] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, a distance D1 between pixels PX between display devices 100 is constantly configured to minimize a seam area.

[0068] However, Figure 2A and Figure 2B It is exemplary, and thus the display device 100 according to the exemplary embodiment of the present disclosure may be a general display device 100 having a bezel, but is not limited thereto.

[0069] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure. Figure 4 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 5 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 6 is a plan view of a pixel region of a display device according to an exemplary embodiment of the present disclosure. Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 5 In the figure, for the convenience of description, only a plan view of one sub-pixel SP is shown.

[0070] First, refer to Figure 3, the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components provided in the display device 100, and may be an insulating substrate. A plurality of pixels PX are formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. In addition, the first substrate 110 may include a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a plastic material having flexibility.

[0071] A plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of pad areas are provided in the first substrate 110. Among them, the plurality of pixel areas UPA and the plurality of gate driving areas GA may be included in the display area AA of the display panel PN.

[0072] First, a plurality of pixel areas UPA are areas where a plurality of pixels PX are disposed. The plurality of pixel areas UPA may be disposed by forming a plurality of rows and a plurality of columns. Each of the plurality of pixels PX disposed in the plurality of pixel areas UPA includes a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light emitting diode 130 and a pixel circuit to emit light independently.

[0073] The plurality of gate drive areas GA are areas where gate drivers GD are provided. The gate driver GD may be installed in the display area AA in a gate-in-display-area (GIA) manner. For example, the gate drive area GA may be formed between the plurality of pixel areas UPA in a row direction and / or a column direction. The gate driver GD formed in the gate drive area GA may supply a scan signal to the plurality of scan lines SL.

[0074] The multiple pad areas are areas where multiple first pad electrodes PAD1 are provided. The multiple first pad electrodes PAD1 can transmit various signals to various wirings extending in the column direction in the display area AA. For example, the multiple first pad electrodes PAD1 include a data pad DP, a gate pad GP, a high potential power pad VP1, and a low potential power pad VP2. The data pad DP transmits the data voltage to the data line DL, and the gate pad GP transmits the clock signal, start signal, gate low voltage, gate high voltage, etc. used to drive the gate driver GD to the gate driver GD. The high potential power pad VP1 transmits the high potential power supply voltage to the high potential power line VL1, and the low potential power pad VP2 transmits the low potential power supply voltage to the low potential power line VL2.

[0075] The plurality of pad regions include a first pad region PA1 adjacent to the upper edge of the display panel PN and a second pad region PA2 adjacent to the lower edge of the display panel PN. At this time, different types of first pad electrodes PAD1 may be provided in the first pad region PA1 and the second pad region PA2. For example, in the first pad region PA1, a data pad DP, a gate pad GP, and a high potential power pad VP1 among the plurality of first pad electrodes PAD1 may be provided, and in the second pad region PA2, a low potential power pad VP2 may be provided.

[0076] At this time, the plurality of first pad electrodes PAD1 may be formed to have different sizes. For example, the plurality of data pads DP connected to the plurality of data lines DL in a one-to-one correspondence may have a narrow width, while the high potential power pad VP1, the low potential power pad VP2 and the gate pad GP may have a larger width. However, Figure 3 The illustrated widths of the data pad DP, the gate pad GP, the high potential power pad VP1, and the low potential power pad VP2 are exemplary, and thus the first pad electrode PAD1 may be configured in various sizes, but is not limited thereto.

[0077] Meanwhile, in order to reduce the frame of the display panel PN, the edge of the display panel PN may be cut and removed. A plurality of pixels PX, a plurality of wirings, and a plurality of first pad electrodes PAD1 are formed on an initial first substrate 110i, and an edge portion of the initial first substrate 110i is cut and ground to reduce the frame area. During the grinding process, a portion of the initial first substrate 110i is removed to form a first substrate 110 having a smaller size. At this time, a portion of the plurality of first pad electrodes PAD1 and the wirings disposed at the edge of the first substrate 110 may be removed. Therefore, only a portion of the plurality of first pad electrodes PAD1 may be retained on the first substrate 110.

[0078] Next, a plurality of data lines DL extending in a column direction from a plurality of first pad electrodes PAD1 are disposed on the first substrate 110 of the display panel PN. The plurality of data lines DL may extend from a plurality of data pads DP of the first pad area PA1 toward a plurality of pixel areas UPA. The plurality of data lines DL may extend in a column direction and overlap with the plurality of pixel areas UPA. Thus, the plurality of data lines DL may transmit a data voltage to a pixel circuit of each of the plurality of sub-pixels SP.

[0079] A plurality of high potential power lines VL1 extending in the column direction are disposed on the first substrate 110 of the display panel PN. A portion of the plurality of high potential power lines VL1 extends from the high potential power pad VP1 of the first pad area PA1 to the plurality of pixel areas UPA to transmit the high potential power voltage to the light emitting diodes 130 of the plurality of sub-pixels SP. Other high potential power lines of the plurality of high potential power lines VL1 may be electrically connected to the other high potential power lines VL1 through an auxiliary high potential power line AVL1 to be described below. Figure 3 In the present invention, for convenience of description, although one high potential power supply line VL1 and one high potential power supply pad VP1 are shown to be provided, a plurality of high potential power supply lines VL1 and a plurality of high potential power supply pads VP1 may be provided.

[0080] A plurality of low potential power lines VL2 extending in the column direction are provided on the first substrate 110 of the display panel PN. At least a portion of the plurality of low potential power lines VL2 extend from the low potential power pad VP2 of the second pad area PA2 to the plurality of pixel areas UPA to transmit the low potential power voltage to the pixel circuit of each of the plurality of sub-pixels SP. Other low potential power lines of the plurality of low potential power lines VL2 may be electrically connected to the other low potential power lines VL2 through an auxiliary low potential power line AVL2 to be described below.

[0081] A plurality of scan lines SL extending in a row direction are disposed on the first substrate 110 of the display panel PN. The plurality of scan lines SL extend in a row direction and may be disposed to pass through a plurality of pixel areas UPA and a plurality of gate driving areas GA. The plurality of scan lines SL may transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0082] A plurality of auxiliary high potential power lines AVL1 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary high potential power lines AVL1 may be provided in the region between the plurality of pixel regions UPA. The plurality of auxiliary high potential power lines AVL1 extending in the row direction may be electrically connected to the plurality of high potential power lines VL1 extending in the column direction through contact holes, and form a mesh structure. Therefore, the plurality of auxiliary high potential power lines AVL1 and the plurality of high potential power lines VL1 are configured to form a mesh structure to reduce voltage drop and voltage deviation.

[0083] A plurality of auxiliary low potential power lines AVL2 extending in the row direction are arranged on the first substrate 110 of the display panel PN. The plurality of auxiliary low potential power lines AVL2 may be arranged in the region between the plurality of pixel regions UPA. The plurality of auxiliary low potential power lines AVL2 extending in the row direction are electrically connected to the plurality of low potential power lines VL2 extending in the column direction through contact holes to form a mesh structure. Therefore, the plurality of auxiliary low potential power lines AVL2 and the plurality of low potential power lines VL2 are configured to form a mesh structure to reduce the resistance of the wiring and reduce the voltage deviation.

[0084] Reference Figure 3 and Figure 5 , a plurality of gate drive lines GVL extending in the row direction and the column direction are disposed on the first substrate 110 of the display panel PN. A portion of the plurality of gate drive lines GVL extends from the gate pad GP of the first pad area PA1 to the gate drive area GA to transmit signals to the gate driver GD. Other gate drive lines of the plurality of gate drive lines GVL extend in the row direction and may transmit signals to the gate drivers GD of the plurality of gate drive areas GA. Therefore, various signals are transmitted from the gate drive lines GVL to the gate driver GD to drive the gate driver GD.

[0085] The plurality of gate driving lines GVL may include wirings for transmitting a clock signal, a start signal, a gate high voltage, and a gate low voltage to the gate driver GD. Therefore, various signals are transmitted from the gate driving lines GVL to the gate driver GD to drive the gate driver GD.

[0086] For example, refer to Figure 5 The plurality of gate driving lines GVL may include gate power lines that transmit power voltage to the gate driver GD of the gate driving area GA. The plurality of gate power lines include a first gate power line VGHL that transmits a gate high voltage to the gate driver GD and a second gate power line VGLL that transmits a gate low voltage to the gate driver GD.

[0087] Reference Figure 3 The plurality of alignment keys are disposed in an area between the plurality of pixel areas UPA in the display panel PN. The plurality of alignment keys are used for alignment during a manufacturing process of the display panel PN. The plurality of alignment keys include a first alignment key AK1 and a second alignment key AK2.

[0088] The first alignment key AK1 may be disposed in the gate driving area GA between the plurality of pixel areas UPA. The first alignment key AK1 may be used to check the alignment positions of the plurality of light emitting diodes 130. For example, the first alignment key AK1 may have a cross shape, but is not limited thereto.

[0089] The second alignment key AK2 may be disposed to overlap the high potential power line VL1 between the plurality of pixel areas UPA. In the high potential power line VL1, a hole overlapping the second alignment key AK2 is formed to divide the second alignment key AK2 and the high potential power line VL1. The second alignment key AK2 may be used to align the display panel PN and the carrier. The display panel PN and the carrier are aligned using the second alignment key AK2, and a plurality of light emitting diodes 130 of the carrier may be transferred to the display panel PN. For example, the second alignment key AK2 may have a ring shape, but is not limited thereto.

[0090] In the following, reference will be made to Figures 4 to 7 The plurality of sub-pixels SP of the pixel area UPA are described in more detail.

[0091] Reference Figure 6 In one pixel area UPA, a plurality of sub-pixels SP forming one pixel PX are provided. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 that emit light of different colors. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be red sub-pixels, the third sub-pixel SP3 may be a green sub-pixel, and the fourth sub-pixel SP4 may be a blue sub-pixel, but is not limited thereto.

[0092] Hereinafter, description will be made by assuming that one pixel PX includes one first subpixel SP1, one second subpixel SP2, one third subpixel SP3, and one fourth subpixel SP4, that is, two red subpixels, one green subpixel, and one blue subpixel. However, the configuration of the pixel PX is not limited thereto.

[0093] Reference Figure 4 and Figure 5 Each of the plurality of sub-pixels SP is connected to a first scan line SL1, a second scan line SL2, a data line DL, a light emitting control signal line EL, a reference line RL, a high potential power line VL1, and a low potential power line VL2. In each of the plurality of sub-pixels SP, a pixel circuit and a light emitting diode 130 connected to the pixel circuit are provided, and the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0094] First, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 of a pixel circuit are provided in each of a plurality of sub-pixels SP. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 includes a gate, a source, and a drain.

[0095] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be N-type transistors or P-type transistors. In an N-type transistor, the carriers are electrons, so that the electrons can flow from the source to the drain, and the current can flow from the drain to the source. In a P-type transistor, the carriers are holes, so that the holes can flow from the source to the drain, and the current can flow from the source to the drain. For example, one of the multiple transistors may be an N-type transistor, and another of the multiple transistors may be a P-type transistor. Hereinafter, it will be described by assuming that the multiple transistors of the sub-pixel SP are P-type transistors, but the present disclosure is not limited thereto.

[0096] The first transistor T1 includes a first gate GE1, a first source SE1, and a first drain DE1. The first gate GE1 is connected to the first scan line SL1, the first source SE1 is connected to the data line DL, and the first drain DE1 is connected to the first node N1. The first transistor T1 can transfer a data voltage from the data line DL to the first node N1 based on a scan signal of the first scan line SL1.

[0097] The second transistor T2 includes a second gate GE2, a second source SE2, and a second drain DE2. The second gate GE2 is connected to the first scan line SL1, the second source SE2 is connected to the second node N2, and the second drain DE2 is connected to the third node N3. The second transistor T2 can short-circuit the sixth gate GE6 and the sixth drain DE6 of the sixth transistor T6, and the sixth transistor T6 can be diode-connected. In the diode connection, the gate and the drain are short-circuited so that the transistor works as a diode. At this time, the second transistor T2 forms a dual-gate structure with a low cut-off current to reduce the leakage current from the sixth gate GE6 of the sixth transistor T6. In addition, the second transistor T2 can be implemented by an oxide semiconductor transistor with a low cut-off current, but is not limited thereto.

[0098] The third transistor T3 includes a third gate GE3, a third source SE3, and a third drain DE3. The third gate GE3 is connected to the light emission control signal line EL, the third source SE3 is connected to the reference line RL, and the third drain DE3 is connected to the first node N1. The third transistor T3 can transfer the reference voltage from the reference line RL to the first node N1 based on the light emission control signal of the light emission control signal line EL, and keep the voltage of the second node N2 constant while the light emitting diode 130 emits light.

[0099] The fourth transistor T4 includes a fourth gate GE4, a fourth source SE4, and a fourth drain DE4. The fourth gate GE4 is connected to the light emission control signal line EL, the fourth source SE4 is connected to the third node N3, and the fourth drain DE4 is connected to the low potential power line VL2. The fourth transistor T4 can supply a low potential power voltage to the third node N3 based on the light emission control signal to allow a driving current to flow.

[0100] The fifth transistor T5 includes a fifth gate GE5, a fifth source SE5, and a fifth drain DE5. The fifth gate GE5 is connected to the second scan line SL2, the fifth source SE5 is connected to the reference line RL, and the fifth drain DE5 is connected to the third node N3. The fifth transistor T5 can supply a reference voltage to the third node N3 based on the scan signal of the second scan line SL2, and reset the sixth drain DE6 of the sixth transistor T6 as the third node using the reference voltage. At this time, although the fifth transistor T5 is shown in the drawings to have a dual-gate structure, the fifth transistor T5 can also be formed to have a single-gate structure, but is not limited thereto.

[0101] The sixth transistor T6 includes a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6. The sixth gate electrode GE6 is connected to the second node N2, the sixth source electrode SE6 is connected to the fourth node N4, and the sixth drain electrode DE6 is connected to the third node N3. The sixth transistor T6 is turned on to control the driving current flowing through the light emitting diode 130 and may also be referred to as a driving transistor.

[0102] The seventh transistor T7 includes a seventh gate electrode GE7, a seventh source electrode SE7, and a seventh drain electrode DE7. The seventh gate electrode GE7 is connected to the first scan line SL1, the seventh source electrode SE7 is connected to the high potential power line VL1, and the seventh drain electrode DE7 is connected to the fourth node N4. The seventh source electrode SE7 can transmit the high potential power voltage to the fourth node N4 based on the scan signal of the first scan line SL1, and suppress the light emission of the light emitting diode 130 while supplying the data voltage.

[0103] The first capacitor C1 includes a plurality of capacitor electrodes connected to the first node N1 and the second node N2. The first capacitor C1 can adjust the voltage of the second node N2 using coupling characteristics and fix the voltage applied to the sixth gate GE6 of the sixth transistor T6 while the light emitting diode 130 emits light to maintain a constant driving current.

[0104] The second capacitor C2 includes a plurality of capacitor electrodes connected to the second node N2 and the fourth node N4. In other words, the second capacitor C2 may be connected between the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6. The second capacitor C2 may be connected between the sixth gate GE6 and the first electrode 134 of the light emitting diode 130 as a cathode.

[0105] When the voltage in the first node N1 fluctuates, the voltage of the second node N2 also fluctuates. At this time, the second capacitor C2 connected in series with the first capacitor C1 can be coupled to the first capacitor C1, and the voltage of the first node N1 can be transmitted to the voltage of the second node N2 according to the capacitance ratio of the first capacitor C1 and the second capacitor C2. Therefore, the second capacitor C2 can be used to reduce the transmission rate of the data voltage from the first node N1 to the second node N2. In addition, when the light emitting diode 130 is configured as a micro LED having a large IV curve slope, the second capacitor C2 is used to reduce the transmission rate of the data voltage to display a more subtle grayscale.

[0106] The third capacitor C3 is a capacitor formed between the fourth node N4 and the high potential power line VL1, and may be a parasitic capacitor. That is, the third capacitor C3 may be a capacitor formed between the existing configuration without additionally forming a separate electrode. The third capacitor C3 increases the intrinsic capacitance in the light emitting diode 130 to emit light with higher brightness from the light emitting diode 130.

[0107] The third capacitor C3 may be formed between the high potential power line VL1, the configuration electrically connected to the high potential power line VL1, and the configuration electrically connected to the fourth node N4. For example, the fourth node N4 may be electrically connected to the first electrode 134 of the light emitting diode 130 to be described below, the sixth source electrode SE6 of the sixth transistor T6, the light shielding layer BSM, a portion of the reflection plate RF, the second connection electrode CE, etc. The high potential power line VL1 may be electrically connected to a portion of the reflection plate RF to be described below, the first connection electrode CE1, etc. In the sub-pixel SP, the area of ​​the configuration electrically connected to the fourth node N4 and the area of ​​the configuration electrically connected to the high potential power line VL1 are relatively large, so that the third capacitor C3 may be formed between them.

[0108] Next, let’s refer to Figure 5 and Figure 7, a light shielding layer BSM is disposed on the first substrate 110. The light shielding layer BSM blocks light incident on the sixth active layer ACT6 of the sixth transistor T6 as a driving transistor to reduce leakage current. For example, the light shielding layer BSM is disposed below the sixth active layer ACT6 of the sixth transistor T6 to block light incident on the sixth active layer ACT6. If light is irradiated onto the sixth active layer ACT6, leakage current is generated, which deteriorates the reliability of the transistor. Therefore, a light shielding layer BSM that blocks light is disposed on the first substrate 110 to improve the reliability of the sixth transistor T6. The light shielding layer BSM may be formed of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0109] The buffer layer 111 is disposed on the light shielding layer BSM. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 can be made of silicon oxide SiO x or silicon nitride SiN x The buffer layer 111 may be formed of a single layer or a double layer, but is not limited thereto. However, the buffer layer 111 may be omitted according to the type of the first substrate 110 or the type of the thin film transistor, but is not limited thereto.

[0110] A first transistor T1 including a first active layer ACT1 , a first gate electrode GE1 , a first source electrode SE1 , and a first drain electrode DE1 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111 .

[0111] First, the first active layer ACT1 of the first transistor T1 is disposed on the buffer layer 111. The first active layer ACT1 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0112] The gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer that electrically insulates the first active layer ACT1 from the first gate GE1, and may be made of silicon oxide SiO x or silicon nitride SiN x The single layer or double layer structure is not limited thereto.

[0113] The first gate GE1 is disposed on the gate insulating layer 112. The first gate GE1 is formed integrally with the first scan line SL1 to be electrically connected to the first scan line SL1. The first gate GE1 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0114] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the first gate electrode GE1. Contact holes through which the first source electrode SE1 and the first drain electrode DE1 are connected to the first active layer ACT1 may be formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, respectively. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers that protect components thereunder and may be made of silicon oxide SiO x or silicon nitride SiN x The single layer or double layer structure is not limited thereto.

[0115] The first source electrode SE1 and the first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the second interlayer insulating layer 114. The source electrode SE1 is integrally formed with the data line DL to be electrically connected to the data line DL, and the first drain electrode DE1 may be electrically connected to the 1-2 capacitor electrode C1b of the first capacitor C1. The first source electrode SE1 and the first drain electrode DE1 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0116] The second transistor T2 including the second active layer ACT2 , the second gate GE2 , the second source electrode SE2 , and the second drain electrode DE2 is disposed on the buffer layer 111 .

[0117] The second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0118] The gate insulating layer 112 is disposed on the second active layer ACT2, and the second gate GE2 is disposed on the gate insulating layer 112. The second gate GE2 is formed integrally with the first scan line SL1 to be electrically connected to the first scan line SL1. The second gate GE2 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0119] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second gate GE2, and the second source electrode SE2 and the second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the second interlayer insulating layer 114. The second source electrode SE2 is electrically connected to the gate electrode of the sixth transistor T6, wherein the gate electrode of the sixth transistor T6 is the 1-1 capacitor electrode C1a of the first capacitor C1. The second drain electrode DE2 is electrically connected to the fifth drain electrode DE5 of the fifth transistor T5 and the fourth source electrode SE4 of the fourth transistor T4. The second source electrode SE2 and the second drain electrode DE2 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the foregoing metals, but are not limited thereto.

[0120] The third transistor T3 including a third active layer ACT3 , a third gate GE3 , a third source electrode SE3 , and a third drain electrode DE3 is disposed on the buffer layer 111 .

[0121] The third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0122] The gate insulating layer 112 is disposed on the third active layer ACT3, and the third gate GE3 is disposed on the gate insulating layer 112. The third gate GE3 is formed integrally with the light emitting control signal line EL to be electrically connected to the light emitting control signal line EL. The third gate GE3 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0123] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the third gate electrode GE3, and the third source electrode SE3 and the third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the second interlayer insulating layer 114. The third source electrode SE3 is electrically connected to the fifth source electrode SE5 and the reference line RL, and the third drain electrode DE3 is electrically connected to the 1-2 capacitor electrode C1b of the first capacitor C1 and the first drain electrode DE1 of the first transistor T1. The third source electrode SE3 and the third drain electrode DE3 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0124] The fourth transistor T4 including a fourth active layer ACT4 , a fourth gate GE4 , a fourth source electrode SE4 , and a fourth drain electrode DE4 is disposed on the buffer layer 111 .

[0125] The fourth active layer ACT4 is disposed on the buffer layer 111. The fourth active layer ACT4 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0126] The gate insulating layer 112 is disposed on the fourth active layer ACT4, and the fourth gate GE4 is disposed on the gate insulating layer 112. The fourth gate GE4 is formed integrally with the light emission control signal line EL to be electrically connected to the light emission control signal line EL. The fourth gate GE4 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0127] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the fourth gate GE4, and the fourth source SE4 and the fourth drain DE4 electrically connected to the fourth active layer ACT4 are disposed on the second interlayer insulating layer 114. The fourth source SE4 is electrically connected to the fifth drain DE5 and the second drain DE2 of the fifth transistor T5, and the fourth drain DE4 is electrically connected to the low potential power line VL2. At this time, the low potential power line VL2 and the fourth drain DE4 can be integrally formed on the same layer using the same material. The fourth source SE4 and the fourth drain DE4 can be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but are not limited thereto.

[0128] The fifth transistor T5 including a fifth active layer ACT5 , a fifth gate GE5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 is disposed on the buffer layer 111 .

[0129] The fifth active layer ACT5 is disposed on the buffer layer 111. The fifth active layer ACT5 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0130] The gate insulating layer 112 is disposed on the fifth active layer ACT5, and the fifth gate GE5 is disposed on the gate insulating layer 112. The fifth gate GE5 is electrically connected to the second scan line SL2. The fifth gate GE5 may be integrally formed on the same layer with the second scan line SL2 using the same material. The fifth gate GE5 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0131] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the fifth gate electrode GE5, and the fifth source electrode SE5 and the fifth drain electrode DE5 electrically connected to the fifth active layer ACT5 are disposed on the second interlayer insulating layer 114. The fifth source electrode SE5 is connected to the reference line RL, and the fifth drain electrode DE5 is connected to the sixth drain electrode DE6, the fourth source electrode SE4, and the second drain electrode DE2. The fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0132] A sixth transistor T6 including a sixth active layer ACT6 , a sixth gate GE6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 is disposed on the buffer layer 111 .

[0133] The sixth active layer ACT6 is disposed on the buffer layer 111. The sixth active layer ACT6 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0134] The gate insulating layer 112 is disposed on the sixth active layer ACT6, and the sixth gate GE6 is disposed on the gate insulating layer 112. The sixth gate GE6 is electrically connected to the 1-1 capacitor electrode C1a of the first capacitor C1 and the second source SE2. The sixth gate GE6 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0135] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the sixth gate electrode GE6, and the sixth source electrode SE6 and the sixth drain electrode DE6 electrically connected to the sixth active layer ACT6 are disposed on the second interlayer insulating layer 114. The sixth source electrode SE6 is electrically connected to the 2-1 capacitor electrode C2a and the 2-3 capacitor electrode C2c of the second capacitor C2 and the first electrode 134 of the light emitting diode 130. The sixth drain electrode DE6 is electrically connected to the fifth drain electrode DE5, the fourth source electrode SE4, and the second drain electrode DE2. The sixth source electrode SE6 and the sixth drain electrode DE6 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but are not limited thereto.

[0136] The seventh transistor T7 including a seventh active layer ACT7 , a seventh gate GE7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 is disposed on the buffer layer 111 .

[0137] The seventh active layer ACT7 is disposed on the buffer layer 111. The seventh active layer ACT7 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0138] The gate insulating layer 112 is disposed on the seventh active layer ACT7, and the seventh gate GE7 is disposed on the gate insulating layer 112. The seventh gate GE7 is connected to the first scan line SL1. The seventh gate GE7 may be formed integrally with the first scan line SL1 to be electrically connected to the first scan line SL1. The seventh gate GE7 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0139] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the seventh gate electrode GE7, and the seventh source electrode SE7 and the seventh drain electrode DE7 electrically connected to the seventh active layer ACT7 are disposed on the second interlayer insulating layer 114. The seventh source electrode SE7 is electrically connected to the high potential power line VL1, and the seventh drain electrode DE7 is electrically connected to the first electrode 134 of the light emitting diode 130 and the 2-1 capacitor electrode C2a and the 2-3 capacitor electrode C2c of the second capacitor C2. The seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0140] The first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1th capacitor electrode C1a and a 1-2th capacitor electrode C1b.

[0141] First, the 1-1 capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1 capacitor electrode C1a may be integrally formed with the sixth gate GE6 of the sixth transistor T6. Therefore, the 1-1 capacitor electrode C1a may be electrically connected to the sixth gate GE6 and the second source SE2.

[0142] The 1-2 capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The 1-2 capacitor electrode C1b is disposed to overlap the 1-1 capacitor electrode C1a with the first interlayer insulating layer 113 between the 1-2 capacitor electrode C1b and the 1-1 capacitor electrode C1a. The 1-2 capacitor electrode C1b may be electrically connected to the first drain electrode DE1 and the third drain electrode DE3.

[0143] The second capacitor C2 is disposed on the first substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The second capacitor C2 includes a 2-1st capacitor electrode C2a as a lower capacitor electrode, a 2-2nd capacitor electrode C2b as a middle capacitor electrode, and a 2-3rd capacitor electrode C2c as an upper capacitor electrode.

[0144] The 2-1st capacitor electrode C2a is disposed on the substrate. The 2-1st capacitor electrode C2a extends from the light shielding layer BSM and may be formed integrally with the light shielding layer BSM. At this time, the 2-1st capacitor electrode C2a may be electrically connected to the sixth source electrode SE6 through a contact hole formed in the buffer layer 111 and the gate insulating layer 112. At this time, an intermediate electrode electrically connecting the 2-1st capacitor electrode C2a and the sixth source electrode SE6 may be disposed between the gate insulating layer 112 and the first interlayer insulating layer 113. However, the 2-1st capacitor electrode C2a and the sixth source electrode SE6 may be electrically connected without an intermediate electrode, but are not limited thereto.

[0145] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b extends from the sixth gate GE6 and may be disposed to overlap the 2-1st capacitor electrode C2a. The 2-2nd capacitor electrode C2b may be electrically connected to the sixth gate GE6 and the second source SE2 of the sixth transistor T6.

[0146] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3rd capacitor electrode C2c may be formed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3rd capacitor electrode C2c has an island pattern formed on the same layer as the 1-2nd capacitor electrode C1b using the same material. The first layer C2c1 may be disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113 between the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b.

[0147] The second layer C2c2 of the 2-3rd capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 extends from the sixth source electrode SE6 and may be connected to the first layer C2c1 through a contact hole of the second interlayer insulating layer 114.

[0148] The first scan line SL1, the second scan line SL2, and the light emission control signal line EL are disposed on the gate insulating layer 112. The first scan line SL1, the second scan line SL2, and the light emission control signal line EL may extend in a row direction and may be disposed along a plurality of sub-pixels SP disposed on the same row.

[0149] The first scan line SL1 is formed integrally with the first gate GE1, the second gate GE2 and the seventh gate GE7 to transmit the scan signal to the first transistor T1, the second transistor T2 and the seventh transistor T7, and turn on or off the first transistor T1, the second transistor T2 and the seventh transistor T7. The second scan line SL2 is formed integrally with the fifth gate GE5 to transmit the scan signal to the fifth transistor T5 and turn on or off the fifth transistor T5. The light emission control signal line EL is formed integrally with the third gate GE3 and the fourth gate GE4 to transmit the light emission control signal to the third transistor T3 and the fourth transistor T4, and turn on or off the third transistor T3 and the fourth transistor T4.

[0150] The reference line RL is disposed on the first interlayer insulating layer 113. The reference line RL extends in a row direction and may be disposed along a plurality of sub-pixels SP disposed on the same row. The reference line RL may be electrically connected to the fifth source electrode SE5 through a contact hole formed in the second interlayer insulating layer 114.

[0151] A gate driving line GVL may also be disposed on the first gate insulating layer 113. For example, a first gate power line VGHL may extend in a row direction on the first substrate 110 and may be disposed adjacent to the reference line RL. A second gate power line VGLL may extend upward in a row direction on the first substrate 110 and may be disposed adjacent to the first scan line SL1.

[0152] The data line DL, the high potential power line VL1, and the low potential power line VL2 are disposed on the second interlayer insulating layer 114. The data line DL, the high potential power line VL1, and the low potential power line VL2 may extend in a column direction and may be disposed along a plurality of subpixels SP disposed in the same column.

[0153] At the same time, although not shown in the drawings, the gate driver GD disposed in the gate drive area GA may also include a circuit for outputting a scan signal. For example, similar to the pixel circuit, the gate driver may include a plurality of gate drive transistors and / or capacitors. Here, the active layers of the plurality of gate drive transistors of the gate driver may be formed of semiconductor materials such as oxide semiconductors, amorphous silicon or polycrystalline silicon, but are not limited thereto. The active layers of the plurality of gate drive transistors may be formed of the same material as each other or of materials different from each other. In addition, the active layers of the plurality of gate drive transistors of the gate driver may be formed of the same material as the active layers of the various transistors of the pixel circuit, or of materials different from each other. In addition, the active layers of the plurality of transistors included in the pixel circuit may be formed of the same material as each other or of materials different from each other.

[0154] Reference Figure 7, the first passivation layer 115a is disposed on the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an insulating layer that protects components below the first passivation layer 115a, and may be made of, for example, silicon oxide SiO x or silicon nitride SiN x The present invention is formed of inorganic materials, but is not limited thereto.

[0155] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the sixth transistor T6. The first planarization layer 116a may be composed of a single layer or a double layer and may be formed of, for example, benzocyclobutene or acrylic organic material, but is not limited thereto.

[0156] Refer to Figure 6 and Figure 7 , the reflective plate RF is disposed in each of the plurality of sub-pixels SP on the first planarization layer 116a. The reflective plate RF is a configuration that reflects light emitted from the plurality of light-emitting diodes 130 above the first substrate 110, and may be formed to have a shape corresponding to each of the plurality of sub-pixels SP. One reflective plate RF may be arranged to cover most of the area of ​​one sub-pixel SP. The reflective plate RF may reflect light emitted from the light-emitting diode 130, and may also be used as an electrode that electrically connects the light-emitting diode 130 to the pixel circuit. Therefore, considering the light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy of the foregoing metals and a transparent conductive layer such as indium tin oxide, but the structure of the reflective plate RF is not limited thereto.

[0157] The reflection plate RF includes a first reflection plate RF1 corresponding to the first sub-pixel SP1, a second reflection plate RF2 corresponding to the second sub-pixel SP2, a third reflection plate RF3 corresponding to the third sub-pixel SP3, and a fourth reflection plate RF4 corresponding to the fourth sub-pixel SP4.

[0158] The first reflector RF1 includes a 1-1 reflector RF1a overlapping most of the first sub-pixel SP1 and a 1-2 reflector RF1b overlapping the red light emitting diode 130R of the first sub-pixel SP1.

[0159] The 1-1st reflector RF1a may reflect light emitted from the red light emitting diode 130R to above the red light emitting diode 130R. The 1-1st reflector RF1a may be electrically connected to the sixth source electrode SE6 of the sixth transistor T6 through the first contact hole CH1 of the first planarization layer 116a and the first passivation layer 115a. Therefore, the 1-1st reflector RF1a may electrically connect the sixth transistor T6 and the first electrode 134 of the red light emitting diode 130R.

[0160] The 1-2nd reflector RF1b may reflect light emitted from the red LED 130R to above the red LED 130R. The 1-2nd reflector RF1b may function as an electrode for electrically connecting the second electrode 135 of the red LED 130R and the high potential power line VL1.

[0161] The second reflector RF2 includes a 2-1st reflector RF2a overlapping most of the second sub-pixel SP2 and a 2-2nd reflector RF2b overlapping the red light emitting diode 130R of the second sub-pixel SP2.

[0162] The 2-1st reflector RF2a can reflect light emitted from the red LED 130R to above the red LED 130R. The 2-1st reflector RF2a is electrically connected to the sixth source SE6 of the sixth transistor T6 through the first contact hole CH1 to electrically connect the sixth transistor T6 and the first electrode 134 of the red LED 130R.

[0163] The 2-2nd reflective plate RF2b may function to reflect light emitted from the red light emitting diode 130R above the red light emitting diode 130R and electrically connect the second electrode 135 of the red light emitting diode 130R to the high potential power line VL1.

[0164] The third reflector RF3 may be formed as a third reflector RF3 overlapping the entire third sub-pixel SP3. The third reflector RF3 may reflect light emitted from the green light emitting diode 130G of the third sub-pixel SP3 to above the green light emitting diode 130G. The third reflector RF3 may electrically connect the sixth source electrode SE6 of the sixth transistor T6 and the first electrode 134 of the green light emitting diode 130G through the first contact hole CH1.

[0165] The fourth reflector RF4 may be formed as one fourth reflector RF4 overlapping the entire fourth sub-pixel SP4. The fourth reflector RF4 may reflect light emitted from the blue light emitting diode 130B of the fourth sub-pixel SP4 to above the blue light emitting diode 130B. The fourth reflector RF4 may electrically connect the sixth source electrode SE6 of the sixth transistor T6 and the first electrode 134 of the blue light emitting diode 130B through the first contact hole CH1.

[0166] At this time, the 1-1 reflecting plate RF1a, the 2-1 reflecting plate RF2a, the third reflecting plate RF3 and the fourth reflecting plate RF4 occupying most of the areas of the plurality of sub-pixels SP may be electrically connected to the first electrode 134 serving as the cathode of the light-emitting diode 130. When a defect occurs in a specific sub-pixel SP, the 1-1 reflecting plate RF1a, the 2-1 reflecting plate RF2a, the third reflecting plate RF3 and the fourth reflecting plate RF4 are connected to the 1-1 reflecting plate RF1a, the 2-1 reflecting plate RF2a, the third reflecting plate RF3 and the fourth reflecting plate RF4 of the adjacent sub-pixel SP. Therefore, the light-emitting diode 130 of the defective sub-pixel SP may be electrically connected to the sixth transistor T6 of the adjacent sub-pixel SP. Therefore, the reflecting plate RF of each sub-pixel SP is electrically connected to the sixth transistor T6 of the adjacent sub-pixel SP to repair the light-emitting diode 130 of the defective sub-pixel SP to operate normally. The following will refer to Figures 8 to 11B A repairing method of the defective sub-pixel SP using the 1-1th reflection plate RF1a, the 2-1th reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 is described in detail.

[0167] Meanwhile, although it has been described that the first sub-pixel SP1 and the second sub-pixel SP2 are formed with two reflection plates RF, and the third sub-pixel SP3 and the fourth sub-pixel SP4 are formed with one reflection plate RF, the reflection plate RF may be designed in various ways. For example, similar to the third sub-pixel SP3 and the fourth sub-pixel SP4, only one reflection plate RF may be provided in all the plurality of sub-pixels SP, or similar to the first sub-pixel SP1 and the second sub-pixel SP2, a plurality of reflection plates RF may be provided in all the sub-pixels, but the reflection plate is not limited thereto.

[0168] In addition, it has been described that the red light emitting diode 130R of each of the first sub-pixel SP1 and the second sub-pixel SP2 is electrically connected to the high potential power line VL1 through the 1-2 reflective plate RF1b and the 2-2 reflective plate RF2b. However, all the red light emitting diodes 130R, the green light emitting diodes 130G, and the blue light emitting diodes 130B may be individually connected to the high potential power line VL1 without the reflective plate RF, but are not limited thereto.

[0169] The second passivation layer 115b is disposed on the plurality of reflection plates RF. The second passivation layer 115b is an insulating layer that protects components below the second passivation layer 115b and may be made of silicon oxide SiO x or silicon nitride SiN x The single layer or double layer structure is not limited thereto.

[0170] The adhesive layer AD is disposed on the second passivation layer 115b. The adhesive layer AD is formed on the entire surface of the first substrate 110 to fix the light emitting diode 130 disposed on the adhesive layer AD. The adhesive layer AD may be formed of a light-curable photocurable adhesive material. For example, the adhesive layer AD may be formed of an acrylic material including a photoresist, but is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate 110 excluding the pad region where the first pad electrode PAD1 is disposed.

[0171] A plurality of light emitting diodes 130 are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. The light emitting diode 130 is an element that emits light by current, and may include a red light emitting diode 130R that emits red light, a green light emitting diode 130G that emits green light, and a blue light emitting diode 130B that emits blue light, and realizes light of various colors including white light through a combination thereof. For example, the light emitting diode 130 may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0172] A red light emitting diode 130R is provided in each of the first sub-pixel SP1 and the second sub-pixel SP2, a pair of green light emitting diodes 130G is provided in the third sub-pixel SP3, and a pair of blue light emitting diodes 130B is provided in the fourth sub-pixel SP4. That is, two red light emitting diodes 130R, two green light emitting diodes 130G and two blue light emitting diodes 130B can be provided in one pixel PX. At this time, the two red light emitting diodes 130R are respectively connected to the sixth transistor T6 of the first sub-pixel SP1 and the second sub-pixel SP2 to be driven separately. On the contrary, a pair of green light emitting diodes 130G of the third sub-pixel SP3 and a pair of blue light emitting diodes 130B of the fourth sub-pixel SP4 are connected in parallel to the sixth transistor T6 to be driven.

[0173] The plurality of light emitting diodes 130 include a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 , and an encapsulation layer 136 .

[0174] The first semiconductor layer 131 is disposed on the adhesive layer AD, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0175] The light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 is supplied with holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. The light emitting layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0176] The first electrode 134 is disposed on the first semiconductor layer 131. The first electrode 134 is an electrode electrically connecting the sixth transistor T6 and the first semiconductor layer 131. In this case, the first semiconductor layer 131 is a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be disposed on the top surface of the first semiconductor layer 131 exposed from the light emitting layer 132 and the second semiconductor layer 133. The first electrode 134 may be formed of a conductive material such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy of the foregoing metals), but is not limited thereto.

[0177] The second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 may be disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode electrically connecting the high potential power line VL1 and the second semiconductor layer 133. In this case, the second semiconductor layer 133 is a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be formed of a conductive material such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy of the foregoing metals), but is not limited thereto.

[0178] Next, an encapsulation layer 136 is provided to surround the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation layer 136 is formed of an insulating material to protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In the encapsulation layer 136, contact holes exposing the first electrode 134 and the second electrode 135 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 134 and the second electrode 135.

[0179] At the same time, a portion of the side of the first semiconductor layer 131 may be exposed from the encapsulation layer 136. The light emitting diode 130 manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode 130 from the wafer, a portion of the encapsulation layer 136 may be torn. For example, during the process of separating the light emitting diode 130 from the wafer, a portion of the encapsulation layer 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting diode 130 is torn. Therefore, a portion of the lower side of the first semiconductor layer 131 may be exposed to the outside. However, although the lower portion of the light emitting diode 130 is exposed from the encapsulation layer 136, after forming the second planarization layer 116b and the third planarization layer 116c covering the side of the first semiconductor layer 131, the first connection electrode CE1 and the second connection electrode CE2 are also formed. Therefore, the short circuit problem can be reduced.

[0180] Next, the second planarization layer 116 b and the third planarization layer 116 c are disposed on the adhesive layer AD and the light emitting diode 130 .

[0181] The second planarization layer 116b overlaps a portion of the side of the plurality of light emitting diodes 130 to fix and protect the plurality of light emitting diodes 130. The second planarization layer 116b may be formed using a half-tone mask. Therefore, the second planarization layer 116b may be formed to have a step.

[0182] Specifically, a portion of the second planarization layer 116b that is relatively adjacent to the light emitting diode 130 may be formed to have a smaller thickness, and a portion that is away from the light emitting diode 130 may be formed to have a larger thickness. A portion of the second planarization layer 116b that is adjacent to the light emitting diode 130 may be provided to surround the light emitting diode 130, and may also be in contact with the side of the light emitting diode 130. Therefore, during the process of separating the light emitting diode 130 from the wafer to transfer to the display panel PN, the torn portion of the encapsulation layer 136 that protects the side of the first semiconductor layer 131 of the light emitting diode 130 may be covered by the second planarization layer 116b. By doing so, the contact and short circuit problems of the connection electrodes CE1 and CE2 with the first semiconductor layer 131 may be suppressed later.

[0183] The third planarization layer 116c is formed to cover the second planarization layer 116b and the upper portion of the light emitting diode 130, and a contact hole exposing the first electrode 134 and the second electrode 135 of the light emitting diode 130 may be formed. The first electrode 134 and the second electrode 135 of the light emitting diode 130 are exposed from the third planarization layer 116c, and the third planarization layer 116c is partially disposed in a region between the first electrode 134 and the second electrode 135 to reduce a short circuit problem. The second planarization layer 116b and the third planarization layer 116c may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0184] Meanwhile, the third planarization layer 116c may cover only the light emitting diode 130 and the region adjacent to the light emitting diode 130. The third planarization layer 116c may be disposed in the region of the sub-pixel SP surrounded by the bank BB, and may be disposed in an island shape. The bank BB is disposed in a portion of the top surface of the second planarization layer 116b, and the third planarization layer 116c may be disposed in another portion of the top surface of the second planarization layer 116b.

[0185] The first connection electrode CE1 and the second connection electrode CE2 are disposed on the third planarization layer 116c. The first connection electrode CE1 is an electrode that electrically connects the second electrode 135 of the light emitting diode 130 to the high potential power line VL1. The first connection electrode CE1 may be electrically connected to the second electrode 135 of the light emitting diode 130 through a contact hole formed in the third planarization layer 116c.

[0186] The second connection electrode CE2 is an electrode that electrically connects the first electrode 134 of the light emitting diode 130 and the sixth transistor T6. The second connection electrode CE2 may be connected to the 1-1 reflection plate RF1a, the 2-1 reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 of each of the plurality of sub-pixels SP through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. At this time, the 1-1 reflection plate RF1a, the 2-1 reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 are also connected to the sixth source electrode SE6 of the sixth transistor T6, so that the sixth source electrode SE6 of the sixth transistor T6 and the first electrode 134 of the light emitting diode 130 may be electrically connected to each other.

[0187] Meanwhile, the first electrode 134, the second connection electrode CE2 and the reflection plate RF are electrically connected to the sixth source SE6 of the sixth transistor T6. However, the first electrode 134, the second connection electrode CE2 and the reflection plate RF may be connected to the sixth drain DE6 of the sixth transistor T6, but are not limited thereto.

[0188] The levee BB is disposed on the first connection electrode CE1, the second connection electrode CE2, and the second planarization layer 116b exposed from the third planarization layer 116c. The levee BB may be disposed to be spaced apart from the light emitting diode 130 at a predetermined interval and to overlap at least partially with the reflective plate RF. For example, the levee BB may cover a portion of the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b. In addition, the levee BB may be disposed on the second planarization layer 116b at a predetermined interval from the light emitting diode 130. In this case, the levee BB and the third planarization layer 116c may be spaced apart from each other on a portion of the second planarization layer 116b having a smaller thickness. That is, the end of the levee BB and the end of the third planarization layer 116c may be disposed on a portion of the second planarization layer 116b having a smaller thickness formed by a halftone mask process to be spaced apart from each other. The levee BB may be formed of an opaque material to reduce color mixing between a plurality of sub-pixels SP, and may be formed of a black resin, for example, but is not limited thereto.

[0189] Meanwhile, the thickness of the portion of the bank BB formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b and covering a portion of the second connection electrode CE2 and the thickness of the portion disposed on the second planarization layer 116b may be different from each other. Specifically, when the portion of the bank BB covers a portion of the second connection electrode CE2 formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b, since the contact hole is formed from the second passivation layer 115b to the third planarization layer 116c, the bank BB may be disposed below the light emitting diode 130, that is, disposed lower than the light emitting diode 130. Therefore, the thickness of the portion of the bank BB covering a portion of the second connection electrode CE2 formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b may be greater than the thickness of the portion of the bank BB disposed on the second planarization layer 116b.

[0190] The first protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The first protective layer 117 is a layer that protects components below the first protective layer 117. The first protective layer 117 may be composed of a single layer or a double layer, and is formed of, for example, benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic organic material, but is not limited thereto.

[0191] A plurality of first pad electrodes PAD1 are disposed in the first pad area PA1 and the second pad area PA2 of the first substrate 110. Each of the plurality of first pad electrodes PAD1 may be composed of a plurality of conductive layers. For example, each of the plurality of first pad electrodes PAD1 includes a first conductive layer PE1a, a second conductive layer PE1b, and a third conductive layer PE1c.

[0192] First, a first conductive layer PE1a is disposed on the second interlayer insulating layer 114. The first conductive layer PE1a may be formed of the same conductive material as the sixth source electrode SE6 and the sixth drain electrode DE6, and may be formed of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0193] The first passivation layer 115a is disposed on the first conductive layer PE1a, and the second conductive layer PE1b is disposed on the first passivation layer 115a. The second conductive layer PE1b may be formed of the same conductive material as the reflective plate RF, and may be formed of, for example, silver (Ag), aluminum (Al), molybdenum (Mo), or an alloy thereof, but is not limited thereto.

[0194] The third conductive layer PE1c is disposed on the second conductive layer PE1b. The third conductive layer PE1c may be formed of the same conductive material as the first and second connection electrodes CE1 and CE2, and for example, of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0195] At this time, although not shown in the drawings, a portion of the plurality of conductive layers of the first pad electrode PAD1 is electrically connected to the plurality of wirings on the first substrate 110 to supply various signals to the plurality of wirings and the plurality of sub-pixels SP. For example, the first conductive layer PE1a and / or the second conductive layer PE1b of the first pad electrode PAD1 are connected to the data line DL, the high potential power line VL1, and the low potential power line VL2 provided in the display area AA to transmit signals to the data line DL, the high potential power line VL1, and the low potential power line VL2.

[0196] The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers may be disposed together under the first pad electrode PAD1. The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers are disposed under the first pad electrode PAD1 to adjust the step of the first pad electrode PAD1. For example, the buffer layer 111, the gate insulating layer 112, the first metal layer ML1, the first interlayer insulating layer 113, and the second metal layer ML2 may be sequentially disposed between the first pad electrode PAD1 and the first substrate 110. The first metal layer ML1 may be formed of the same conductive material as the sixth gate GE6, and the second metal layer ML2 may be formed of the same conductive material as the 1-2 capacitor electrode C1b. However, the plurality of insulating layers, the first metal layer ML1, and the second metal layer ML2 under the first pad electrode PAD1 may be omitted according to the design and are not limited thereto.

[0197] The second substrate 120 is disposed below the first substrate 110. The second substrate 120 is a substrate that supports components disposed below the display device 100 and may be an insulating substrate. For example, the second substrate 120 may be formed of glass or resin. In addition, the second substrate 120 may include a polymer or plastic. The second substrate 120 may be formed of the same material as the first substrate 110. In some exemplary embodiments, the second substrate 120 may be formed of a plastic material having flexibility.

[0198] The bonding layer BDL is disposed between the first substrate 110 and the second substrate 120. The bonding layer BDL may be formed of a material that is cured by various curing methods to bond the first substrate 110 and the second substrate 120. The bonding layer BDL may be disposed only in a partial region between the first substrate 110 and the second substrate 120, or may be disposed in the entire region.

[0199] A plurality of second pad electrodes PAD2 are disposed on the back surface of the second substrate 120. The plurality of second pad electrodes PAD2 are electrodes that transmit signals from a driving part disposed on the back surface of the second substrate 120 to a plurality of side lines SRL and a plurality of first pad electrodes PAD1 and a plurality of wirings on the first substrate 110. The plurality of second pad electrodes PAD2 are disposed in an end portion of the second substrate 120 located in the non-display area NA to be electrically connected to the side line SRL covering the end portion of the second substrate 120.

[0200] At this time, a plurality of second pad electrodes PAD2 may also be arranged to correspond to the first pad area PA1 and the second pad area PA2. A plurality of first pad electrodes PAD1 may be arranged to correspond to the plurality of second pad electrodes PAD2, respectively, and then the first pad electrodes PAD1 and the second pad electrodes PAD2 overlapping each other may be electrically connected through the side line SRL.

[0201] Each of the plurality of second pad electrodes PAD2 includes a plurality of conductive layers. For example, each of the plurality of second pad electrodes PAD2 includes a fourth conductive layer PE2a, a fifth conductive layer PE2b, and a sixth conductive layer PE2c.

[0202] First, the fourth conductive layer PE2a is disposed under the second substrate 120. The fourth conductive layer PE2a may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0203] The fifth conductive layer PE2b is disposed under the fourth conductive layer PE2a. The fifth conductive layer PE2b may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0204] The sixth conductive layer PE2c is disposed under the fifth conductive layer PE2b. The sixth conductive layer PE2c may be formed of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0205] The second protective layer 121 is disposed in the remaining area of ​​the second substrate 120. The second protective layer 121 may protect various wirings and driving components formed on the second substrate 120. The second protective layer 121 may be composed of a single layer or a double layer, and may be formed of, for example, benzocyclobutene, light-transmitting epoxy resin, photoresist, or acrylic organic insulating material, but is not limited thereto.

[0206] Although not shown in the drawings, a driving component including a plurality of flexible films and a printed circuit board may also be provided on the back side of the second substrate 120. The plurality of flexible films are components in which various components such as a data driver IC are provided on a base film having ductility to supply signals to a plurality of sub-pixels SP. The printed circuit board is a component electrically connected to the plurality of flexible films to supply signals to the driver IC. On the printed circuit board, various components for supplying various signals to the driver IC may be provided.

[0207] For example, the fourth conductive layer PE2a and / or the fifth conductive layer PE2b of the second pad electrode PAD2 extend to a plurality of flexible films disposed on the back surface of the second substrate 120 to be electrically connected to the plurality of flexible films. The plurality of flexible films may supply various signals to the plurality of side lines SRL, the plurality of first pad electrodes PAD1, the plurality of wirings, and the plurality of sub-pixels SP through the second pad electrode PAD2. Therefore, the signal from the driving component may be transmitted to the plurality of wirings and the plurality of sub-pixels SP on the front surface of the first substrate 110 through the plurality of second pad electrodes PAD2 of the second substrate 120, the side lines SRL, and the plurality of first pad electrodes PAD1 of the first substrate 110.

[0208] Next, a plurality of side lines SRL are disposed on the side surfaces of the first substrate 110 and the second substrate 120. The plurality of side lines SRL may electrically connect a plurality of first pad electrodes PAD1 formed on the top surface of the first substrate 110 and a plurality of second pad electrodes PAD2 formed on the back surface of the second substrate 120. The plurality of side lines SRL may be disposed to surround the side surfaces of the display device 100. Each of the plurality of side lines SRL may cover the first pad electrode PAD1 located at the end of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the second pad electrode PAD2 located at the end of the second substrate 120. For example, the plurality of side lines SRL may be formed by a pad printing method using, for example, a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0209] A side insulating layer 140 covering the plurality of side lines SRL is provided. The side insulating layer 140 may be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the back surface of the second substrate 120 to cover the side lines SRL. The side insulating layer 140 may protect the plurality of side lines SRL.

[0210] Meanwhile, when the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected from the plurality of side lines SRL or light emitted from the light emitting diode 130 is reflected from the plurality of side lines SRL and is visibly recognized by the user. Therefore, the side insulating layer 140 is configured to contain a black material to suppress the reflection of external light. For example, the side insulating layer 140 can be formed by a pad printing method using an insulating material containing a black material (e.g., black ink).

[0211] A sealing member 150 is provided to cover the side insulating layer 140. The sealing member 150 is provided to surround the side of the display device 100 to protect the display device 100 from external impact, moisture, oxygen, etc. For example, the sealing member 150 may be formed of polyimide (PI), polyurethane, epoxy resin, acrylic-based insulating material, etc., but is not limited thereto.

[0212] The optical film MF is disposed on the sealing member 150, the side insulating layer 140, and the first protective layer 117. The optical film MF may be a functional film that realizes a higher quality image while protecting the display device 100. For example, the optical film MF may be an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an organic light emitting diode transmittance controllable film, a polarizer, etc., but is not limited thereto.

[0213] Meanwhile, the edge of the sealing member 150 and the edge of the optical film MF may be arranged on the same line. During the manufacturing process of the display device 100, the optical film ML having a larger size is attached above the first substrate 110, and the sealing member 150 covering the side insulating layer 140 may be formed. Thereafter, a laser is irradiated on the sealing member 150 and the optical film MF to cut a portion of the sealing member 150 and the optical film MF corresponding to the edge of the display device 100. Therefore, the size of the display device 100 is adjusted by the peripheral cutting process of the sealing member 150, and the edges of the optical film MF and the display device 100 may be formed to be flat.

[0214] In the following, reference will be made to Figures 8 to 11B A repair method of the display device 100 according to an exemplary embodiment of the present disclosure is described.

[0215] Figure 8 is a circuit diagram for explaining a repair process of a sub-pixel according to an exemplary embodiment of the present disclosure. Fig.9A and Fig. 9B is a cross-sectional view of a second capacitor of a display device according to an exemplary embodiment of the present disclosure. Fig.10 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Fig.11A and Fig. 11B It is along Fig.10 For ease of description, no Fig.9A , Fig. 9B , Fig.11A and Fig. 11B 1 and 12. In addition, among the plurality of reflectors RF, the 1-1 reflector RF1a, the 2-1 reflector RF2a, the third reflector RF3, and the fourth reflector RF4 connected to the first electrode 134 of the light emitting diode 130 are represented by reflectors RF(N) and RF(M).

[0216] Hereinafter, when a defect occurs in a subpixel SP(N) set in the Nth row among multiple rows, a description will be given assuming that the subpixel SP(M) in the Mth row adjacent to the Nth row is used to repair the subpixel SP(N) in the Nth row.

[0217] First, when a defect occurs in a specific sub-pixel SP, a dark spot or bright spot problem may occur. For example, when a defect occurs in the light-emitting diode 130, a short circuit problem may occur in multiple transistors and multiple capacitors due to foreign matter or static electricity. When the transistor is abnormally driven, a dark spot problem in which the light-emitting diode 130 does not emit light or a bright spot problem in which the light-emitting diode 130 continues to emit light may occur. When a defect occurs in a pixel circuit including multiple transistors or multiple capacitors, the light-emitting diode 130 and the defective pixel circuit are separated so that the light-emitting diode 130 does not emit light through the defective pixel circuit. In addition, the pixel circuit and the light-emitting diode 130 of the adjacent sub-pixel SP are electrically connected to drive the light-emitting diode 130 normally.

[0218] Specifically, when a defective sub-pixel SP is generated, repair may be performed in the order of process (1), process (2), and process (3). Process (1) is a process of darkening the defective sub-pixel SP by performing a welding process on the second capacitor C2. In process (1), the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c of the second capacitor C2 are connected to each other to short-circuit the sixth gate electrode GE6 and the sixth source electrode SE6 of the sixth transistor T6, and the defective sub-pixel SP may be darkened. Process (2) is a process of connecting the light emitting diode 130 and the reflection plate RF of the darkened defective sub-pixel SP to the reflection plate RF and the pixel circuit of the adjacent normal sub-pixel SP by performing a welding process on the first connection pattern CP1 and the second connection pattern CP2. The light emitting diode 130 of the defective sub-pixel SP is electrically connected to the pixel circuit of the normal sub-pixel SP through process (2) to drive the light emitting diode 130 of the defective sub-pixel SP normally. Step (3) is a step of separating the light emitting diode 130 of the defective sub-pixel SP from the pixel circuit of the normal sub-pixel SP when an error occurs again after the defective sub-pixel SP is repaired. The sub-pixel SP with the error can be dimmed again through step (3).

[0219] First, refer to Figures 8 to 9B , when a defect occurs in the sub-pixel SP(N) in the Nth row, the process (1) of darkening the sub-pixel SP(N) in the Nth row by performing a welding process on the second capacitor C2 may be performed. Through the process (1), the driving current may not flow through the light emitting diode 130 of the sub-pixel SP(N) in the Nth row. Specifically, the dark spot problem in which the light emitting diode 130 does not emit light or the bright spot problem in which the light emitting diode continues to emit light may be caused by a defective pixel circuit. Therefore, the welding process may be performed to short-circuit a portion of the pixel circuit so as to prevent the defective pixel circuit from abnormally driving the light emitting diode 130.

[0220] Reference Fig.9A , the laser LS is irradiated onto the second capacitor C2 to connect the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6 serving as a driving transistor.

[0221] The second capacitor C2 is a capacitor connected between the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6 used as a driving transistor. The second capacitor C2 includes a 2-2 capacitor electrode C2b connected to the sixth gate GE6 and a 2-1 capacitor electrode C2a and a 2-3 capacitor electrode C2c respectively disposed above and below the 2-2 capacitor electrode C2b and connected to the sixth source SE6. Insulating layers 111, 112, and 113 are disposed between the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b and between the 2-2 capacitor electrode C2b and the 2-3 capacitor electrode C2c, so that the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c are spaced apart from each other. However, the present disclosure is not limited thereto. For example, the 2-1 capacitor electrode C2a may be omitted, and the second capacitor C2 may include only the 2-2 capacitor electrode C2b connected to the sixth gate GE6 and the 2-3 capacitor electrode C2c connected to the sixth source SE6.

[0222] Reference Fig. 9B , when the welding process is performed by irradiating the laser LS onto the second capacitor C2 electrode, the buffer layer 111 and the gate insulating layer 112 between the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b, and the first interlayer insulating layer 113 between the 2-2 capacitor electrode C2b and the 2-3 capacitor electrode C2c are opened. In addition, the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c are partially melted for connection. In this case, the sixth source SE6 and the sixth gate GE6 of the sixth transistor T6 may be short-circuited by the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c connected to each other by the welding process. Therefore, the voltage difference Vgs between the sixth gate GE6 and the sixth source SE6 may be always 0V, and the sixth transistor T6 may no longer be turned on.

[0223] Therefore, a welding process is performed on the second capacitor C2 of the defective sub-pixel SP(N) of the Nth row to connect the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c of the second capacitor C2, and the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6 are short-circuited. Therefore, the erroneous operation of the light emitting diode 130 caused by the defective pixel circuit, specifically, the bright spot problem, can be suppressed.

[0224] Refer to Figure 8 and Fig.10After the process (1) of welding the second capacitor C2 is completed, the process (2) of electrically connecting the first electrode 134 of the light emitting diode 130 of the sub-pixel SP(N) of the Nth row as the defective sub-pixel SP and the first electrode 134 of the light emitting diode 130 of the sub-pixel SP(M) of the Mth row as the normal sub-pixel SP can be performed. The light emitting diode 130 of the sub-pixel SP(N) of the Nth row is electrically connected to the sixth transistor T6 of the sub-pixel SP(M) of the Mth row to drive the light emitting diode 130 of the defective sub-pixel SP using the pixel circuit of the sub-pixel SP(M) of the Mth row. Therefore, the light emitting diode 130 in the Nth row and the light emitting diode 130 in the Mth row are connected in parallel to the circuit of the sub-pixel SP(M) of the Mth row to be driven together.

[0225] First, the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3, and the fourth reflector RF4 are arranged to cover most of the sub-pixel SP. Therefore, the outermost portions of the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3, and the fourth reflector RF4 may be arranged to be adjacent to the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3, and the fourth reflector RF4 of the adjacent sub-pixel SP, respectively. For example, the third reflector RF3(N) of the sub-pixel SP(N) of the Nth row and the third reflector RF3(M) of the Mth row may be opposite to each other at the boundary of the sub-pixel SP.

[0226] At this time, when all of the plurality of sub-pixels SP are normal sub-pixels SP, the reflection plate RF of each of the plurality of sub-pixels SP may be electrically insulated from the reflection plate RF of an adjacent sub-pixel SP.

[0227] However, when a portion of the sub-pixels SP among the plurality of sub-pixels SP is a defective sub-pixel SP, the reflection plate RF of the defective sub-pixel SP and the reflection plate RF of the sub-pixel SP adjacent to the defective sub-pixel SP may be electrically connected.

[0228] Specifically, the reflective plate RF(N) of the sub-pixel SP(N) in the Nth row and the reflective plate RF(M) of the sub-pixel SP(M) in the Mth row adjacent to each other are electrically connected to respectively electrically connect the first electrodes 134 of the light-emitting diodes 130 of the sub-pixel SP(N) in the Nth row and the sub-pixel SP(M) in the Mth row. Figures 4 to 7As described above, the 1-1 reflecting plate RF1a, the 2-1 reflecting plate RF2a, the third reflecting plate RF3, and the fourth reflecting plate RF4 of the plurality of sub-pixels SP may be electrically connected to the first electrode 134 of the light emitting diode 130. Therefore, the sub-pixel SP(N) of the Nth row may be repaired by connecting the 1-1 reflecting plate RF1a, the 2-1 reflecting plate RF2a, the third reflecting plate RF3, and the fourth reflecting plate RF4 of each of the normal sub-pixel SP(M) of the Mth row and the defective sub-pixel SP(N) of the Nth row.

[0229] For example, when the first sub-pixel SP1(N) of the Nth row is defective, the 1-1 reflector RF1a(N) of the Nth row may be electrically connected to the 1-1 reflector RF1a(M) of the Mth row. When the second sub-pixel SP2(N) of the Nth row is defective, the 2-1 reflector RF2a(N) of the Nth row may be electrically connected to the 2-1 reflector RF2a(M) of the Mth row. When the third sub-pixel SP3(N) of the Nth row is defective, the third reflector RF3(N) of the Nth row may be electrically connected to the third reflector RF3(M) of the Mth row. Finally, when the fourth sub-pixel SP4(N) of the Nth row is defective, the fourth reflector RF4(N) of the Nth row may be electrically connected to the fourth reflector RF4(M) of the Mth row.

[0230] Reference Fig.11A and Fig. 11B The first connection pattern CP1 and the second connection pattern CP2 are provided to electrically connect the reflection plate RF(N) of the Nth row and the reflection plate RF(M) of the Mth row. The reflection plate RF(N) of the sub-pixel SP(N) of the Nth row and the reflection plate RF(M) of the sub-pixel SP(M) of the Mth row can be connected by performing a welding process of the first connection pattern CP1 and the second connection pattern CP2.

[0231] The first connection pattern CP1 is an electrode electrically connected to each of the 1-1st reflection plate RF1a(N), the 2-1st reflection plate RF2a(N), the third reflection plate RF3(N), and the fourth reflection plate RF4(N) of the sub-pixel SP(N) of the Nth row. The second connection pattern CP2 is an electrode electrically connected to each of the 1-1st reflection plate RF1a(M), the 2-1st reflection plate RF2a(M), the third reflection plate RF3(M), and the fourth reflection plate RF4(M) of the Mth row.

[0232] The first connection pattern CP1 may be connected to the lower portions of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4. The second connection pattern CP2 may be connected to the upper portions of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4. Thus, one reflection plate RF may be connected to both the first connection pattern CP1 connected to the lower portion and the second connection pattern CP2 connected to the upper portion.

[0233] Each of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 may include a protrusion RFP protruding toward the first connection pattern CP1 and the second connection pattern CP2. For example, each of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 may include a protrusion RFP protruding from each of the lower edge and the upper edge toward the first connection pattern CP1 and the second connection pattern CP2. The protrusion RFP of each of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 may be connected to the first connection pattern CP1 and the second connection pattern CP2 exposed from the first planarization layer 116a and the first passivation layer 115a.

[0234] At this time, the first connection pattern CP1 of each of the plurality of sub-pixels SP may partially overlap with the second connection pattern CP2 of the sub-pixel SP of the adjacent row. For example, the first connection pattern CP1 connected to the reflector RF(N) of the Nth row and the second connection pattern CP2 connected to the reflector RF(M) of the Mth row may be arranged to overlap at the boundary of the Nth row and the Mth row. The laser LS is irradiated in the welding area WA where the first connection pattern CP1 overlaps with the second connection pattern CP2 to connect the reflector RF of the adjacent sub-pixels SP.

[0235] Reference Fig.11A, the first connection pattern CP1 is disposed on the first interlayer insulating layer 113 in the sub-pixel SP(N) of the Nth row. The first connection pattern CP1 includes a 1-1 connection pattern CP1a and a 1-2 connection pattern CP1b. The 1-1 connection pattern CP1a is disposed on the first interlayer insulating layer 113 and may be formed on the same layer with the reference line RL using the same material. The 1-2 connection pattern CP1b is disposed on the second interlayer insulating layer 114 and is connected to the 1-1 connection pattern CP1a through a contact hole formed on the second interlayer insulating layer 114. The 1-2 connection pattern CP1b is partially exposed from the first passivation layer 115a and the first planarization layer 116a to be electrically connected to any one of the 1-1 reflection plate RF1a, the 2-1 reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 on the first planarization layer 116a. The 1-2 connection pattern CP1b may be formed of the same material on the same layer with the source and drain of a plurality of transistors having the same material.

[0236] The second connection pattern CP2 is disposed on the first substrate 110 in the sub-pixel SP(M) of the Mth row. The second connection pattern CP2 includes a 2-1st connection pattern CP2a, a 2-2nd connection pattern CP2b, and a 2-3rd connection pattern CP2c. The 2-1st connection pattern CP2a is disposed on the first substrate 110 and may be formed on the same layer with the light shielding layer BSM using the same material. The 2-2nd connection pattern CP2b is disposed on the gate insulating layer 112 and may be connected to the 2-1st connection pattern CP2a through contact holes of the buffer layer 111 and the gate insulating layer 112. The 2-2nd connection pattern CP2b may be formed on the same layer with the gates of a plurality of transistors using the same material. The 2-3rd connection pattern CP2c is disposed on the second interlayer insulating layer 114 and is connected to the 2-2nd connection pattern CP2b through contact holes formed on the second interlayer insulating layer 114. The 2-3rd connection pattern CP2c is partially exposed from the first passivation layer 115a and the first planarization layer 116a to be electrically connected to any one of the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 on the first planarization layer 116a. The 2-3rd connection pattern CP2c can be formed on the same layer with the source and drain of a plurality of transistors using the same material.

[0237] The first connection pattern CP1 and the second connection pattern CP2 at least partially overlap to form a welding area WA. The first connection pattern CP1 and the second connection pattern CP2 may be arranged to overlap at the boundary of the Nth row and the Mth row. For example, the 2-1st connection pattern CP2a, the buffer layer 111, the gate insulating layer 112, the 2-2nd connection pattern CP2b, the first interlayer insulating layer 113, the 1-2nd connection pattern CP1b and the second interlayer insulating layer 114 are sequentially arranged on the first substrate 110 at the boundary of the Nth row and the Mth row. The 1-2nd connection pattern CP1b and the 2-3rd connection pattern CP2c, which are the top layers of the connection pattern, may be arranged to be spaced apart from the welding area WA at the boundary of the Nth row and the Mth row. Therefore, the 1-1st connection pattern CP1a of the first connection pattern CP1 overlaps with the 2-1st connection pattern CP2a and the 2-2nd connection pattern CP2b of the second connection pattern CP2 to form a welding area WA.

[0238] At least a portion of the plurality of insulating layers formed on the first and second connection patterns CP1 and CP2 overlapping the welding area WA may be opened. For example, an opening is formed in a portion of the first planarization layer 116a overlapping the welding area WA so that the first passivation layer 115a under the first planarization layer 116a may be exposed.

[0239] The opening overlapping the welding area WA may be formed only in one of the adhesive layer AD and the second planarization layer 116b formed on the first planarization layer 116a. If a dam BB is formed on the second planarization layer 116b while an opening is formed on both the adhesive layer AD and the second planarization layer 116b, the depth of the opening on the welding area WA is large, making it impossible to properly remove the dam BB from the lower part of the opening. Therefore, a residual film may be formed. In this case, energy loss of the laser LS irradiated into the welding area WA in the dam BB formed by the black material may be caused. Therefore, when the residual film of the dam BB exists, in order to perform the welding process of the first connection pattern CP1 and the second connection pattern CP2, it is necessary to irradiate the laser LS with a higher intensity. Therefore, the periphery of the welding area WA may be damaged by the laser LS with increased intensity. Therefore, the opening corresponding to the welding area WA is formed only in one of the adhesive layer AD and the second planarization layer 116b to form an opening with a smaller depth and reduce the residual film of the dam BB in the opening. Therefore, despite the Fig.11A and Fig. 11B 2 shows that the opening is formed in the second planarization layer 116 b , the opening may also be formed in the adhesive layer AD, and the second planarization layer 116 b may be formed on the welding area WA, but is not limited thereto.

[0240] An opening overlapping the welding area WA may be formed in the dam BB. As described above, the dam BB may be formed of a black material, and when the dam BB covers the welding area WA, it may be difficult to normally irradiate the laser LS onto the welding area WA. Therefore, an opening is formed in the dam BB formed on the first connection pattern CP1 and the second connection pattern CP2 to smoothly irradiate the laser LS onto the welding area WA.

[0241] At the same time, despite Fig.11A and Fig. 11B 4 shows at least a portion of the opening of the first passivation layer 115 a overlapping the welding area WA, but the present disclosure is not limited thereto.

[0242] Next, refer to Fig.11A , a process (2) of connecting the first connection pattern CP1 and the second connection pattern CP2 by irradiating the laser LS onto the welding area WA may be performed. When the welding process is performed, at least the first interlayer insulating layer 113 of the welding area WA, the gate insulating layer 112, and the first interlayer insulating layer 113 of the buffer layer 111 are opened, and the first connection pattern CP1 and the second connection pattern CP2 may be electrically connected.

[0243] Therefore, the reflector RF(N) of the sub-pixel SP(N) of the Nth row can be electrically connected to the reflector RF(M) of the adjacent sub-pixel SP(M) of the Mth row through the first connection pattern CP1 and the second connection pattern CP2. In addition, the light-emitting diode 130 of the sub-pixel SP(N) of the Nth row can be normally driven using the pixel circuit of the sub-pixel SP(M) of the Mth row. In this case, the driving current for driving the light-emitting diode 130 of the Nth row and the driving current for driving the light-emitting diode 130 of the Mth row can flow through the sixth transistor T6 of the sub-pixel SP(M) of the Mth row.

[0244] At this time, in the configuration of the first connection pattern CP1 and the second connection pattern CP2, the 1-2 connection pattern CP1b and the 2-3 connection pattern CP2c formed of the same material as the source and the drain are not provided in the welding area WA. Therefore, the welding process can be performed more easily. For example, the 1-1 connection pattern CP1a provided on the same layer as the reference line RL can be formed of a material having a thickness of about 1. The 2-2nd connection pattern CP2b disposed on the same layer as the plurality of gate electrodes may be formed of molybdenum (Mo) having a thickness of about In addition, the 1st-2nd connection pattern CP1b and the 2nd-3rd connection pattern CP2c provided on the same layer as the plurality of source electrodes and the plurality of drain electrodes using the same material may be formed to have a thickness of about Thickness of titanium / aluminum / titanium (Ti / Al / Ti) three-layer structure.

[0245] If the 1-2 connection pattern CP1b or the 2-3 connection pattern CP2c is set to overlap with the welding area WA, the welding process can be performed by irradiating the laser LS with a stronger intensity. The 1-2 connection pattern CP1b or the 2-3 connection pattern CP2c has a relatively large thickness, so in order to allow the energy of the laser LS to reach the configuration below the 1-2 connection pattern CP1b and the 2-3 connection pattern CP2c, it is necessary to irradiate the laser LS with a stronger intensity. Therefore, in the welding area WA, the 1-2 connection pattern CP1b and the 2-3 connection pattern CP2c with a relatively large thickness are not set, but the 1-1 connection pattern CP1a or the 2-2 connection pattern CP2b with a relatively small thickness is set, so that the welding process can be performed using the laser LS with a weaker intensity.

[0246] At the same time, the plurality of layers forming the first connection pattern CP1 and the second connection pattern CP2 are formed to have a smaller size toward the upper portion, so that the first connection pattern CP1 and the second connection pattern CP2 can be protected from static electricity. Among the plurality of layers included in the first connection pattern CP1 and the second connection pattern CP2, the upper layer can be arranged to overlap with the inner region of the lower layer. The upper layer can be arranged to overlap only with the inner region of the lower layer so that the upper layer does not cover the edge of the lower layer.

[0247] Static electricity may be introduced into the display device 100 for various reasons. For example, in the process of manufacturing the display device 100, the display panel PN and a portion of the configuration are in contact with each other, thereby generating static electricity due to induction / separation charging. The static electricity entering the display panel PN causes the edges of some conductive layers to be broken down, thereby causing the conductive layer to be short-circuited with another conductive layer.

[0248] For example, when only the normal sub-pixels SP exist so that the welding process is not performed and static electricity does not enter, the 2-2nd connection pattern CP2b and the 1-1st connection pattern CP1a may be insulated from each other by the first interlayer insulating layer 113 therebetween. On the contrary, when static electricity enters and causes the edge of the 2-2nd connection pattern CP2b to be broken down, the 2-2nd connection pattern CP2b and the 1-1st connection pattern CP1a are connected, so that the normal sub-pixels SP may be connected to each other, thereby causing defects in the sub-pixels SP.

[0249] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the edges of the multiple layers of the first connection pattern CP1 and the second connection pattern CP2 are formed not to overlap with the upper layer of the multiple layers. Therefore, although the edges of the layers are broken down due to static electricity, a short circuit problem does not occur.

[0250] For example, among the multiple layers forming the first connection pattern CP1 and the second connection pattern CP2, the 2-1st connection pattern CP2a disposed at the bottom is formed to have the largest size, and the other layers disposed on the 2-1st connection pattern CP2a may be formed to have a smaller size toward the top. The 2-2nd connection pattern CP2b on the 2-1st connection pattern CP2a may be formed to have a smaller size than the 2-1st connection pattern CP2a, and the edge of the 2-2nd connection pattern CP2b may be formed to overlap with the area in the 2-1st connection pattern CP2a. The 1-1st connection pattern CP1a on the 2-2nd connection pattern CP2b may be formed to have a smaller size than the 2-2nd connection pattern CP2b, and the edge of the 1-1st connection pattern CP1a may be disposed in the area where the 2-2nd connection pattern CP2b is disposed. The 2-3rd connection pattern CP2c may be formed to have a smaller size than the 2-2nd connection pattern CP2b, and the edge of the 2-3rd connection pattern CP2c may overlap with the inside of the 2-2nd connection pattern CP2b. The 1-2nd connection pattern CP1b can be formed to have a smaller size than the 1-1st connection pattern CP1a, and the entire edge of the 1-2nd connection pattern CP1b can overlap with the 1-1st connection pattern CP1a. Therefore, the edge of the upper layer is set outside the edge of the lower layer, so that the short circuit problem caused by the problem of the edges of each layer being broken through can be reduced.

[0251] Next, after completing process (2), the defective sub-pixel SP causing abnormal brightness or color may be detected again by inspecting the display panel PN. When it is determined that the sub-pixel SP in which process (2) is performed needs to be dimmed again, process (3) may be performed. Process (3) is a process of cutting the reflective plate RF of the cutting area CA to separate the reflective plate RF connected by the first connection pattern CP1 and the second connection pattern CP2 again.

[0252] Reference Figures 10 to 11B , the cutting area CA is an area of ​​the protrusion RFP of the reflecting plate RF that does not overlap with the first connection pattern CP1 and the second connection pattern CP2. In the cutting area CA, only the protrusion RFP in the first connection pattern CP1, the second connection pattern CP2, and the protrusion RFP of the reflecting plate RF may be provided. The protrusion RFP may be cut from at least one of the cutting area CA adjacent to the first connection pattern CP1 and the cutting area CA adjacent to the second connection pattern CP2. Therefore, the protrusion RFP of the cutting area CA is cut to separate the reflecting plate RF connected by the first connection pattern CP1 and the second connection pattern CP2 again.

[0253] For example, when the first connection pattern CP1 and the second connection pattern CP2 are connected to each other through a welding process and the reflection plate RF(N) of the Nth row and the reflection plate RF(M) of the Mth row are electrically connected, the protrusion RFP of the reflection plate RF adjacent to the first connection pattern CP1 and the second connection pattern CP2 is cut to electrically separate the reflection plate RF(N) of the Nth row and the reflection plate RF(M) of the Mth row. Therefore, the reflection plate RF electrically connected through the first connection pattern CP1 and the second connection pattern CP2 is separated again to darken the defective sub-pixel SP again.

[0254] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, a welding process is performed on the second capacitor C2 connected between the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6 to darken the defective sub-pixel SP. The second capacitor C2 is connected between the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6. When the pixel circuit is defective, a welding process is performed on the second capacitor C2 to suppress the bright spot problem caused by the defective pixel circuit. When the laser LS is irradiated onto the second capacitor C2, the electrodes constituting the second capacitor C2 contact each other to connect the sixth gate GE6 and the sixth source SE6 of the sixth transistor T6 used as a driving transistor. In this case, the voltage difference Vgs between the sixth gate GE6 and the sixth source SE6 is 0V, so that the pixel circuit cannot make the light emitting diode 130 emit light. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, only the welding process is performed on the second capacitor C2, without performing a complicated laser (LS) cutting and welding process, to easily darken the defective pixel circuit.

[0255] In the display device 100 according to an exemplary embodiment of the present disclosure, the reflector RF of the defective sub-pixel SP and the reflector RF of the normal sub-pixel SP adjacent to the defective sub-pixel SP are connected by a welding process. Therefore, the light emitting diode 130 of the defective sub-pixel SP can be driven by the pixel circuit of the normal sub-pixel SP. First, in each of the plurality of sub-pixels SP, a reflector RF covering most of the plurality of sub-pixels SP and reflecting the light emitted from the light emitting diode 130 above the substrate is provided. At this time, the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3 and the fourth reflector RF4 among the reflectors RF serve as electrodes connecting the first electrode 134 of the light emitting diode 130 and the pixel circuit. Therefore, the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3 and the fourth reflector RF4 of the defective sub-pixel SP are connected to the 1-1st reflector RF1a, the 2-1st reflector RF2a, the third reflector RF3 and the fourth reflector RF4 of the adjacent rows. Therefore, the light emitting diode 130 of the defective sub-pixel SP may be electrically connected to the pixel circuit of the adjacent sub-pixel SP.

[0256] At this time, the first connection pattern CP1 and the second connection pattern CP2 overlapping the first interlayer insulating layer 113 located therebetween are arranged in the area between a pair of adjacent reflective plates RF, and a welding process for connecting the first connection pattern CP1 and the second connection pattern CP2 is performed to connect the pair of adjacent reflective plates RF. The first connection pattern CP1 and the second connection pattern CP2 overlapping each other can be connected to different reflective plates RF. The first connection pattern CP1 can be connected to one of a pair of adjacent reflective plates RF, and the second connection pattern CP2 can be connected to the other reflective plate RF. The laser LS is irradiated onto the welding area WA where the first connection pattern CP1 and the second connection pattern CP2 overlap to electrically connect one reflective plate RF connected to the first connection pattern CP1 and another reflective plate RF connected to the second connection pattern CP2 to perform the welding process. Therefore, the first electrode 134 of the light emitting diode 130 of the defective sub-pixel SP can be electrically connected to the first electrode 134 of the light emitting diode 130 of the normal sub-pixel SP through the first connection pattern CP1, the second connection pattern CP2 and the reflective plate RF connected to each other. In addition, the light emitting diode 130 of the defective sub-pixel SP and the light emitting diode 130 of the normal sub-pixel SP can be driven together using one pixel circuit. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the light emitting diode 130 can be easily connected to the normally driven pixel circuit only through one welding process using the reflection plate RF, the first connection pattern CP1 and the second connection pattern CP2, and the repair process can be simplified.

[0257] In the display device 100 according to an exemplary embodiment of the present disclosure, the edges of the multiple layers included in the first connection pattern CP1 and the second connection pattern CP2 are formed not to cover the edge of the lower layer. Therefore, the short circuit problem of the first connection pattern CP1 and the second connection pattern CP2 due to static electricity can be suppressed. In some cases, the problem of the edges of each conductive layer being broken down due to static electricity. In this case, when the breakdown occurs at the edge of the lower layer, a short circuit problem between the lower layer and the upper layer covering the edge of the lower layer may be caused. The first connection pattern CP1 and the second connection pattern CP2 between the normal sub-pixels SP need to be separated by the insulating layer located therebetween, but the first connection pattern CP1 and the second connection pattern CP2 are connected due to static electricity, resulting in another problem. Therefore, the multiple layers of the first connection pattern CP1 and the second connection pattern CP2 that are arranged to overlap each other are formed not to cover the edge of the lower layer, thereby reducing the short circuit problem caused by static electricity. For example, the 2-2nd connection pattern CP2b is formed to have a size smaller than the 2-1st connection pattern CP2a arranged at the bottom, so as to overlap only with the inside of the 2-1st connection pattern CP2a. Therefore, the 2-2nd connection pattern CP2b may be set not to cover the edge of the 2-1st connection pattern CP2a. Therefore, the multiple layers forming the first connection pattern CP1 and the second connection pattern CP2 are formed to have a smaller size toward the top, so that the upper layer may be designed not to cover the edge of the lower layer.

[0258] In the display device 100 according to the exemplary embodiment of the present disclosure, the conductive layer having a relatively large thickness is removed from the welding area WA connecting the reflective plate RF, so that the welding process can be easily performed using a laser having a lower output. For example, among the plurality of conductive layers of the first connection pattern CP1 and the second connection pattern CP2 provided in the welding area WA, the 1st-2nd connection pattern CP1b and the 2nd-3rd connection pattern CP2c formed to be relatively thick can be provided to be spaced apart from the welding area WA. In addition, in the welding area WA, the 2nd-2nd connection pattern CP2b having a relatively small thickness is provided at the top to reduce the intensity of the laser and reduce damage to the periphery of the welding area WA.

[0259] In the display device 100 according to an exemplary embodiment of the present disclosure, a cutting process of separating the reflective plate RF from the first connection pattern CP1 or the second connection pattern CP2 is performed in the sub-pixel SP that needs to be dimmed again to perform dimming again. The reflective plate RF of the defective sub-pixel SP can be connected to the reflective plate RF of the adjacent sub-pixel SP through the first connection pattern CP1 and the second connection pattern CP2. However, when it is determined that it is necessary to dim again after repair, the protrusion RFP of the protrusion RFP of the reflective plate RF that is spaced apart from the first connection pattern CP1 and the second connection pattern CP2 in the cutting area CA can be cut. Therefore, the protrusion RFP is cut from the cutting area CA to separate the protrusion RFP and the reflective plate RF, thereby separating the reflective plate RF from the first connection pattern CP1 and the second connection pattern CP2 to make the defective sub-pixel SP dim again.

[0260] Exemplary embodiments of the present disclosure may also be described as follows:

[0261] According to one aspect of the present disclosure, a display device includes: a first substrate in which a plurality of sub-pixels including at least one defective sub-pixel and a plurality of normal sub-pixels are defined; a light emitting diode disposed in each of the plurality of sub-pixels; a plurality of transistors disposed in each of the plurality of sub-pixels and including a driving transistor having a source connected to a first electrode of the light emitting diode; a capacitor including a plurality of capacitor electrodes connected to a gate and a source of the driving transistor; and a reflective plate disposed in each of the plurality of sub-pixels and electrically connected to the first electrode. In the defective sub-pixel, the plurality of capacitor electrodes of the capacitor are in contact with each other.

[0262] In the defective sub-pixel, the gate and source of the driving transistor may be electrically connected through a plurality of capacitor electrodes.

[0263] In a plurality of normal sub-pixels, a plurality of capacitor electrodes may be spaced apart from each other by an insulating layer disposed therebetween.

[0264] Among the plurality of normal sub-pixels, reflection plates of a pair of adjacent normal sub-pixels may be insulated, and the reflection plate of the defective sub-pixel may be electrically connected to one of the reflection plates of the plurality of normal sub-pixels adjacent to the defective sub-pixel.

[0265] The first electrode of the light emitting diode of the defective sub-pixel may be electrically connected to the driving transistors of the plurality of normal sub-pixels.

[0266] The display device may further include: a first connection pattern connected to one edge of the reflective plate of each of the plurality of sub-pixels; and a second connection pattern connected to another edge of the reflective plate of each of the plurality of sub-pixels. The first connection pattern and the second connection pattern connected to different reflective plates of the reflective plates may overlap at a boundary between the plurality of sub-pixels to form a welding area.

[0267] The first connection pattern may include a 1-1 connection pattern disposed on the first substrate, and a 1-2 connection pattern disposed on the 1-1 connection pattern and having a thickness greater than that of the 1-1 connection pattern. The second connection pattern may include a 2-1 connection pattern disposed between the first substrate and the first connection pattern, a 2-2 connection pattern disposed between the 2-1 connection pattern and the first connection pattern, and a 2-3 connection pattern disposed on the 2-2 connection pattern and having a thickness greater than that of the 2-2 connection pattern, and the 1-2 connection pattern and the 2-3 connection pattern may be connected to the reflective plate.

[0268] The 1-1st, 2-1st, and 2-2nd connection patterns may overlap the welding region, and the 1-2nd and 2-3rd connection patterns may be disposed to be spaced apart from the welding region.

[0269] The first connection pattern and the second connection pattern may be disposed to be spaced apart from each other at a boundary of a pair of adjacent normal sub-pixels with an insulating layer therebetween.

[0270] The 1-1th connection pattern may contact the 2-2th connection pattern in a welding region disposed at a boundary between the defective sub-pixel and the normal sub-pixel.

[0271] The 1-2 connection pattern may be arranged in the inner area of ​​the 1-1 connection pattern, the inner area of ​​the 2-1 connection pattern and the inner area of ​​the 2-2 connection pattern, the 2-2 connection pattern may be arranged in the inner area of ​​the 2-1 connection pattern, and the 2-3 connection pattern may be arranged in the inner area of ​​the 2-2 connection pattern.

[0272] An entire edge of the 1-2 connection pattern may overlap with the 1-1 connection pattern, an entire edge of the 2-2 connection pattern may overlap with the 2-1 connection pattern, and an entire edge of the 2-3 connection pattern may overlap with the 2-2 connection pattern.

[0273] The reflective plate may further include a protrusion protruding from each of the one edge and the other edge and connected to the first and second connection patterns, and the protrusion may include a cut region not overlapping the first and second connection patterns.

[0274] At least a portion of the protrusions of the plurality of sub-pixels may be cut from the cutting region to be separated from the reflection plate.

[0275] The display device may further include: a plurality of gate driving regions disposed between the plurality of sub-pixels; and a gate driver disposed in the plurality of gate driving regions and including a plurality of gate driving transistors.

[0276] The plurality of transistors of the plurality of sub-pixels may include an active layer formed of any one of an oxide semiconductor, amorphous silicon, and polysilicon, and the plurality of gate driving transistors of the gate driver may include an active layer formed of any one of an oxide semiconductor, amorphous silicon, and polysilicon.

[0277] Active layers of a plurality of gate driving transistors of the gate driver may be formed of different materials.

[0278] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A splicing display device, comprising: Multiple display devices, Each of the plurality of display devices comprises: a plurality of pixel regions arranged to form a plurality of rows and a plurality of columns; and The gate driver is disposed between a first plurality of data lines connecting a plurality of pixel regions in a first column and a second plurality of data lines connecting a plurality of pixel regions in a second column adjacent to the first column.

2. The splicing display device according to claim 1, further comprising: A plurality of pixels are arranged in the plurality of pixel regions, The distance between the outermost pixel of one of the multiple display devices and the outermost pixel of another display device adjacent to the one display device is equal to the distance between the multiple pixels in the one display device.

3. The splicing display device according to claim 2, wherein: All of the plurality of pixels included in the plurality of display devices are arranged at equal intervals.

4. The spliced ​​display device according to claim 2, wherein: Each of the plurality of display devices further includes a substrate having the plurality of pixels defined therein; Wherein, the substrate comprises: a display area in which the plurality of pixels are disposed; A first pad region, disposed on one side of the display region; and The second pad area is arranged at the other side of the display area.

5. The spliced ​​display device according to claim 4, wherein: Each of the plurality of display devices further comprises: A plurality of gate drivers are arranged in the display area; The plurality of gate drivers are configured to provide a scan signal to each of the plurality of pixels.

6. The spliced ​​display device according to claim 5, wherein: Each of the plurality of display devices further comprises: a plurality of data lines, arranged in the display area and extending in a first direction; and a plurality of scanning lines, arranged in the display area and extending in a second direction perpendicular to the first direction, Wherein, the plurality of scan lines are electrically connected to the plurality of gate drivers.

7. The spliced ​​display device according to claim 6, wherein: Each of the plurality of display devices further comprises: A plurality of first pad electrodes are disposed on a surface of the substrate; and a plurality of second pad electrodes disposed on a surface of the substrate opposite to the one surface; The plurality of first pad electrodes and the plurality of second pad electrodes are arranged to overlap with the first pad region and the second pad region.

8. The spliced ​​display device according to claim 7, wherein: The plurality of data lines are electrically connected to the plurality of first pad electrodes in the first pad region.

9. The spliced ​​display device according to claim 7, wherein: The plurality of scan lines are spaced apart from the plurality of first pad electrodes.

10. The spliced ​​display device according to claim 7, wherein: Each of the plurality of display devices further comprises: A plurality of side lines are arranged on the side of the substrate, One ends of the plurality of side surface lines are in contact with the plurality of first pad electrodes, and the other ends of the plurality of side surface lines are in contact with the plurality of second pad electrodes.

11. The spliced ​​display device according to claim 10, wherein: Each of the plurality of display devices further comprises: a side insulating layer covering the plurality of side lines; and a sealing member covering the side insulating layer, The sealing members of each of the plurality of display devices are arranged to face each other.

12. The spliced ​​display device according to claim 11, wherein: Each of the plurality of display devices further includes an optical film disposed on the sealing member, the side insulating layer, and the plurality of pixels, Wherein, the side surface of the optical film and the side surface of the sealing member are arranged on the same plane.

13. The spliced ​​display device according to claim 2, wherein: Each of the plurality of display devices further comprises: a plurality of micro LEDs disposed in each of the plurality of pixels; A plurality of pixel circuits, arranged in the plurality of pixels; a plurality of reflective plates disposed below the plurality of micro LEDs in the plurality of pixels; and an adhesive layer disposed between the plurality of reflective plates and the plurality of micro LEDs, Wherein, the plurality of micro LEDs are electrically connected to the plurality of pixel circuits through the plurality of reflective plates.

14. The spliced ​​display device according to claim 13, wherein: Each of the plurality of micro-LEDs comprises: a first semiconductor layer disposed on the adhesive layer; A light emitting layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the light emitting layer; A first electrode, disposed on the first semiconductor layer; A second electrode is disposed on the second semiconductor layer; and an encapsulation layer, which surrounds the first semiconductor layer, the light emitting layer, the second semiconductor layer, the first electrode and the second electrode, Wherein, the encapsulation layer includes contact holes exposing the first electrode and the second electrode.

15. The spliced ​​display device according to claim 14, wherein: Each of the plurality of display devices further comprises: an organic insulating layer, covering the plurality of micro LEDs, Wherein, the organic insulating layer is arranged to cover the side surfaces and top surfaces of the plurality of micro LEDs.

16. The spliced ​​display device according to claim 15, wherein: Each of the plurality of display devices further comprises: a first connection electrode disposed on the organic insulating layer and electrically connected to the second electrode of each of the plurality of micro LEDs; and a second connecting electrode disposed on the organic insulating layer and electrically connected to the first electrode of each of the plurality of micro LEDs, wherein a portion of the organic insulating layer is disposed in a portion between the first electrode and the second electrode of each of the plurality of micro LEDs, The first connecting electrode and the second connecting electrode are arranged to be spaced apart from each other with the portion of the organic insulating layer disposed therebetween.

17. The spliced ​​display device according to claim 14, wherein: Each of the plurality of display devices further includes a second planarization layer disposed on the adhesive layer and overlapping a portion of a side surface of the plurality of micro LEDs, and The second planarization layer is formed to have a step, so that a portion of the second planarization layer relatively adjacent to the plurality of micro LEDs has a smaller thickness than a portion of the second planarization layer far from the plurality of micro LEDs.

18. The spliced ​​display device according to claim 17, wherein: Each of the plurality of display devices further includes a third planarization layer, the third planarization layer being disposed to cover the second planarization layer and an upper portion of the plurality of micro LEDs, and The first electrode and the second electrode of each of the plurality of micro LEDs are exposed from the third planarization layer, and the third planarization layer is partially disposed in a region between the first electrode and the second electrode of each of the plurality of micro LEDs.

19. The spliced ​​display device according to claim 18, wherein: Each of the plurality of display devices further includes a bank that is spaced apart from the plurality of micro LEDs at a predetermined interval and is disposed on the second planarization layer, wherein the second planarization layer includes a portion and another portion having a thickness thicker than the portion, and The bank and the third planarization layer are disposed on the portion of the second planarization layer and are spaced apart from each other.

20. The spliced ​​display device according to claim 4, wherein: An alignment key is provided in an area between the plurality of pixel areas, Wherein, the alignment key comprises: a first alignment key configured to check alignment positions of the plurality of light emitting diodes in the plurality of pixel regions; and The second alignment key is configured to align the substrate with a carrier, and the carrier is configured to transfer the plurality of light emitting diodes to the substrate.

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