Thin film transistor, preparation method thereof, photoelectric detection device and display device

Abstract

The invention provides a thin film transistor, a preparation method thereof, a photoelectric detection device and a display device, the thin film transistor comprises an active layer, a laminated structure comprises at least one metal oxide layer and at least one low-temperature polycrystalline silicon layer, and the low-temperature polycrystalline silicon layer is arranged on the upper layer and / or the lower layer of the metal oxide layer; according to the scheme, the active layer of the photoelectric detector TFT is designed into a laminated structure of the metal oxide layer and the low-temperature polycrystalline silicon layer, the advantages of the metal oxide layer and the low-temperature polycrystalline silicon layer are combined, the disadvantages are made up, the radiation reliability of the X-ray detector backboard TFT is improved, and the service life of the X-ray flat panel detector is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, a photoelectric detection device, and a display device. Background Art

[0002] X-ray flat panel detectors are composed of scintillators, sensors, and TFT backplanes (thin film transistors). After the X-rays from the target object are attenuated, they reach the scintillator layer of the detector. The scintillator converts the X-rays into visible light, which is then received by the sensor. After photoelectric conversion and analog-to-digital conversion, the optical signal is converted into a digital signal for imaging. In this process, although the scintillator absorbs some X-rays and converts them into visible light, some X-rays will still irradiate the TFT backplane. Due to the high energy of X-rays, the parameters of the TFT backplane (thin film transistor) will deteriorate, affecting the service life of the detector. Summary of the invention

[0003] The purpose of the present invention is to provide a thin film transistor, a preparation method thereof, a photoelectric detection device, and a display device, wherein the active layer of the thin film transistor is designed to be a stacked structure of a metal oxide layer and a low-temperature polysilicon layer, combining the advantages of both layers, compensating for the disadvantages, and solving the problem that the service life of TFT is affected by the deterioration of X-ray irradiation parameters.

[0004] To achieve the above purpose, the technical solution provided by the present invention is as follows:

[0005] In a first aspect, the present invention provides a thin film transistor, comprising an active layer, wherein the active layer comprises a stacked structure, and the stacked structure comprises:

[0006] at least one metal oxide layer,

[0007] At least one low temperature polysilicon layer, wherein

[0008] The low temperature polysilicon layer is disposed on an upper layer and / or a lower layer of the metal oxide layer.

[0009] Furthermore, the thin film transistor further comprises:

[0010] Base,

[0011] a buffer layer, the buffer layer being disposed on the substrate, the active layer being disposed on the buffer layer,

[0012] a gate insulating layer, the gate insulating layer being disposed on the active layer and covering the active layer,

[0013] a gate layer, the gate layer being disposed on the gate insulating layer,

[0014] a dielectric layer, the dielectric layer being disposed on the gate layer and covering the gate layer,

[0015] A source electrode layer and a drain electrode layer are provided on the dielectric layer, and the source electrode layer and the drain electrode layer are connected to the active layer through the dielectric layer and the gate insulating layer.

[0016] Further,

[0017] The metal oxide layer comprises a first metal oxide layer,

[0018] The low temperature polysilicon layer includes a first low temperature polysilicon layer and a second low temperature polysilicon layer.

[0019] The first low-temperature polysilicon layer is disposed under the first metal oxide layer, the second low-temperature polysilicon layer is disposed on the first metal oxide layer, and a single crystal silicon layer is disposed on the second low-temperature polysilicon layer.

[0020] or,

[0021] The metal oxide layer includes a second metal oxide layer and a third metal oxide layer.

[0022] The low temperature polysilicon layer includes a third low temperature polysilicon layer,

[0023] The second metal oxide layer is disposed under the third low temperature polysilicon layer, and the third metal oxide layer is disposed on the third low temperature polysilicon layer;

[0024] or,

[0025] The metal oxide layer includes a fourth metal oxide layer, the low temperature polysilicon layer includes a fourth low temperature polysilicon layer, and the fourth metal oxide layer is disposed on the fourth low temperature polysilicon layer;

[0026] or,

[0027] The metal oxide layer includes a fifth metal oxide layer, the low temperature polysilicon layer includes a fifth low temperature polysilicon layer, the fifth metal oxide layer is arranged under the fifth low temperature polysilicon layer, and a single crystal silicon layer is arranged on the fifth low temperature polysilicon layer.

[0028] Furthermore, the metal oxide layer includes an indium gallium zinc oxide layer.

[0029] In a second aspect, the present invention further provides a photoelectric detection device, comprising any of the thin film transistors described above.

[0030] Furthermore, the photoelectric detection device also includes:

[0031] Scintillator,

[0032] A photodiode array, wherein the scintillator is located at an upper layer of the photodiode array, and the thin film transistor is located at a lower layer of the photodiode array;

[0033] In a third aspect, the present invention provides a display device, wherein the display device comprises a display module, and the display module comprises any one of the thin film transistors described above.

[0034] In a fourth aspect, the present invention provides a method for preparing a thin film transistor, the preparation method comprising preparing an active layer, the active layer comprising at least one metal oxide layer and at least one low-temperature polysilicon layer, wherein the low-temperature polysilicon layer is arranged on the upper layer and / or lower layer of the metal oxide layer.

[0035] Furthermore, the preparation method comprises the following steps:

[0036] Providing a substrate,

[0037] preparing a buffer layer on the substrate,

[0038] The active layer and the gate insulating layer are prepared on the buffer layer, and the gate insulating layer covers the active layer.

[0039] A gate layer and a dielectric layer are prepared on the gate insulating layer, and the dielectric layer covers the gate layer.

[0040] A source electrode layer and a drain electrode layer are prepared on the dielectric layer, and holes are punched on the dielectric layer and the gate insulating layer so that the source electrode layer and the drain electrode layer pass through the dielectric layer and the gate insulating layer to connect with the active layer.

[0041] Furthermore, the preparation of the active layer includes the following steps:

[0042] Prepare a low temperature polysilicon layer,

[0043] A metal oxide layer is prepared on the upper surface of the low temperature polysilicon layer,

[0044] A low-temperature polysilicon layer is further prepared on the upper surface of the metal oxide layer.

[0045] A single crystal silicon layer is prepared on the upper surface of the low temperature polysilicon layer at the uppermost layer;

[0046] or,

[0047] Prepare a metal oxide layer,

[0048] A low-temperature polysilicon layer is prepared on the upper surface of the metal oxide layer,

[0049] Further preparing a metal oxide layer on the upper surface of the low temperature polysilicon layer;

[0050] or,

[0051] Prepare a metal oxide layer,

[0052] A low-temperature polysilicon layer is prepared on the upper surface of the metal oxide layer,

[0053] Prepare a single crystal silicon layer on the upper surface of the low temperature polysilicon layer;

[0054] or,

[0055] Prepare a low temperature polysilicon layer,

[0056] A metal oxide layer is prepared on the upper surface of the low temperature polysilicon layer.

[0057] The advantages of the present invention are as follows:

[0058] The present invention provides a thin film transistor, a preparation method thereof, a photoelectric detection device, and a display device, wherein the active layer of the thin film transistor of the photoelectric detection device is designed to be a stacked structure of a metal oxide layer and a low-temperature polysilicon layer, combining the advantages of both layers to compensate for the disadvantages, thereby improving the radiation reliability of the X-ray detector TFT and extending the service life of the X-ray flat panel detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 This is the X-ray radiation reliability test parameter characteristic curve of LTPS-TFT.

[0061] Figure 2 This is the X-ray radiation reliability test parameter characteristic curve of IGZO-TFT.

[0062] Figure 3 FIG. 4 is a schematic diagram of a thin film transistor structure in an embodiment of the present invention.

[0063] Figure 4 FIG. 4 is a schematic diagram of a thin film transistor structure in another embodiment of the present invention.

[0064] Figure 5 FIG. 4 is a schematic diagram of a thin film transistor structure in another embodiment of the present invention.

[0065] Figure 6 FIG. 4 is a schematic diagram of a thin film transistor structure in yet another embodiment of the present invention.

[0066] Figure 7 The figure is a flow chart of the method for preparing a thin film transistor of the present invention.

[0067] Figure 8 The present invention is a flowchart of a method for preparing an active layer in one embodiment of the present invention.

[0068] Fig. 9 The present invention is a flow chart of a method for preparing an active layer in another embodiment of the present invention.

[0069] Fig.10 The present invention is a flowchart of a method for preparing an active layer in another embodiment of the present invention.

[0070] Fig.11 The present invention is a flowchart of a method for preparing an active layer in another embodiment of the present invention.

[0071] Fig.12 It is a partial structural schematic diagram of a photoelectric detection device in one embodiment of the present invention.

[0072] The components in the figure are shown as follows:

[0073] 1. Substrate; 2. Buffer layer; 3. Gate insulating layer; 4. Active layer; 5. Dielectric layer; 6. Gate layer; 7. Single crystal silicon layer; 8. Source layer; 9. Drain layer;

[0074] 41. a first metal oxide layer; 42. a first low-temperature polysilicon layer; 43. a second low-temperature polysilicon layer; 44. a third low-temperature polysilicon layer; 45. a second metal oxide layer; 46. a third metal oxide layer; 47. a fourth metal oxide layer; 48. a fourth low-temperature polysilicon layer; 49. a fifth metal oxide layer; 410. a fifth low-temperature polysilicon layer;

[0075] 100. scintillator; 200. photodiode array; 300. thin film transistor. DETAILED DESCRIPTION

[0076] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0077] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0078] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0079] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0080] Overview

[0081] As described in the background technology, the X-ray flat panel detector is composed of a scintillator, a sensor, and a TFT backplane (thin film transistor). After the X-rays from the target object are attenuated, they reach the scintillator layer of the detector, and the scintillator converts the X-rays into visible light. The converted visible light is then received by the sensor, and the optical signal is converted into a digital signal for imaging through photoelectric conversion and analog-to-digital conversion. In this process, although the scintillator absorbs X-rays and converts them into visible light, due to the large energy of X-rays, the scintillator cannot absorb all of the X-rays, and some X-rays will still irradiate the TFT. Therefore, there is a problem that the TFT is affected by the X-ray ionization effect, displacement effect, etc., and the Vth (threshold voltage) and SS (subthreshold swing) parameters are deteriorated, affecting the imaging quality of the X-ray detector.

[0082] At present, the commonly used X-ray flat panel detector TFT can be divided into two categories according to the material. The first category is the TFT made of low temperature polycrystalline silicon material (LTPS-TFT), and the second category is the TFT made of metal oxide material (IGZO-TFT). The TFTs of these two materials were subjected to X-ray irradiation tests respectively. The distance between the TFTs of the two materials and the X-ray source was equal. The X-rays were directly irradiated onto the TFTs without the scintillator. After a certain amount of X-ray irradiation, the parameters of the TFTs of the two materials showed different degrees of deterioration, such as Figure 1 and Figure 2 As shown, according to the TFT parameter characteristic curves of the two materials, the following test results can be obtained:

[0083] The Vth of LTPS-TFT becomes positively biased as the X-ray irradiation dose increases (Dose2>Dose1), while the Vth of IGZO-TFT becomes negatively biased, and the offset is large, indicating that the Vth parameter of IGZO-TFT deteriorates more seriously;

[0084] The SS of LTPS-TFT deteriorates more seriously, while the SS of IGZO-TFT is more stable, which indicates that the SS parameter of LTPS-TFT deteriorates more seriously;

[0085] X-ray irradiation causes an increase in Si-SiO interface defects in LTPS-TFT and an increase in oxide layer defects in IGZO-TFT, which ultimately leads to the deterioration of TFT parameters and affects detector imaging.

[0086] Based on the test results of the X-ray radiation reliability of the above two different material TFTs, the inventors improved the active layer in the TFT and designed the active layer into a stacked structure of low-temperature polycrystalline silicon material and metal oxide material. The stable Vth parameter of the low-temperature polycrystalline silicon material under X-ray irradiation is used to compensate for the serious deterioration of the Vth parameter of the metal oxide material under X-ray irradiation. The stable SS parameter of the metal oxide material under X-ray irradiation is used to compensate for the serious deterioration of the SS parameter of the low-temperature polycrystalline silicon material under X-ray irradiation. The advantages of both are fully combined to compensate for the disadvantages, thereby improving the radiation reliability of the TFT backplane of the X-ray detector.

[0087] Based on the above concept, the present application will be exemplarily described below in conjunction with the accompanying drawings.

[0088] Exemplary Components

[0089] This embodiment provides a thin film transistor, including:

[0090] Base 1,

[0091] A buffer layer 2 is provided on the substrate, wherein the buffer layer 2 comprises a stacked structure of silicon nitride and silicon oxide,

[0092] An active layer 4 and a gate insulating layer 3 are arranged on the buffer layer 2, wherein the gate insulating layer 3 covers the active layer 4.

[0093] A gate layer 6 and a dielectric layer 5 are provided on the gate insulating layer 3, wherein the dielectric layer 5 covers the gate layer 6.

[0094] A source electrode layer 8 and a drain electrode layer 9 are disposed on the dielectric layer 5, wherein the source electrode layer 8 and the drain electrode layer 9 are disposed on the dielectric layer 5, and the source electrode layer 8 and the drain electrode layer 9 pass through the dielectric layer 5 and the gate insulating layer 3 to be connected to the active layer 4;

[0095] The active layer 4 includes a stacked structure of a low-temperature polysilicon layer and a metal oxide layer;

[0096] In some embodiments, Figure 3 As shown, the active layer 4 includes a first metal oxide layer 41, a first low-temperature polysilicon layer 42 and a second low-temperature polysilicon layer 43, wherein:

[0097] The first low-temperature polysilicon layer 42 is disposed under the first metal oxide layer 41 , the second low-temperature polysilicon layer 43 is disposed on the first metal oxide layer 41 , and a single crystal silicon layer 7 is disposed on the second low-temperature polysilicon layer 43 .

[0098] In some embodiments, Figure 4 As shown, the active layer 4 includes a third low-temperature polysilicon layer 44, a second metal oxide layer 45 and a third metal oxide layer 46, wherein:

[0099] The second metal oxide layer 45 is disposed under the third low-temperature polysilicon layer 44, and the third metal oxide layer 46 is disposed on the third low-temperature polysilicon layer 44;

[0100] In some embodiments, Figure 5 As shown, the active layer 4 includes a fourth metal oxide layer 47 and a fourth low-temperature polysilicon layer 48, wherein:

[0101] The fourth metal oxide layer 47 is disposed on the fourth low-temperature polysilicon layer 48;

[0102] In some embodiments, Figure 6 As shown, the active layer 4 includes a fifth metal oxide layer 49 and a fifth low-temperature polysilicon layer 410, wherein:

[0103] The fifth metal oxide layer 49 is disposed under the fifth low-temperature polysilicon layer 410 , and a single crystal silicon layer 7 is disposed on the fifth low-temperature polysilicon layer 410 .

[0104] It should be noted that, in the above embodiment, it is assumed that the X-rays are irradiated from top to bottom. Since the SS parameters of the LTPS-TFT are seriously deteriorated in the X-ray irradiation test of the TFT backplane of two materials, LTPS-TFT and IGZO-TFT, it can be seen that the grain boundaries of the LTPS-TFT are seriously affected by the X-ray irradiation. Therefore, it is necessary to avoid the surface of the low-temperature polycrystalline silicon layer in the active layer 4 from being directly irradiated by X-rays. Therefore, when the low-temperature polycrystalline silicon layer is located at the top in the above embodiment, it is necessary to cover the upper surface of the low-temperature polycrystalline silicon layer with a single crystal silicon layer, so as to effectively avoid the serious deterioration of the grain boundaries of the low-temperature polycrystalline silicon layer caused by direct X-ray irradiation.

[0105] It should be noted that the metal oxide in the above embodiment includes IGZO (indium gallium zinc oxide), and also includes other materials that can achieve the same or similar functions.

[0106] Exemplary Preparation Methods

[0107] This embodiment provides a method for preparing a thin film transistor, such as Figure 7 As shown, the preparation method comprises the following steps:

[0108] S1. providing a substrate,

[0109] S2, preparing a buffer layer on the substrate,

[0110] S3, preparing the active layer and the gate insulating layer on the buffer layer, and allowing the gate insulating layer to cover the active layer,

[0111] S4, preparing a gate layer and a dielectric layer on the gate insulating layer, and allowing the dielectric layer to cover the gate layer,

[0112] S5. Prepare a source electrode layer and a drain electrode layer on the dielectric layer, and drill holes in the dielectric layer and the gate insulating layer so that the source electrode layer and the drain electrode layer pass through the dielectric layer and the gate insulating layer to connect with the active layer.

[0113] In some embodiments, Figure 8 As shown, the preparation of the active layer includes the following steps:

[0114] S31, preparing a low-temperature polysilicon layer,

[0115] S32, preparing a metal oxide layer on the upper surface of the low-temperature polysilicon layer,

[0116] S33, preparing a low-temperature polysilicon layer on the upper surface of the metal oxide layer;

[0117] S34, preparing a single crystal silicon layer on the upper surface of the low-temperature polysilicon layer at the uppermost layer;

[0118] In some embodiments, Fig. 9 As shown, the preparation of the active layer includes the following steps:

[0119] S31, preparing a metal oxide layer,

[0120] S32, preparing a low-temperature polysilicon layer on the upper surface of the metal oxide layer,

[0121] S33, preparing another metal oxide layer on the upper surface of the low-temperature polysilicon layer;

[0122] In some embodiments, Fig.10 As shown, the preparation of the active layer includes the following steps:

[0123] S31, preparing a metal oxide layer,

[0124] S32, preparing a low-temperature polysilicon layer on the upper surface of the metal oxide layer;

[0125] S33, preparing a single crystal silicon layer on the upper surface of the low temperature polycrystalline silicon layer;

[0126] In some embodiments, Fig.11 As shown, the preparation of the active layer includes the following steps:

[0127] S31, preparing a low-temperature polysilicon layer,

[0128] S32, preparing a metal oxide layer on the upper surface of the low-temperature polysilicon layer.

[0129] It should be noted that the LTPS-TFT grain boundaries are severely affected by X-ray irradiation, and it is necessary to avoid direct X-ray irradiation of the surface of the low-temperature polycrystalline silicon layer in the active layer. Therefore, when the low-temperature polycrystalline silicon layer in the active layer is located at the topmost layer, it is necessary to prepare a single crystal silicon layer on the upper surface of the low-temperature polycrystalline silicon layer. The single crystal silicon layer needs to cover the upper surface of the low-temperature polycrystalline silicon layer to ensure that the single crystal silicon layer blocks the X-rays and avoids direct X-ray irradiation, which causes serious deterioration of the grain boundaries of the low-temperature polycrystalline silicon layer.

[0130] Exemplary Photodetection Devices

[0131] This embodiment provides a photoelectric detection device, which uses the thin film transistor 300 described in any one of the above embodiments. Fig.12 As shown, the photodetection device includes a scintillator 100 and a photodiode array 200. The scintillator 100 is located on an upper layer of the photodiode array 200, and the thin film transistor 300 is located on a lower layer of the photodiode array.

[0132] The photoelectric detection device provided in this embodiment designs the active layer of the TFT to be a stacked structure of a metal oxide layer and a low-temperature polysilicon layer, combining the advantages of the two layers to make up for the disadvantages, thereby reducing the serious deterioration of the Vth parameter and SS parameter of the TFT backplane under X-ray irradiation, improving the radiation reliability of the X-ray detector TFT, extending the service life of the X-ray flat-panel detector, and improving the overall quality of the product.

[0133] Exemplary Display Devices

[0134] This embodiment provides a display device, which includes a display module. The display module includes the thin film transistor described in any one of the above embodiments.

[0135] The display device provided in this embodiment designs the TFT active layer in the display module into a stacked structure of a metal oxide layer and a low-temperature polysilicon layer. Unlike the photoelectric detection device, the TFT in the display device does not require X-ray irradiation but requires ultraviolet light irradiation. Therefore, the use of a stacked structure can also avoid serious deterioration of the Vth parameter and SS parameter of the TFT, extend the service life of the display device, and improve the overall quality of the product.

[0136] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A thin film transistor, characterized in that: The invention comprises an active layer, wherein the active layer comprises a stacked structure, and the stacked structure comprises: at least one metal oxide layer, At least one low temperature polysilicon layer, wherein The low temperature polysilicon layer is disposed on an upper layer and / or a lower layer of the metal oxide layer.

2. The thin film transistor according to claim 1, wherein: Also includes Base, a buffer layer, the buffer layer being disposed on the substrate, the active layer being disposed on the buffer layer, a gate insulating layer, the gate insulating layer being disposed on the active layer and covering the active layer, a gate layer, the gate layer being disposed on the gate insulating layer, a dielectric layer, the dielectric layer being disposed on the gate layer and covering the gate layer, A source electrode layer and a drain electrode layer are provided on the dielectric layer, and the source electrode layer and the drain electrode layer are connected to the active layer through the dielectric layer and the gate insulating layer.

3. The thin film transistor according to claim 1, wherein: The metal oxide layer comprises a first metal oxide layer, The low temperature polysilicon layer includes a first low temperature polysilicon layer and a second low temperature polysilicon layer. The first low-temperature polysilicon layer is disposed under the first metal oxide layer, the second low-temperature polysilicon layer is disposed on the first metal oxide layer, and a single crystal silicon layer is disposed on the second low-temperature polysilicon layer; or, The metal oxide layer includes a second metal oxide layer and a third metal oxide layer, The low temperature polysilicon layer includes a third low temperature polysilicon layer, The second metal oxide layer is disposed under the third low temperature polysilicon layer, and the third metal oxide layer is disposed on the third low temperature polysilicon layer; or, The metal oxide layer includes a fourth metal oxide layer, the low temperature polysilicon layer includes a fourth low temperature polysilicon layer, and the fourth metal oxide layer is disposed on the fourth low temperature polysilicon layer; or, The metal oxide layer includes a fifth metal oxide layer, the low temperature polysilicon layer includes a fifth low temperature polysilicon layer, the fifth metal oxide layer is arranged under the fifth low temperature polysilicon layer, and a single crystal silicon layer is arranged on the fifth low temperature polysilicon layer.

4. The thin film transistor according to claim 1, wherein: The metal oxide layer includes an indium gallium zinc oxide layer.

5. A photoelectric detection device, characterized in that: The invention comprises the thin film transistor according to any one of claims 1 to 4.

6. The photoelectric detection device as claimed in claim 5, characterized in that: Also includes Scintillator, The photodiode array is provided, wherein the scintillator is located above the photodiode array, and the thin film transistor is located below the photodiode array.

7. A display device, characterized in that: The invention comprises a display module, wherein the display module comprises the thin film transistor according to any one of claims 1 to 4.

8. A method for preparing a thin film transistor, characterized in that: The preparation method comprises preparing an active layer, wherein the active layer comprises at least one metal oxide layer and at least one low-temperature polysilicon layer, wherein the low-temperature polysilicon layer is arranged on an upper layer and / or a lower layer of the metal oxide layer.

9. The method for preparing a thin film transistor according to claim 8, wherein: The preparation method comprises the following steps: Providing a substrate, preparing a buffer layer on the substrate, The active layer and the gate insulating layer are prepared on the buffer layer, and the gate insulating layer covers the active layer; the gate layer and the dielectric layer are prepared on the gate insulating layer, and the dielectric layer covers the gate layer; A source electrode layer and a drain electrode layer are prepared on the dielectric layer, and holes are punched on the dielectric layer and the gate insulating layer so that the source electrode layer and the drain electrode layer pass through the dielectric layer and the gate insulating layer to connect with the active layer.

10. The method for preparing a thin film transistor according to claim 8, wherein: The preparation of the active layer includes the following steps: Prepare a low temperature polysilicon layer, A metal oxide layer is prepared on the upper surface of the low temperature polysilicon layer, A low-temperature polysilicon layer is further prepared on the upper surface of the metal oxide layer. A single crystal silicon layer is prepared on the upper surface of the low temperature polysilicon layer at the uppermost layer; or, Prepare a metal oxide layer, A low-temperature polysilicon layer is prepared on the upper surface of the metal oxide layer, Further preparing a metal oxide layer on the upper surface of the low temperature polysilicon layer; or, Prepare a metal oxide layer, A low-temperature polysilicon layer is prepared on the upper surface of the metal oxide layer, Prepare a single crystal silicon layer on the upper surface of the low temperature polysilicon layer; or, Prepare a low temperature polysilicon layer, A metal oxide layer is prepared on the upper surface of the low temperature polysilicon layer.

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