Semiconductor structure, forming method thereof and memory system

Abstract

The invention provides a semiconductor structure and a forming method thereof, and a memory system, the forming method comprises the steps: providing a substrate, forming a stack structure comprising insulating layers and conductive layers which are alternately stacked on the substrate, and a channel structure which penetrates through the stack structure and extends into the substrate, the channel structure comprises a channel layer and a functional layer surrounding the channel layer; removing the substrate, the conductive layer closest to the substrate and the insulating layer between the substrate, and exposing the conductive layer closest to the substrate and a part of the functional layer of the channel structure; and removing the exposed part of the functional layer of the channel structure to expose the part of the channel layer of the channel structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory system. Background Art

[0002] Three-dimensional memory is an emerging type of flash memory. Three-dimensional memory devices solve the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage units. Three-dimensional memory devices have excellent precision, support higher storage capacity in a smaller space, low cost, low power consumption, and can fully meet many needs.

[0003] However, three-dimensional memory still faces many challenges. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, on which a stacking structure including an insulating layer and a conductive layer alternately stacked and a channel structure are formed, the channel structure penetrates the stacking structure and extends into the substrate, and the channel structure includes a channel layer and a functional layer surrounding the channel layer;

[0008] Removing the substrate, the conductive layer closest to the substrate, and the insulating layer between the substrate to expose the conductive layer closest to the substrate and a portion of the functional layer of the channel structure;

[0009] The exposed portion of the functional layer of the channel structure is removed, so that a portion of the channel layer of the channel structure is exposed.

[0010] In an optional embodiment, the forming method further comprises:

[0011] forming a conductive structure, wherein the conductive structure is connected to the channel structure;

[0012] A welding layer is formed, wherein the welding layer is located on the conductive structure and connected to the conductive structure.

[0013] In an optional implementation, the forming of the conductive structure includes:

[0014] retaining the conductive layer closest to the substrate, wherein the conductive layer closest to the substrate constitutes the conductive structure;

[0015] The forming of the welding layer comprises:

[0016] A solder layer is formed in contact with the conductive layer closest to the substrate and the exposed channel layer.

[0017] In an optional embodiment, the forming method further includes

[0018] After removing the exposed part of the functional layer of the channel structure, removing the conductive layer closest to the substrate to expose the insulating layer;

[0019] The forming of the conductive structure comprises:

[0020] A conductive structure is formed in contact with the exposed channel layer and the exposed insulating layer.

[0021] In an optional embodiment, the forming method further comprises:

[0022] forming a dielectric layer covering the conductive structure;

[0023] forming a first contact structure penetrating the dielectric layer, wherein the first contact structure contacts the conductive structure;

[0024] The forming of the welding layer comprises:

[0025] A welding layer contacting the first contact structure is formed on the dielectric layer.

[0026] In an optional embodiment, the stacked structure includes: a first part and a second part arranged in parallel along a first direction; the first part includes alternately stacked insulating layers and conductive layers, the second part includes alternately stacked insulating layers and sacrificial layers, and the channel structure is located in the first part; the first direction is perpendicular to the stacking direction of the stacked structure; a second contact structure penetrating the second part is formed in the stacked structure;

[0027] The removing of the substrate, the conductive layer closest to the substrate, and the insulating layer between the substrate to expose the conductive layer closest to the substrate and a portion of the functional layer of the channel structure includes:

[0028] The substrate, the insulating layer between the conductive layer closest to the substrate and the substrate, and the insulating layer between the sacrificial layer closest to the substrate and the substrate are removed to expose part of the functional layer of the channel structure, the conductive layer closest to the substrate, and the sacrificial layer closest to the substrate.

[0029] In an optional embodiment, the forming of the welding layer includes:

[0030] The welding layer is formed on both the first part and the second part; the welding layer is in contact with the exposed partial functional layer of the channel structure, the exposed conductive layer closest to the substrate, the exposed sacrificial layer closest to the substrate and the second contact structure.

[0031] In an optional embodiment, the forming method further comprises:

[0032] forming a first bonding layer on a side of the stack structure away from the substrate;

[0033] Providing a peripheral circuit wafer; the peripheral circuit wafer comprises a peripheral circuit and a second bonding layer located on the peripheral circuit;

[0034] The first bonding layer and the second bonding layer are bonded.

[0035] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0036] A stacked structure comprising alternately stacked insulating layers and conductive layers; a channel structure comprising a first sub-portion penetrating the stacked structure and a second sub-portion protruding from the stacked structure; the first sub-portion comprising a channel layer and a functional layer, and the second sub-portion comprising a channel layer;

[0037] a conductive structure connected to the second subsection;

[0038] The welding layer is located on the conductive structure and connected to the conductive structure.

[0039] In an optional embodiment, the conductive layer closest to the welding layer constitutes the conductive structure;

[0040] The conductive structure contacts a sidewall of the first subsection;

[0041] The solder layer contacts both the conductive structure and the second sub-portion.

[0042] In an optional implementation, the material of the conductive structure includes tungsten.

[0043] In an optional implementation, the conductive structure is in contact with both the second sub-portion and the insulating layer closest to the conductive structure.

[0044] In an optional implementation, the material of the conductive structure includes polysilicon.

[0045] In an optional implementation, the semiconductor structure further includes:

[0046] a plurality of first contact structures, located on the conductive structure and in contact with the conductive structure;

[0047] The welding layer is located on the first contact structure and contacts the first contact structure.

[0048] In an optional embodiment, the material of the welding layer includes aluminum.

[0049] In an optional embodiment, the stacking structure includes: a first part and a second part arranged in parallel along a first direction;

[0050] The first part includes alternately stacked insulating layers and conductive layers, the second part includes alternately stacked insulating layers and sacrificial layers, and the channel structure is located in the first part; a second contact structure penetrating the second part is also formed in the stacking structure; the first direction is perpendicular to the stacking direction of the stacking structure.

[0051] In an optional implementation, the welding layer contacts the sacrificial layer closest to the welding layer; and the second contact structure extends into the welding layer and contacts the welding layer.

[0052] In an optional embodiment, the conductive structure is located on the first part and the second part, and is in contact with both the sacrificial layer closest to the conductive structure and the insulating layer closest to the conductive structure; and the bottom surface of the sacrificial layer closest to the conductive structure is flush with the bottom surface of the conductive structure located on the first part.

[0053] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0054] At least one semiconductor structure according to any one of the above embodiments;

[0055] The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

[0056] In the technical solution provided in the present disclosure, the insulating layer between the conductive layer closest to the substrate and the substrate is removed with the conductive layer closest to the substrate as a stop layer, and the part of the functional layer of the exposed channel structure is removed with the conductive layer closest to the substrate as a stop layer, so as to expose part of the channel layer. On the one hand, the etching selectivity of the material of the functional layer and the material of the conductive layer is relatively large, and the etching selectivity ratio of the insulating layer to the functional layer is also large, so that a better effect of removing the insulating layer and the functional layer can be achieved, and the impact on the conductive layer is small, so that the defect problem caused by using the semiconductor layer as a stop layer in the process of exposing the channel layer can be improved, thereby improving the performance of the semiconductor structure; on the other hand, using the conductive layer in the stacked structure as a stop layer improves the problem of restrictions on high temperature and oxidation process in the process when using polysilicon as a stop layer, so that the use of high temperature and oxidation process in the process of the semiconductor structure can be more flexible; on the other hand, using the conductive layer in the stacked structure as a stop layer, there is no need to form a stop layer separately, so that the process steps are reduced, the process materials are saved, thereby reducing the process cost and saving the production cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 and Figure 2 A schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure;

[0058] Figure 3 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0059] Figures 4 to 14 A schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure;

[0060] Fig.15 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0061] Fig.16 A schematic diagram of a memory system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0063] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0064] In the drawings, like reference numerals refer to like elements throughout.

[0065] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] The present disclosure provides a method for forming a semiconductor structure, referring to Figure 1 and Figure 2After the memory array wafer is bonded to the peripheral circuit wafer, the substrate 100 is removed from the back side (the side away from the peripheral circuit wafer) to expose the channel layer 105, and the channel layer 105 is subsequently led out from the back side. A multilayer structure of a first silicon oxide layer 120, a first polysilicon layer 121, a second silicon oxide layer 122, and a second polysilicon layer 123 is arranged between the stacked structure and the substrate. In the process of thinning to expose the channel layer 105 from the back side, the multilayer structure of the first silicon oxide layer 120, the first polysilicon layer 121, the second silicon oxide layer 122, and the second polysilicon layer 123 are used as stop layers in sequence, thereby removing the first silicon oxide layer 120, the first polysilicon layer 121, and the second silicon oxide layer 122 on the substrate 100 and the channel structure in sequence, stopping on the second polysilicon layer 123, and using the second polysilicon layer 123 to remove the exposed functional layer, thereby exposing part of the channel layer, so that the channel layer 105 can be led out from the back side in the subsequent process.

[0068] However, the method provided in the above embodiment uses the second polysilicon layer 123 as a stop layer, which is more likely to produce unfriendly contours such as polysilicon missing (Poly Missing), oxidation (Oxidation) and bending (Bending) during the subsequent process, which ultimately affects the performance of the memory; on the other hand, after the first polysilicon layer 121 and the second polysilicon layer 123 are formed, there are more oxidation and high-temperature processes in the subsequent process, and the polysilicon material is not resistant to oxidation and high temperature, which limits the subsequent oxidation and high-temperature processes; on the other hand, using a multi-layered structure as a stop layer requires additional process steps such as edge etching to avoid residual defects, and the process steps are more complicated.

[0069] Based on the above problems, the present disclosure provides a method for forming a semiconductor structure. Figure 3 Schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 3 As shown, the method for forming a semiconductor structure includes the following steps:

[0070] Step S10: providing a substrate, on which a stacking structure including an insulating layer and a conductive layer alternately stacked and a channel structure are formed, wherein the channel structure penetrates the stacking structure and extends into the substrate, and the channel structure includes a channel layer and a functional layer surrounding the channel layer;

[0071] Step S20: removing the substrate, the conductive layer closest to the substrate and the insulating layer between the substrate, exposing the conductive layer closest to the substrate and a portion of the functional layer of the channel structure;

[0072] Step S30: removing the exposed portion of the functional layer of the channel structure, so as to expose a portion of the channel layer of the channel structure.

[0073] Figures 4 to 12 The structure diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is as follows. Figures 4 to 12 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0074] Reference Figure 4 , perform step S10 to provide a substrate 100 , on which a stacking structure 103 and a channel structure 104 are formed.

[0075] In some embodiments, the substrate 100 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (e.g., a germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, etc.

[0076] In some embodiments, the stacking structure 103 includes: a first part 111 and a second part 112 arranged in parallel along a first direction; the first part 111 includes alternately stacked insulating layers 101 and conductive layers 102, the second part 112 includes alternately stacked insulating layers 101 and sacrificial layers 113, and the channel structure 104 is located in the first part 111; the first direction is perpendicular to the stacking direction of the stacking structure 103; and a second contact structure 119 is formed in the stacking structure 103 that passes through the second part 112.

[0077] In some specific examples, the first direction is the X-axis direction shown in the drawings of the present disclosure; the stacking direction of the stacked structure 103 is the Y-axis direction shown in the drawings of the present disclosure. However, it should be noted that the description of the directions in the following embodiments is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.

[0078] In some specific examples, the substrate 100 may include a first region and a second region arranged in parallel along a first direction, and the process of forming the stacked structure 103 includes: firstly, forming an insulating layer 101 and a sacrificial layer 113 alternately stacked along the Y-axis direction on both the first region and the second region by a deposition process; after forming a gate line slit (GLS), removing the sacrificial layer 113 on the second region, and retaining the sacrificial layer 113 on the first region; depositing a conductive layer 102 at a position where the sacrificial layer 113 is removed on the second region. Thus, a second portion 112 of the stacked structure 103 is formed on the first region, and a first portion 111 of the stacked structure 103 is formed on the second region. In some specific examples, the method further includes filling the gate line slit to form a gate line slit structure 115.

[0079] In some specific examples, the material of the insulating layer 101 in the stacked structure 103 includes, but is not limited to, one or more of silicon oxide layers. The material of the sacrificial layer 113 includes, but is not limited to, one or more of silicon nitride layers and silicon oxynitride layers; in some specific examples, the insulating layer 101 and the sacrificial layer 113 may have the same thickness as each other, or may have different thicknesses from each other. In some specific embodiments, the insulating layer 101 may be formed of silicon oxide (SiO2); the sacrificial layer 113 may be formed of silicon nitride (SiN). The material of the conductive layer 102 in the stacked structure 103 may include, but is not limited to, one or more of conductive materials such as tungsten, cobalt, copper, and aluminum.

[0080] In some specific examples, the material of the gate line gap structure 115 may be one or more of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and semiconductor materials such as polysilicon. In some specific examples, the material of the second contact structure 119 includes but is not limited to tungsten, and the second contact structure 119 may extend into the substrate 100. In other specific examples, the second contact structure 119 does not extend into the substrate 100. The following embodiments will be further described by taking the second contact structure 119 extending into the substrate 100 as an example.

[0081] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0082] It should be noted that Figure 4 The numbers of the conductive layer 102 , the insulating layer 101 , and the sacrificial layer 113 are only examples, and the present disclosure does not limit the specific numbers of the conductive layer 102 , the insulating layer 101 , and the sacrificial layer 113 .

[0083] In some specific examples, the formation process of the channel structure 104 may include: forming a channel hole penetrating the stacked structure 103; after forming the channel hole, sequentially forming a blocking layer, a charge trapping layer, a tunneling layer and a channel layer 105 from the outside to the inside along the radial direction of the channel hole, so as to form a memory material layer in the channel hole. The blocking layer, the charge trapping layer and the tunneling layer constitute the functional layer 106 of the channel structure 104, wherein the blocking layer covers the sidewall surface of the channel hole, the charge trapping layer covers the surface of the blocking layer, the tunneling layer covers the surface of the charge trapping layer, and the channel layer 105 covers the surface of the tunneling layer, forming an oxide-nitride-oxide-polysilicon (ONOP) structure.

[0084] In some embodiments, the forming method further comprises:

[0085] forming a first bonding layer on a side of the stack structure 103 away from the substrate 100;

[0086] Providing a peripheral circuit wafer 114; the peripheral circuit wafer 114 includes a peripheral circuit and a second bonding layer located on the peripheral circuit;

[0087] The first bonding layer and the second bonding layer are bonded.

[0088] In some specific examples, the first bonding layer and the second bonding layer may be bonded by a hybrid bonding process.

[0089] It should be noted that the embodiment of the present disclosure takes the example of bonding the memory array wafer including the stacking structure 103 to the peripheral circuit wafer 114, and then performing the subsequent back lead-out process from the side of the substrate 100 away from the stacking structure 103. In other embodiments, the memory array wafer may be bonded to the peripheral circuit wafer 114 after performing the back lead-out process, or only the memory array wafer is formed, and the back lead-out process is performed on the memory array wafer.

[0090] Next, refer to Figures 5 to 7 , perform step S20 and step S30 to remove the substrate 100 , the insulating layer 101 between the conductive layer 102 closest to the substrate 100 and the substrate 100 , and the exposed portion of the functional layer 106 of the channel structure 104 .

[0091] In some specific examples, the substrate 100 can be first thinned from the side of the substrate 100 away from the stacking structure 103 by a grinding process, and then the substrate 100 can be removed by a wet etching process to expose the insulating layer 101 between the substrate 100 and the conductive layer 102 closest to the substrate 100, a portion of the second contact structure 119, a portion of the gate line gap structure 115, and a portion of the channel structure 104.

[0092] In some specific examples, refer to Figure 6 The method further includes depositing a first dielectric layer 117 on the exposed surface of the insulating layer 101. The material of the first dielectric layer 117 includes but is not limited to silicon oxide.

[0093] Next, refer to Figure 7 , using the sacrificial layer 113 and the conductive layer 102 closest to the substrate 100 as stop layers, the first dielectric layer 117 on the stacked structure 103, the insulating layer 101 between the substrate 100 and the conductive layer 102 closest to the substrate 100 are removed, thereby exposing the conductive layer 102 closest to the substrate 100 and a portion of the functional layer 106 of the channel structure 104. Then, the exposed portion of the functional layer 106 of the channel structure 104 is removed, so that a portion of the channel layer 105 of the channel structure 104 is exposed.

[0094] In some specific examples, methods for removing the first dielectric layer 117 , the insulating layer 101 , and the functional layer 106 include, but are not limited to, dry etching and wet etching.

[0095] It can be understood that in the embodiment of the present disclosure, the insulating layer 101 between the conductive layer closest to the substrate and the substrate is removed with the conductive layer closest to the substrate as the stop layer, and the part of the functional layer 106 of the exposed channel structure 104 is removed with the conductive layer closest to the substrate as the stop layer, exposing part of the channel layer 105. On the one hand, since the material of the conductive layer is generally a metal material, the etching selectivity of the material of the functional layer 106 and the material of the conductive layer 102 is relatively large, and the etching selectivity ratio of the insulating layer 101 to the functional layer 106 is also large, so that a better effect of removing the insulating layer 101 and the functional layer 106 can be achieved, and the impact on the conductive layer 101 is small, so that it can be The defect problem caused by using the semiconductor layer as a stop layer in the process of exposing the channel layer 105 is improved, thereby improving the performance of the semiconductor structure; on the other hand, the conductive layer 102 in the stacked structure 103 is directly used as the stop layer, which improves the problem of restrictions on high temperature and oxidation process in the process when using polysilicon as the stop layer, making the use of high temperature and oxidation process in the process of the semiconductor structure more flexible; on the other hand, by using the conductive layer 102 in the stacked structure 103 as a stop layer, there is no need to form a stop layer separately, which reduces the process steps and saves process materials, thereby reducing process costs and saving production cycles.

[0096] In some embodiments, removing the substrate 100, the conductive layer 102 closest to the substrate 100, and the insulating layer 101 between the substrate 100 to expose the conductive layer 102 closest to the substrate 100 and a portion of the functional layer 106 of the channel structure 104 includes:

[0097] The substrate 100, the insulating layer 101 between the conductive layer 102 closest to the substrate 100 and the substrate 100, and the insulating layer 101 between the sacrificial layer 113 closest to the substrate 100 and the substrate 100 are removed to expose a portion of the functional layer 106 of the channel structure 104, the conductive layer 102 closest to the substrate 100, and the sacrificial layer 113 closest to the substrate 100.

[0098] In some specific examples, the method further includes: performing ion implantation and laser activation on the channel layer 105 .

[0099] In some embodiments, the forming method further comprises:

[0100] forming a conductive structure 107, wherein the conductive structure 107 is connected to the channel structure 104;

[0101] A welding layer 108 is formed. The welding layer 108 is located on the conductive structure 107 and connected to the conductive structure 107 .

[0102] It should be noted that the connection in the embodiments of the present disclosure includes direct connection and indirect connection.

[0103] In some embodiments, the material of the welding layer 108 includes, but is not limited to, aluminum.

[0104] Regarding how to form the conductive structure 107 and the welding layer 108, the present disclosure provides two solutions. Figures 8 to 9 The first option is described in detail.

[0105] In some embodiments, forming the conductive structure 107 includes:

[0106] The conductive layer 102 closest to the substrate 100 is retained, and the conductive layer 102 closest to the substrate 100 constitutes the conductive structure 107;

[0107] The forming of the welding layer 108 comprises:

[0108] A solder layer 108 is formed to contact the conductive layer 102 closest to the substrate 100 and the exposed channel layer 105 .

[0109] Here, the conductive structure 107 formed by the conductive layer 102 closest to the substrate 100 may serve as a source layer.

[0110] In some embodiments, forming the welding layer 108 includes:

[0111] The welding layer 108 is formed on both the first part 111 and the second part 112; the welding layer 108 is in contact with the exposed partial functional layer 106 of the channel structure 104, the exposed conductive layer 102 closest to the substrate 100, the exposed sacrificial layer 113 closest to the substrate 100, and the second contact structure 119.

[0112] It can be understood that in scheme one, the conductive layer 102 closest to the substrate 100 is retained, and a welding layer 108 is formed directly on the exposed conductive layer 102 closest to the substrate 100 and the exposed sacrificial layer 113 closest to the substrate 100. The welding layer 108 is in contact with the exposed partial functional layer 106 of the channel structure 104, the exposed conductive layer 102 closest to the substrate 100, the exposed sacrificial layer 113 closest to the substrate 100, and the second contact structure 119. The conductive layer 102 closest to the substrate 100 can be connected to the channel layer 105 of the channel structure 104 through the welding layer 108, so that the conductive layer 102 closest to the substrate 100 can be used as a source layer.

[0113] In the embodiment of the present disclosure, on the basis of utilizing the conductive layer 102 closest to the substrate 100 as a stop layer to expose the channel layer 105, the conductive layer 102 closest to the substrate 100 is ultimately retained, and the conductive layer 102 closest to the substrate 100 is cleverly used as a source layer. That is to say, the bottom conductive layer in the stacked structure is not used to form a gate, but is directly used as a source layer, without the need to form additional material for the source layer, thereby reducing the process flow and saving process costs.

[0114] In some specific examples, refer to Fig. 9 The method further includes removing a portion of the material of the conductive structure 107 so that the second contact structure 119 and the channel structure 104 can be led out separately.

[0115] Combine the following Figure 10 to Figure 11 The method for forming the conductive structure 107 and the welding layer 108 in the second solution is described in detail.

[0116] In some embodiments, reference Fig.10 , the forming method further comprises

[0117] After removing the exposed portion of the functional layer 106 of the channel structure 104 , the conductive layer 102 closest to the substrate 100 is removed to expose the insulating layer 101 .

[0118] In some specific examples, the method of removing the conductive layer 102 closest to the substrate 100 includes but is not limited to an etching process. An adhesion layer is also formed between the conductive layer 102 and the insulating layer 101, and the material of the adhesion layer includes but is not limited to titanium nitride. Before removing the conductive layer 102 closest to the substrate 100, the adhesion layer is also removed.

[0119] Next, refer to Fig.11 , the forming of the conductive structure 107 comprises:

[0120] A conductive structure 107 is formed to contact the exposed channel layer 105 and the exposed insulating layer 101 .

[0121] Here, the conductive structure 107 is also in contact with the second contact structure 119 and the sacrificial layer 113 .

[0122] In some specific examples, the method of forming the conductive structure 107 includes, but is not limited to, a deposition process.

[0123] In some specific examples, the method further includes performing ion implantation and laser activation on the channel layer 105 of the channel structure 104 .

[0124] In some embodiments, reference Fig.12 , the forming method further comprises:

[0125] forming a dielectric layer 109 covering the conductive structure 107;

[0126] forming a first contact structure 110 penetrating the dielectric layer 109 , wherein the first contact structure 110 is in contact with the conductive structure 107 ;

[0127] The forming of the welding layer 108 comprises:

[0128] A welding layer 108 contacting the first contact structure 110 is formed on the dielectric layer 109 .

[0129] In some specific examples, the method of forming the dielectric layer 109 includes but is not limited to a deposition process, and the material of the dielectric layer 109 includes but is not limited to silicon oxide. The material of the first contact structure 110 includes but is not limited to tungsten.

[0130] In some specific examples, the method further includes: after forming the conductive structure 107, removing a portion of the conductive structure 107 material on the second contact structure 119, and forming a second dielectric layer 118 at the position where the portion of the conductive structure 107 material is removed; the dielectric layer 109 not only covers the conductive structure 107 but also covers the second dielectric layer 118. Here, the second contact structure 119 can be connected to the peripheral circuit in the peripheral circuit wafer 114 through the interconnection layer, the first contact structure 110 penetrates the second dielectric layer 118 and the dielectric layer 109, and the welding layer 108 is connected to the second contact structure 119 through the first contact structure 110, thereby realizing the lead-out of the peripheral circuit.

[0131] Based on the same concept as the method for forming the semiconductor structure in the aforementioned embodiment, the embodiment of the present disclosure further provides a semiconductor structure, Fig.13 as well as Fig.14 A schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present disclosure.

[0132] Reference Fig.13 as well as Fig.14 , the semiconductor structure provided by the embodiment of the present disclosure includes:

[0133] The stacked structure 103 includes insulating layers 101 and conductive layers 102 that are alternately stacked;

[0134] The channel structure 104 includes a first sub-portion penetrating the stack structure 103 and a second sub-portion protruding from the stack structure 103; the first sub-portion includes a channel layer 105 and a functional layer 106, and the second sub-portion includes the channel layer 105;

[0135] a conductive structure 107 connected to the second sub-portion;

[0136] The welding layer 108 is located on the conductive structure 107 and connected to the conductive structure 107 .

[0137] In some embodiments, the stack structure 103 includes: a first portion 111 and a second portion 112 arranged in parallel along a first direction;

[0138] The first part 111 includes alternately stacked insulating layers 101 and conductive layers 102, the second part 112 includes alternately stacked insulating layers 101 and sacrificial layers 113, the channel structure 104 is located in the first part 111; a second contact structure 119 is also formed in the stacking structure 103 and penetrates the second part 112; the first direction is perpendicular to the stacking direction of the stacking structure 103.

[0139] In some embodiments, the material of the welding layer 108 includes aluminum.

[0140] The following will be combined Fig.13 First, the conductive structure 107 and the welding layer 108 formed by the method provided in the scheme 1 in the above method embodiment are specifically introduced.

[0141] In some embodiments, the conductive layer 102 closest to the welding layer 108 constitutes the conductive structure 107;

[0142] The conductive structure 107 is in contact with the sidewall of the first sub-portion;

[0143] The solder layer 108 contacts both the conductive structure 107 and the second sub-portion.

[0144] Here, the conductive structure 107 formed by the conductive layer 102 closest to the substrate 100 may serve as a source layer.

[0145] In some embodiments, the welding layer 108 contacts the sacrificial layer 113 closest to the welding layer 108 ; the second contact structure 119 extends into the welding layer 108 and contacts the welding layer 108 .

[0146] In some embodiments, the material of the conductive structure 107 includes tungsten.

[0147] Next, combine Fig.14 The conductive structure 107 and the welding layer 108 formed by the method provided in the second solution in the above method embodiment are specifically introduced.

[0148] In some embodiments, the conductive structure 107 is in contact with both the second sub-portion and the insulating layer 101 closest to the conductive structure 107 .

[0149] In some embodiments, the material of the conductive structure 107 includes polysilicon.

[0150] In some embodiments, the semiconductor structure further comprises:

[0151] A plurality of first contact structures 110 , located on the conductive structure 107 and in contact with the conductive structure 107 ;

[0152] The welding layer 108 is located on the first contact structure 110 and contacts the first contact structure 110 .

[0153] In some embodiments, the conductive structure 107 is located on the first part 111 and the second part 112, and is in contact with the sacrificial layer 113 closest to the conductive structure 107 and the insulating layer 101 closest to the conductive structure 107; and the bottom surface of the sacrificial layer 113 closest to the conductive structure 107 is flush with the bottom surface of the conductive structure 107 located on the first part 111.

[0154] In some specific examples, such as Fig.13 as well as Fig.14 As shown, the semiconductor structure further includes a gate line gap structure 115 penetrating the stacked structure 103 .

[0155] In some specific examples, the semiconductor structure may include a memory array, wherein the memory array may be a 3D NAND memory array.

[0156] In some embodiments, the semiconductor structure may further include a peripheral circuit wafer 114. The peripheral circuit wafer 114 is provided with a peripheral circuit coupled to the memory array.

[0157] In some other embodiments, the semiconductor structure may not include the peripheral circuit wafer 114 , that is, the semiconductor structure provided by the present disclosure may be only a memory array wafer.

[0158] In some embodiments, the semiconductor structure may be a memory including a peripheral circuit. Fig.15 Schematic diagram of a memory provided by an embodiment of the present disclosure. Fig.15 As shown, the memory 900 includes a storage array 901, the storage array 901 includes a plurality of storage blocks 903, each storage block 903 includes a plurality of storage strings 904, and a plurality of storage cells in a storage string 904 may correspond to Fig.13 Each memory block 903 includes a plurality of word lines 905, which may correspond to a plurality of memory cells corresponding to a channel structure 104. Fig.13 The conductive layer 102 in the embodiment of the present invention.

[0159] The memory 900 may further include a peripheral circuit 902 coupled to the memory array 901. In some specific examples, the peripheral circuit 902 may include circuit elements including page buffer sense amplifiers, column decoders / bit line drivers, row decoders / word line drivers, voltage generators, control logic units, registers, interfaces, and data buses.

[0160] In the embodiment of the present disclosure, the memory 900 includes but is not limited to a 3D NAND memory.

[0161] Reference Fig.16 The present disclosure also provides a memory system 1000, comprising: at least one semiconductor structure in any of the above embodiments and a controller 1002; the controller 1002 is coupled to the at least one semiconductor structure and configured to control the semiconductor structure. Here, the semiconductor structure may be the memory 1001.

[0162] In some embodiments, the controller 1002 and the one or more memories 1001 may be integrated into various types of storage devices, that is, the memory system 1000 may be implemented and packaged into different types of terminal electronic products.

[0163] In some specific examples, the memory system 1000 can be a compact flash card (CFC), a smart media card (SMC), a memory stick (MS), a multimedia card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card (SD card), such as Mini SD card, Micro SD card, SDHC card, etc., a universal flash storage (UFS) card and a solid state drive (SSD).

[0164] In other specific examples, the memory system 1000 may be placed in a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0165] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0166] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0167] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacking structure including an insulating layer and a conductive layer alternately stacked and a channel structure are formed, the channel structure penetrates the stacking structure and extends into the substrate, and the channel structure includes a channel layer and a functional layer surrounding the channel layer; Removing the substrate, the conductive layer closest to the substrate, and the insulating layer between the substrate to expose the conductive layer closest to the substrate and a portion of the functional layer of the channel structure; The exposed portion of the functional layer of the channel structure is removed, so that a portion of the channel layer of the channel structure is exposed.

2. The forming method according to claim 1, characterized in that: The forming method further comprises: forming a conductive structure, wherein the conductive structure is connected to the channel structure; A welding layer is formed, wherein the welding layer is located on the conductive structure and connected to the conductive structure.

3. The forming method according to claim 2, characterized in that: The forming of the conductive structure comprises: retaining the conductive layer closest to the substrate, wherein the conductive layer closest to the substrate constitutes the conductive structure; The forming of the welding layer comprises: A solder layer is formed in contact with the conductive layer closest to the substrate and the exposed channel layer.

4. The forming method according to claim 2, characterized in that: The formation method further comprises, after removing the exposed part of the functional layer of the channel structure, removing the conductive layer closest to the substrate to expose the insulating layer; The forming of the conductive structure comprises: A conductive structure is formed in contact with the exposed channel layer and the exposed insulating layer.

5. The forming method according to claim 4, characterized in that: The forming method further comprises: forming a dielectric layer covering the conductive structure; forming a first contact structure penetrating the dielectric layer, wherein the first contact structure contacts the conductive structure; The forming of the welding layer comprises: A welding layer contacting the first contact structure is formed on the dielectric layer.

6. The forming method according to claim 2, characterized in that: The stacked structure comprises: a first part and a second part arranged in parallel along a first direction; the first part comprises an insulating layer and a conductive layer alternately stacked, the second part comprises an insulating layer and a sacrificial layer alternately stacked, and the channel structure is located in the first part; the first direction is perpendicular to the stacking direction of the stacked structure; a second contact structure penetrating the second part is formed in the stacked structure; The removing of the substrate, the conductive layer closest to the substrate, and the insulating layer between the substrate to expose the conductive layer closest to the substrate and a portion of the functional layer of the channel structure includes: The substrate, the insulating layer between the conductive layer closest to the substrate and the substrate, and the insulating layer between the sacrificial layer closest to the substrate and the substrate are removed to expose part of the functional layer of the channel structure, the conductive layer closest to the substrate, and the sacrificial layer closest to the substrate.

7. The forming method according to claim 6, characterized in that: The forming of the welding layer comprises: The welding layer is formed on both the first part and the second part; the welding layer contacts the exposed partial functional layer of the channel structure, the exposed conductive layer closest to the substrate, the exposed sacrificial layer closest to the substrate and the second contact structure.

8. The forming method according to claim 1, characterized in that: The forming method further comprises: forming a first bonding layer on a side of the stack structure away from the substrate; Providing a peripheral circuit wafer; the peripheral circuit wafer comprises a peripheral circuit and a second bonding layer located on the peripheral circuit; The first bonding layer and the second bonding layer are bonded.

9. A semiconductor structure, characterized in that: include: A stacked structure comprising alternately stacked insulating layers and conductive layers; a channel structure, comprising a first sub-portion penetrating the stacked structure and a second sub-portion protruding from the stacked structure; The first sub-portion includes a channel layer and a functional layer, and the second sub-portion includes a channel layer; a conductive structure connected to the second subsection; The welding layer is located on the conductive structure and connected to the conductive structure.

10. The semiconductor structure according to claim 9, characterized in that: The conductive layer closest to the welding layer constitutes the conductive structure; The conductive structure contacts a sidewall of the first subsection; The solder layer contacts both the conductive structure and the second sub-portion.

11. The semiconductor structure according to claim 10, characterized in that: The material of the conductive structure includes tungsten.

12. The semiconductor structure according to claim 9, characterized in that: The conductive structure is in contact with both the second sub-portion and the insulating layer closest to the conductive structure.

13. The semiconductor structure according to claim 12, characterized in that: The material of the conductive structure includes polysilicon.

14. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure further comprises: a plurality of first contact structures, located on the conductive structure and in contact with the conductive structure; The soldering layer is located on the first contact structure and contacts the first contact structure.

15. The semiconductor structure according to claim 9, characterized in that The material of the welding layer includes aluminum.

16. The semiconductor structure according to claim 9, characterized in that The stacking structure comprises: a first part and a second part arranged in parallel along a first direction; The first part includes alternately stacked insulating layers and conductive layers, the second part includes alternately stacked insulating layers and sacrificial layers, and the channel structure is located in the first part; a second contact structure penetrating the second part is also formed in the stacking structure; the first direction is perpendicular to the stacking direction of the stacking structure.

17. The semiconductor structure according to claim 16, characterized in that: The welding layer contacts the sacrificial layer closest to the welding layer; the second contact structure extends into the welding layer and contacts the welding layer.

18. The semiconductor structure according to claim 16, characterized in that The conductive structure is located on the first part and the second part, and contacts both the sacrificial layer closest to the conductive structure and the insulating layer closest to the conductive structure; and the bottom surface of the sacrificial layer closest to the conductive structure is flush with the bottom surface of the conductive structure located on the first part.

19. A memory system, characterized in that: include: At least one semiconductor structure according to any one of claims 9 to 18; The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

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