Power converter package with common mode conducted emission shielding

Abstract

The invention relates to a power converter package (100) for converting a first DC voltage and a second DC voltage into a common AC voltage. The power converter package includes a first power semiconductor (130) and a second power semiconductor (140), a first substrate (110) and a second substrate (120). The first substrate (110) comprises a first supply voltage region (113) for providing the first DC voltage and a second supply voltage region (114) for providing the second DC voltage. The first substrate (110) comprises a base metal region (115) arranged on a first substrate lower main face (112). The base metal region (115) is used to extract dissipated heat from the first power semiconductor (130) and the second power semiconductor (140). The second substrate (120) comprises an AC voltage output region (150) for providing the AC voltage. By disposing the second supply voltage region (114) between the AC voltage output region (150) and the base metal region (115), the second supply voltage region (114) is used to isolate and shield the AC voltage output region (150) from the base metal region (115). Major embodiments of the present invention may employ lateral current flow devices, reduce AC voltage regions, and employ a second substrate that does not include heat generating devices.

Description

Technical Field

[0001] The present invention relates to the field of module packaging and assembly, in particular to packages based on chip embedding, PCB or ceramic substrate, such as DBC, AMB, etc. The present invention also relates to fast switching power supply device packages, for example, packages that take advantage of wide bandgap (WBG) semiconductors such as SiC or GaN as needed. The frequency range can be from 50kHz to several MHz, where the switching frequency may cause EMI problems. The present invention particularly relates to a power converter package with common-mode conducted emission shielding and a multi-phase system comprising a plurality of such power converter packages. Specifically, the present invention relates to a structure and method for internally isolating and shielding power modules to prevent common-mode conducted electromagnetic emissions. Background Art

[0002] A power converter typically includes a power module, which includes two or more power semiconductors, two or more DC voltage supply terminals (+ = high side (HS); – = low side (LS)), one or more alternating current (AC) voltage terminals, several control and sensing terminals, and a metal thermal interface (heat sink). When the operating voltage is above 100V, the metal thermal interface area is usually connected to the ground (GND) potential, while the direct current (DC) voltage terminal is isolated from the GND potential, or in some systems, the DC– (i.e., low side) or lower voltage potential can be equal to the GND potential. During operation, an AC voltage is generated at the AC voltage terminal, and the AC voltage fluctuates between positive and negative DC voltage levels.

[0003] In power modules used for power conversion, common mode (CM) conducted electromagnetic emission (EMI) may exceed the permissible levels given by national or international standards or regulatory requirements. At switching frequencies in the hundreds of kHz to MHz range, capacitive or inductive coupling effects become severe as the rate of change of voltage dV / dt and current dI / dt, respectively, reaches levels that cause considerable current / voltage to enter nearby conductor structures.

[0004] For these coupling effects, measures need to be taken to compensate for the unwanted EMI coupling effects through large filters. The filters may reduce or even eliminate all the benefits of using wide bandgap semiconductors with fast switching capabilities.

[0005] Therefore, it is worthwhile to spend considerable effort to avoid capacitive / inductive coupling effects through special design / structure of the power module. Summary of the invention

[0006] The present invention provides a solution to overcome the above EMI problem. In particular, the present invention discloses a novel capacitor shielding technology in a power module assembly to reduce CM conducted EMI.

[0007] The above and other aims and other objects are achieved by the features of the independent claims. Further implementations are apparent from the dependent claims, the description and the drawings.

[0008] The present invention provides embodiments for implementing novel capacitor shielding technology in a power module assembly or a power converter package. The various embodiments provided by the present invention can be divided into the following two types:

[0009] (a) Embodiments 1, 2 and 6 constitute completely new arrangements that have technical advantages over existing power converter arrangements. This can be achieved by reducing complexity, increasing the freedom to choose cost-effective materials, and improving thermal management.

[0010] (b) Embodiments 3, 4 and 5 combine power converter arrangements in a new way, and this new way can apply EMI shielding technology to more different types of power semiconductors.

[0011] The present invention provides a solution for providing integrated capacitive EMI shielding of common mode conducted emission (CM EMI) in AC voltage region in power modules. EMI shielding is effectively provided in a better way with less effort and cost compared to currently available power modules, especially for semiconductor devices with longitudinal current flow.

[0012] The solution is based on the investigation of the possibilities of isolating and shielding the power module. The solution provided by the present invention covers the gap between currently available solutions and feasible variants extending to future power modules including wide bandgap semiconductors.

[0013] A key concept is the use of a substrate for isolation and shielding between the AC voltage output region and the supply voltage region. The various embodiments provided herein describe how shielding can be achieved in various ways by arranging the power semiconductors, substrate, and conductor structures relative to each other and connecting them to a half-bridge topology (as an example).

[0014] The following features can be implemented in Embodiment 1, Embodiment 2 and Embodiment 6 described in more detail below, for example:

[0015] (1) mounting one or more dies on a substrate having a conductive layer on at least one side;

[0016] (2) The input terminals of the HS and LS dies are connected to this layer;

[0017] (3) Install an additional substrate on top of the substrate next to the power die;

[0018] (4) output terminals of the two dies are connected to the additional substrate;

[0019] (5) The AC voltage output terminal of the component is located on the top of the additional substrate and is isolated and shielded from the substrate.

[0020] The following features can be realized in Embodiments 3 to 5 described in more detail below, for example:

[0021] (1) The solution targets lateral current flow devices, which are not covered by existing solutions;

[0022] (2) mounting one or more dies on a substrate having a conductive layer on at least one side;

[0023] (3) The input terminals of the HS and LS dies are connected to this layer;

[0024] (4) Install an additional substrate on top of the substrate next to the power die;

[0025] (5) The AC output terminal and the HS semiconductor or LS semiconductor are located on an additional substrate;

[0026] (6) The output terminals of the two dies are connected to an additional substrate;

[0027] (7) The additional substrate is used to isolate and shield the AC voltage output area from the supply voltage area.

[0028] To describe the present invention in detail, the following terms, abbreviations and symbols are used:

[0029] DC Direct Current

[0030] AC

[0031] HS High pressure side

[0032] LS Low pressure side

[0033] GND Ground

[0034] CM Common Mode

[0035] EMI Electromagnetic Emission

[0036] DBC Direct Bond Copper

[0037] AMB Active Metal Brazing

[0038] WBG Wide Band Gap

[0039] SiC Silicon Carbide

[0040] GaN Gallium Nitride

[0041] The solution provided by the present invention can be applied to power semiconductors with longitudinal current flow (hereinafter referred to as longitudinal devices), and can also be applied to power semiconductors with transverse current flow (hereinafter referred to as transverse devices).

[0042] In power semiconductors with longitudinal current flow, the longitudinal current flows through the back side of the semiconductor chip. Typically, both HS (high side, positive supply voltage region, DC+) and LS semiconductors are face-up, where the face-up side is the front side of the semiconductor, i.e., the side on which most of the semiconductor manufacturing processes are performed. This side usually constitutes the terminal for snap-on or wire-bonding interconnection.

[0043] Power semiconductors with longitudinal current flow can be insulated gate bipolar transistors (IGBTs) and freewheeling diodes (FRDs), or SiC-based MOSFETs, etc. However, GaN-based semiconductors and many Si-based MOSFETs are in principle semiconductors with lateral current flow (lateral devices). That is, the switching current enters and remains on the front side of the semiconductor.

[0044] According to a first aspect, the present invention relates to a power converter package for converting a first DC voltage and a second DC voltage into a common AC voltage, the power converter package comprising: a first power semiconductor and a second power semiconductor, the first power semiconductor and the second power semiconductor being used to generate the common AC voltage according to switching between the first DC voltage and the second DC voltage; a first substrate, the first substrate having a first substrate upper main surface and a first substrate lower main surface opposite to the first substrate upper main surface, the first substrate comprising a first power supply voltage region for providing the first DC voltage and a second power supply voltage region for providing the second DC voltage, the first power supply voltage region and the second power supply voltage region being arranged on the first substrate upper main surface, wherein the first substrate comprises a base metal region arranged on the first substrate lower main surface, the base metal region being used to extract dissipated heat from the first power semiconductor and the second power semiconductor, the first power semiconductor having a first semiconductor upper main surface and a first semiconductor lower main surface opposite to the first semiconductor upper main surface, the first power semiconductor comprising an input terminal and an output terminal, wherein the input terminal of the first power semiconductor is connected to the first power supply voltage region, the second power semiconductor has a second semiconductor upper main surface and a second semiconductor lower main surface opposite to the second semiconductor upper main surface, the second power semiconductor includes an input terminal and an output terminal, wherein the input terminal of the second power semiconductor is electrically coupled to the second power supply voltage region; a second substrate, the second substrate has a second substrate upper main surface and a second substrate lower main surface opposite to the second substrate upper main surface, the second substrate includes an AC voltage output region for providing the AC voltage, the AC voltage output region is arranged on the top of the second substrate upper main surface, wherein the AC voltage output region is electrically coupled to the output terminal of the first power semiconductor and the output terminal of the second power semiconductor, wherein the second substrate lower main surface is arranged on the top of the second power supply voltage region, wherein by arranging the second power supply voltage region between the AC voltage output region and the base metal region, the second power supply voltage region is used to isolate and shield the AC voltage output region from the base metal region.

[0045] This power converter package provides integrated capacitive EMI shielding within the package against common mode conducted emissions in the AC voltage region.

[0046] Due to the shielding effect, the effect of forming a capacitor between the AC output area and the base metal area, which couples high-frequency noise to the base metal area, can be significantly reduced. As a result, fast-switching power semiconductor devices such as GaN devices or SiC devices can be efficiently implemented in the converter.

[0047] In an exemplary implementation of the power converter package, the second supply voltage region is arranged at least partially below the second semiconductor lower main face and extends below the AC voltage output region.

[0048] This overlap of the second supply voltage region and the AC voltage output region may produce a shielding function, thereby reducing common mode EMI.

[0049] Exemplary implementations of power converter packages corresponding to different embodiments are described below.Except for the sixth embodiment, all exemplary implementations describe a lateral device arrangement.

[0050] In an exemplary implementation of a power converter package corresponding to the first embodiment, the first power semiconductor and the second power semiconductor are lateral devices, the input terminal of the first power semiconductor is arranged on the main surface of the first semiconductor, and the input terminal of the second power semiconductor is arranged on the main surface of the second semiconductor.

[0051] For such a lateral device, shielding can be advantageously achieved. The second substrate can be arranged next to the first power semiconductor and next to the second power semiconductor. This is the reason why the area of ​​the second substrate area is reduced and why there is no heat generating device on its top. Due to the reduced area, the requirements for thermal performance of the second substrate can be reduced.

[0052] In an exemplary implementation of a power converter package corresponding to the first embodiment, the first power semiconductor and the second power semiconductor are mounted face up on the first substrate, with the lower main surface of the first semiconductor facing the first power supply voltage region and the lower main surface of the second semiconductor facing the second power supply voltage region.

[0053] In such a power converter package, shielding may be advantageously achieved by using a cost-effective material for the second substrate because a significant amount of heat is not generated on the second substrate and does not need to be conducted away from the second substrate.

[0054] In an exemplary implementation of the power converter package corresponding to the first embodiment, the first supply voltage region extends at least partially below the first semiconductor lower main face.

[0055] This structure offers the advantage that the heat path under the second power semiconductor is optimized and the shielding substrate (ie the second substrate) does not require high thermal performance materials.

[0056] In an exemplary implementation of a power converter package corresponding to the second embodiment, the first power semiconductor and the second power semiconductor are both lateral devices and are mounted face up on the first substrate, with the first semiconductor lower main surface and the second semiconductor lower main surface facing the second supply voltage region.

[0057] For this power converter package, the same advantages described for the first embodiment apply.Shielding can be advantageously achieved by using a cost-effective material for the second substrate, as significant amounts of heat are not generated on the second substrate and need not be conducted away from the second substrate.

[0058] In an exemplary implementation of a power converter package corresponding to the second embodiment, the second supply voltage region extends at least partially below the first semiconductor lower main surface, at least partially below the second semiconductor lower main surface, and below the AC voltage output region.

[0059] For this power converter package, the same advantages described for the first embodiment apply: The thermal path under the second power semiconductor is optimized and the shielding substrate (ie, the second substrate) does not require high thermal performance materials.

[0060] In an exemplary implementation of the power converter package corresponding to the second embodiment, the first supply voltage region is arranged next to the first power semiconductor.

[0061] As with all other embodiments described in this invention, this offers the advantage of a compact design of the power converter package.

[0062] In an exemplary implementation of the power converter package corresponding to the third embodiment, the first power semiconductor and the second power semiconductor are mounted on the second substrate by flip-chip method, and the first semiconductor upper main surface and the second semiconductor upper main surface face the first substrate upper main surface.

[0063] Assuming that the first substrate and the second substrate are good thermal conductors, the flip-chip arrangement offers the advantage that heat can be better extracted from the lateral device, since the heat does not have to be conducted from the upper main face of the power semiconductor to the lower main face. Instead, the heat can be extracted directly to the heat sink via the second substrate and the first substrate.

[0064] The back side (lower main side) of the power semiconductor may or may not be electrically connected, which may provide optimization possibilities for certain applications.

[0065] In an exemplary implementation of the power converter package corresponding to the third embodiment, the second supply voltage region extends at least partially below the first semiconductor upper main surface, at least partially below the second semiconductor upper main surface, and below the AC voltage output region.

[0066] For this power converter package, the same advantages described for the first embodiment apply.The thermal path under the second power semiconductor is optimized.

[0067] In an exemplary implementation of the power converter package corresponding to the third embodiment, the first supply voltage region is arranged next to the first power semiconductor.

[0068] As with all other embodiments described in this invention, this offers the advantage of a compact design of the power converter package.

[0069] In an exemplary implementation of a power converter package corresponding to the fourth embodiment, the first power semiconductor is mounted face up on the first substrate, the second power semiconductor is mounted face up on the second substrate, the lower main surface of the first semiconductor faces the first power supply voltage region, and the lower main surface of the second substrate faces the second power supply voltage region.

[0070] For such a power converter package, optimal shielding against common mode EMI can be achieved because the AC voltage region has a maximum overlap with the second supply voltage region (DC supply region).

[0071] In an exemplary implementation of the power converter package corresponding to the fourth embodiment, the first supply voltage region extends at least partially below the first semiconductor lower main face.

[0072] For such a power converter package, the thermal path under the first power semiconductor is optimized since no additional substrate needs to be used.

[0073] In an exemplary implementation of the power converter package corresponding to the fifth embodiment, the first power semiconductor is mounted face up on the first substrate, the second power semiconductor is mounted on the second substrate by flip chip method, the lower main surface of the first semiconductor faces the first power supply voltage area, and the upper main surface of the second semiconductor faces the upper main surface of the second substrate.

[0074] For this power converter package, the AC voltage output area can be reduced to a small portion of the second substrate. In addition, the back side (lower main surface) of the second power semiconductor can be electrically connected or not. This can provide optimization possibilities for certain applications.

[0075] In an exemplary implementation of the power converter package corresponding to the fifth embodiment, the second supply voltage region extends at least partially below the second semiconductor upper main face and the AC voltage output region.

[0076] Assuming that the first substrate and the second substrate are good thermal conductors, the flip-chip arrangement of the second power semiconductor offers the advantage that heat can be better extracted from the lateral device, since the heat does not have to be conducted from the upper main face of the power semiconductor to the lower main face. Instead, the heat can be extracted directly to the heat sink via the second substrate and the first substrate.

[0077] In an exemplary implementation of the power converter package corresponding to the fifth embodiment, the first supply voltage region extends at least partially below the first semiconductor lower main face.

[0078] This is a feature of the power converter package according to the fifth embodiment.

[0079] In an exemplary implementation of a power converter package corresponding to the sixth embodiment, the first power semiconductor and the second power semiconductor are vertical devices; the input terminal and the output terminal of the first power semiconductor are arranged on opposite first semiconductor main surfaces; the input terminal and the output terminal of the second power semiconductor are arranged on opposite second semiconductor main surfaces.

[0080] For this power converter package, the same advantages described for the first embodiment apply.

[0081] In an exemplary implementation of the power converter package corresponding to the sixth embodiment, the first power semiconductor and the second power semiconductor are mounted face up on the first substrate, with the lower main surface of the first semiconductor facing the first power supply voltage region and the lower main surface of the second semiconductor facing the second power supply voltage region.

[0082] For this power converter package, the same advantages described for the first embodiment apply.

[0083] The second supply voltage region may extend at least partially below the second semiconductor lower main face and may extend at least partially below the second substrate lower main face.

[0084] In an exemplary implementation of the power converter package corresponding to the sixth embodiment, the first supply voltage region extends at least partially below the first semiconductor lower main face.

[0085] This arrangement minimizes the AC voltage area.

[0086] Shielding can be advantageously achieved by using cost-effective materials for the second substrate because a significant amount of heat is not generated on the second substrate and does not need to be conducted away from the second substrate.

[0087] In an exemplary implementation of the power converter package, the first power semiconductor and the second power semiconductor are electrically connected in a half-bridge topology.

[0088] This provides an advantage that the power converter package can be advantageously applied to automotive and industrial applications requiring a half bridge. In such applications, thermal performance can be improved by using the power converter package while EMI can be reduced.

[0089] In an alternative embodiment to Embodiment 1, Embodiment 2 or Embodiment 6, the second substrate may be made of a material with lower thermal conductivity, since heat does not need to be extracted through the substrate. This provides a cost advantage for the EMI shielding module.

[0090] In another embodiment, the first substrate and the second substrate may be a multi-layer ceramic substrate layer.

[0091] In another embodiment, the first substrate and the second substrate may be metallized quartz, ceramic or alumina filled organic composite material (= PCB laminate material or epoxy mold composite material in a narrow sense).

[0092] In an exemplary implementation of the power converter package, the AC voltage includes multiple phases; the AC voltage output region formed on the second substrate includes multiple isolated phase segments, each phase segment is associated with a corresponding phase of the AC voltage; the first substrate includes multiple first power supply voltage regions, each first power supply voltage region is associated with a corresponding phase of the AC voltage, wherein the first power supply voltage regions are electrically connected to each other; the second substrate includes multiple second power supply voltage regions, each second power supply voltage region is associated with a corresponding phase of the AC voltage, wherein the second power supply voltage regions are electrically connected to each other; the first substrate includes multiple base metal regions, each base metal region is associated with a corresponding phase of the AC voltage, wherein the base metal regions form a common base metal region.

[0093] In such a multi-phase module in one package, the first substrate and the second substrate can be shared between multiple phases. This means that the first supply voltage areas of all phases are fused together, the second supply voltage areas of all phases are fused together, and the base metal areas of all phases are fused to a common base metal area. The second substrate of each module can be mechanically connected. The second substrate can have a lower main surface electrical conductor area that is connected or not connected between multiple phases. The term "fused" in a broad sense can only have the meaning of "electrically connected to each other (not mechanically connected)". Therefore, there can be multiple independent modules, which function similarly to a three-phase system.

[0094] According to a second aspect, the present invention relates to a multi-phase system, comprising: a plurality of power converter packages according to the first aspect, wherein the first power supply voltage regions of the first substrates of the plurality of power converter packages are electrically connected to each other to form a common first power supply voltage region for all phases of the multi-phase system; wherein the second power supply voltage regions of the first substrates of the plurality of power converter packages are electrically connected to each other to form a common second power supply voltage region for all phases of the multi-phase system. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Other embodiments of the present invention will be described in conjunction with the following drawings, in which:

[0096] Figure 1 1 shows a schematic cross-sectional view of a power converter package 100 according to a first embodiment;

[0097] Figure 2 shows a schematic cross-sectional view of a power converter package 200 according to a second embodiment;

[0098] Figure 3 shows a schematic cross-sectional view of a power converter package 300 according to a third embodiment;

[0099] Figure 4 shows a schematic cross-sectional view of a power converter package 400 according to a fourth embodiment;

[0100] Figure 5 shows a schematic cross-sectional view of a power converter package 500 according to a fifth embodiment;

[0101] Figure 6 shows a schematic cross-sectional view of a power converter package 600 according to a sixth embodiment;

[0102] Figure 7a Shown according to Figure 1 FIG. 1 is a schematic cross-sectional view of a power converter package 100 according to a first embodiment;

[0103] Figure 7b Shown according to Figure 1 The schematic top view of the power converter package 100 of the first embodiment is shown;

[0104] Figure 8 shows a schematic top view of a multi-phase system with a common supply voltage region 800 according to another embodiment;

[0105] Fig. 9 Shown by Figure 1 A schematic top view of a multi-phase system 900 implemented with a plurality of power converter packages 100 is shown. DETAILED DESCRIPTION

[0106] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification, wherein specific aspects of the invention which may be practiced are illustrated by way of illustration. It should be understood that other aspects may be utilized, and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the invention is defined by the appended claims.

[0107] It should be understood that comments related to the described method may also apply to the corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not elaborated or illustrated in detail in the figure. In addition, it should be understood that unless otherwise explicitly stated, the features of the various exemplary aspects described herein can be combined with each other.

[0108] In the following figures, different embodiments of power converter packages are shown.

[0109] All embodiments described below provide integrated capacitive EMI shielding against common mode conducted emissions (CMEMI) in the AC voltage region within a power module.

[0110] Embodiment 1, Embodiment 2 and Embodiment 6 describe the shielding achieved by using an additional substrate with minimal area and low requirements for thermal performance. This is achieved by using power semiconductors with lateral current flow. In this case, large-area back contacts with the AC voltage can be eliminated. This makes it easy to define the oscillating conductor areas (AC voltage areas) and make these areas as small as possible. The smaller these areas are, the less shielding is required. In these embodiments, the additional substrate is used only as a connection point for the AC voltage output contacts. This allows the use of cost-effective materials for the substrate because a lot of heat is not generated on the substrate and a lot of heat does not need to be conducted away from the substrate.

[0111] Embodiment 3, Embodiment 4, and Embodiment 5 described below provide solutions for semiconductor devices having lateral current flow, such as GaN semiconductor devices.

[0112] The solution provided by the present invention exploits the higher degree of freedom in terms of back contact provided by semiconductor devices with lateral current flow. The potential of this area can be freely defined so that the entire semiconductor back area does not oscillate and therefore does not require shielding. This is the case for the HS switch in a half-bridge configuration: the HS source potential can usually be connected to the GaN substrate potential on the back of the die. Instead, for better shielding, the HS drain potential is connected to the substrate as described in the present invention.

[0113] By selecting the LS supply voltage at the back side of the LS device and the HS supply voltage at the back side of the HS device, the supply voltage region is extended over the die area, thereby providing shielding for the top surface AC terminals on the die of the lateral current flow semiconductor device.

[0114] Table 1 provides an overview of the embodiments described below. Six embodiments are shown, and the preferred embodiment may be embodiment 1 for lateral devices and embodiment 6 for vertical devices. These embodiments are described in detail below, where the half-bridge topology represents only one example and can be applied to multi-phase multi-level power module topologies with multiple parallel dies or dies and diodes per switch position. Figure 8 and Fig. 9 An example of a multi-phase topology is shown.

[0115] Table 1: Overview of exemplary embodiments provided by the present invention

[0116] Example 1 Example 2 Example 6 Example 3 Example 4 Example 5 HS die direction S Up S Up S Up S Down S Up S Up LS die direction S Up S Up S Down S Down S Up S Down Current flows through the die Horizontal Horizontal Vertical Horizontal Horizontal Horizontal HS die back side potential DC+ DC– DC+ * DC+ DC+ LS die back side potential DC– DC– AC * AC * The presence or absence of die on the additional substrate none none none have have have

[0117] All embodiments have the following common properties:

[0118] 1. The first power semiconductor input terminal is connected to the first supply voltage region;

[0119] 2. The second power semiconductor input terminal is connected to the second supply voltage region;

[0120] 3. The output terminals of the first power semiconductor and the second power semiconductor are connected to the AC voltage output of the component.

[0121] 4. The AC voltage output region is arranged on an additional substrate, the additional substrate comprising a conductor structure on the substrate surface, the conductor structure being connected to output terminals of the first power semiconductor and the second power semiconductor, wherein the substrate is arranged on top of the second supply voltage region.

[0122] In Example 1, the HS and LS dies face up with lateral current flow (see Figure 1 ):

[0123] The first power semiconductor and the second power semiconductor are lateral devices.

[0124] The first supply voltage region extends at least partially below the first power semiconductor, facing the substrate side of the first power semiconductor.

[0125] The second supply voltage region extends at least partially below the second power semiconductor and the AC output of the component, facing the substrate side of the second power semiconductor.

[0126] In Example 2, the HS and LS die face up with lateral current flow, and the HS and LS back faces are on DC- (see Figure 2 ):

[0127] The first power semiconductor and the second power semiconductor are lateral devices.

[0128] The first supply voltage region is located next to the first power semiconductor.

[0129] The second supply voltage region extends at least partially below the first power semiconductor and the second power semiconductor and the AC output of the component, facing the substrate side of the second power semiconductor.

[0130] In Example 3, the HS and LS dies are flip-chip / face-down with lateral current flow, and the backside of the HS and LS are used for heat sink connection (see Figure 3 ):

[0131] The first power semiconductor and the second power semiconductor are lateral devices.

[0132] The first supply voltage region extends briefly before the boundary of the second supply region.

[0133] The second supply voltage region extends at least partially below the first power semiconductor and the second power semiconductor and the AC output of the component, facing the terminals of the power semiconductors.

[0134] In Example 4, the HS and LS dies face up with lateral current flow and there is ≥ 1 die on the additional substrate (see Figure 4 ):

[0135] The first power semiconductor and the second power semiconductor are lateral devices.

[0136] The first supply voltage region extends at least partially below the first power semiconductor, facing the substrate side of the first power semiconductor.

[0137] The second supply voltage region extends at least partially below the second power semiconductor and the AC output of the component, facing the substrate side of the second power semiconductor.

[0138] In Example 5, HS faces up, LS faces down, with lateral current flow, and ≥1 die on the additional substrate (see Figure 5 ):

[0139] The first power semiconductor and the second power semiconductor are lateral devices.

[0140] The first supply voltage region extends at least partially below the first power semiconductor, facing the substrate side of the first power semiconductor.

[0141] The second supply voltage region extends at least partially below the second power semiconductor and the AC output of the component, facing the terminals of the second power semiconductor.

[0142] In Example 6, HS and LS face up, with longitudinal current flow, and ≥1 die on the additional substrate (see Figure 6 ):

[0143] The first power semiconductor and the second power semiconductor are vertical devices.

[0144] The first supply voltage region extends at least partially below the first power semiconductor, facing the input terminal of the first power semiconductor.

[0145] The second supply voltage region extends at least partially below the second power semiconductor and the AC output of the component, facing the input terminal of the second power semiconductor.

[0146] Figure 1 A schematic cross-sectional view of a power converter package 100 according to a first embodiment is shown. The power converter package 100 may be used to convert a first DC voltage and a second DC voltage into a common AC voltage.

[0147] The power converter package 100 includes a first power semiconductor 130 and a second power semiconductor 140 for commoning an AC voltage according to switching between a first DC voltage and a second DC voltage.

[0148] The power converter package 100 includes a first substrate 110 having a first substrate upper main surface 111 and a first substrate lower main surface 112 opposite to the first substrate upper main surface 111. The first substrate 110 includes a first power supply voltage region 113 for providing a first DC voltage and a second power supply voltage region 114 for providing a second DC voltage. The first power supply voltage region 113 and the second power supply voltage region 114 are arranged on the first substrate upper main surface 111.

[0149] The first substrate 110 includes a base metal region 115 arranged on the first substrate lower main surface 112. The base metal region 115 is used to extract dissipated heat from the first power semiconductor 130 and the second power semiconductor 140.

[0150] The first power semiconductor 130 includes a first semiconductor upper main face 131 and a first semiconductor lower main face 132 opposite to the first semiconductor upper main face 131 .

[0151] The first power semiconductor 130 comprises an input terminal 133 and an output terminal 134 . The input terminal 133 of the first power semiconductor 130 is connected 135 to the first supply voltage region 113 .

[0152] The second power semiconductor 140 includes a second semiconductor upper main face 141 and a second semiconductor lower main face 142 opposite the second semiconductor upper main face 141. The second power semiconductor 140 includes an input terminal 143 and an output terminal 144. The input terminal 143 of the second power semiconductor 140 is electrically coupled to the second supply voltage region 114.

[0153] The power converter package 100 includes a second substrate 120 having a second substrate upper main surface 121 and a second substrate lower main surface 122 opposite to the second substrate upper main surface 121. The second substrate 120 includes an AC voltage output region 150 for providing an AC voltage. The AC voltage output region 150 is disposed on top of the second substrate upper main surface 121. The AC voltage output region 150 is electrically coupled to an output terminal 134 of the first power semiconductor 130 and an output terminal 144 of the second power semiconductor 140. The second substrate lower main surface 122 is disposed on top of the second power supply voltage region 114.

[0154] By disposing the second power supply voltage region 114 between the AC voltage output region 150 and the base metal region 115 , the second power supply voltage region 114 is used to isolate and shield the AC voltage output region 150 from the base metal region 115 .

[0155] Due to the shielding effect, it is possible to avoid the formation of a capacitor between the AC output area and the base metal area, which would couple high-frequency noise to the base metal area.

[0156] The second supply voltage region 114 may be arranged at least partially below the second semiconductor lower main face 142 and may extend below the AC voltage output region 150 .

[0157] This overlap of the second supply voltage region and the AC voltage output region may produce a shielding function.

[0158] The basic structure of the power converter package 100 described above for the first embodiment is also implemented in the power converter packages 200 , 300 , 400 , 500 , 600 described below for the second to sixth embodiments.

[0159] exist Figure 1 In the first embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0160] The first power semiconductor 130 and the second power semiconductor 140 may be lateral devices. The input terminal 133 of the first power semiconductor 130 may be arranged on the first semiconductor upper main surface 131 , and the input terminal 143 of the second power semiconductor 140 may be arranged on the second semiconductor upper main surface 141 .

[0161] exist Figure 1 In the first embodiment shown, the first power semiconductor 130 and the second power semiconductor 140 may be mounted face-up on the first substrate 110 . The first semiconductor lower main surface 132 may face the first supply voltage region 113 , and the second semiconductor lower main surface 142 may face the second supply voltage region 114 .

[0162] exist Figure 1 In the illustrated first embodiment, the first supply voltage region 113 may extend at least partially below the first semiconductor lower main surface 132 .

[0163] Figure 2 A schematic cross-sectional view of a power converter package 200 according to a second embodiment is shown.

[0164] The basic structure of the power converter package 100 described above with respect to the first embodiment is also implemented in the power converter package 200 according to the second embodiment.

[0165] exist Figure 2 In the second embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0166] The first power semiconductor 130 and the second power semiconductor 140 may be mounted face-up on the first substrate 110 . The first semiconductor lower main face 132 and the second semiconductor lower main face 142 may face the second supply voltage region 114 .

[0167] The second supply voltage region 114 may extend at least partially under the first semiconductor lower main face 132 , at least partially under the second semiconductor lower main face 142 , and may extend under the AC voltage output region 150 .

[0168] The first supply voltage region 113 may be arranged next to the first power semiconductor 130 .

[0169] Figure 3 A schematic cross-sectional view of a power converter package 300 according to a third embodiment is shown.

[0170] The basic structure of the power converter package 100 described above for the first embodiment is also implemented in the power converter package 300 according to the third embodiment.

[0171] exist Figure 3 In the third embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0172] The first power semiconductor 130 and the second power semiconductor 140 may be mounted on the second substrate 120 by a flip chip method. The first semiconductor upper main surface 131 and the second semiconductor upper main surface 141 may face the first substrate upper main surface 111 .

[0173] The second supply voltage region 114 may extend at least partially under the first semiconductor upper main face 131 , at least partially under the second semiconductor upper main face 141 , and may extend under the AC voltage output region 150 .

[0174] The first supply voltage region 113 may be arranged next to the first power semiconductor 130 .

[0175] Figure 4 A schematic cross-sectional view of a power converter package 400 according to a fourth embodiment is shown.

[0176] The basic structure of the power converter package 100 described above for the first embodiment is also implemented in the power converter package 400 according to the fourth embodiment.

[0177] exist Figure 4 In the fourth embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0178] The first power semiconductor 130 may be mounted face-up on the first substrate 110, and the second power semiconductor 140 may be mounted face-up on the second substrate 120. The first semiconductor lower main surface 132 may face the first supply voltage region 113, and the second substrate lower main surface 122 may face the second supply voltage region 113.

[0179] The first supply voltage region 113 may extend at least partially below the first semiconductor lower main face 132 .

[0180] Figure 5 A schematic cross-sectional view of a power converter package 500 according to a fifth embodiment is shown.

[0181] The basic structure of the power converter package 100 described above for the first embodiment is also implemented in the power converter package 500 according to the fifth embodiment.

[0182] exist Figure 5 In the fifth embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0183] The first power semiconductor 130 may be mounted face-up on the first substrate 110, and the second power semiconductor 140 may be mounted on the second substrate 120 by flip-chip method. The first semiconductor lower main surface 132 may face the first power supply voltage region 113, and the second semiconductor upper main surface 141 may face the second substrate upper main surface 121.

[0184] The second supply voltage region 114 may extend at least partially below the second semiconductor upper main face 141 and the AC voltage output region 150 .

[0185] The first supply voltage region 113 may extend at least partially below the first semiconductor lower main face 132 .

[0186] Figure 6 A schematic cross-sectional view of a power converter package 600 according to a sixth embodiment is shown.

[0187] The basic structure of the power converter package 100 described above for the first embodiment is also implemented in the power converter package 600 according to the sixth embodiment.

[0188] exist Figure 6 In the sixth embodiment shown, in addition to realizing the above basic structure, the following structural features can also be realized:

[0189] The first power semiconductor 130 and the second power semiconductor 140 may be vertical devices. The input terminal 133 and the output terminal 134 of the first power semiconductor 130 may be arranged on the opposite first semiconductor main faces 132, 131. The input terminal 143 and the output terminal 144 of the second power semiconductor 140 may be arranged on the opposite second semiconductor main faces 142, 141.

[0190] The first power semiconductor 130 and the second power semiconductor 140 may be mounted face-up on the first substrate 110 . The first semiconductor lower main face 132 may face the first supply voltage region 113 , and the second semiconductor lower main face 142 may face the second supply voltage region 114 .

[0191] The second supply voltage region 114 may extend at least partially below the second semiconductor lower main face 142 and may extend at least partially below the second substrate lower main face 122 .

[0192] The first supply voltage region 113 may extend at least partially below the first semiconductor lower main face 132 .

[0193] Figure 7a Shown according to Figure 1 FIG. 1 is a schematic cross-sectional view of a power converter package 100 according to a first embodiment of the present invention. Figure 7b Shown according to Figure 1 FIG. 1 is a schematic top view of a power converter package 100 according to a first embodiment.

[0194] In the exemplary power converter package 100 , a first power semiconductor 130 and a second power semiconductor 140 are implemented to realize a single-phase module.

[0195] As above combined Figure 1 As described, the HS and LS dies face upward and enable lateral current flow. The first power semiconductor 130 and the second power semiconductor 140 can be lateral devices. The first supply voltage region extends at least partially under the first power semiconductor, facing the substrate side of the first power semiconductor. The second supply voltage region extends at least partially under the second power semiconductor and the AC output terminal of the component, facing the substrate side of the second power semiconductor.

[0196] All other embodiments 200, 300, 400, 500, 600 described above may be implemented similarly.

[0197] Figure 8 A schematic top view of a multi-phase system with a common supply voltage range 800 according to another exemplary embodiment is shown.

[0198] The multi-phase system with a common supply voltage region 800 may correspond to the above combined Figures 1 to 6 Any of the power converter packages 100 , 200 , 300 , 400 , 500 , 600 described herein, wherein an exemplary number of three first power semiconductors 130 and an exemplary number of three second power semiconductors 140 are implemented.

[0199] AC voltage consists of multiple phases, such as Figure 8 An exemplary number of three phases are shown.

[0200] The AC voltage output region 150 formed on the second substrate 120 includes a plurality of isolated phase sections, each phase section being associated with a corresponding phase of the AC voltage. The first AC contact 801 may be disposed on the first phase section of the AC voltage output region 150. The second AC contact 802 may be disposed on the second phase section of the AC voltage output region 150. The third AC contact 803 may be disposed on the third phase section of the AC voltage output region 150.

[0201] The AC voltage output region 150 formed on the second substrate 120 includes a plurality of isolated phase sections, each phase section being associated with a corresponding phase of the AC voltage. The first AC contact 801 may be disposed on the first phase section of the AC voltage output region 150. The second AC contact 802 may be disposed on the second phase section of the AC voltage output region 150. The third AC contact 803 may be disposed on the third phase section of the AC voltage output region 150.

[0202] exist Figure 8 In another implementation not shown in FIG. Fig. 9 The illustrated multi-phase system 900 may be implemented in a single power converter package.

[0203] In such a single power converter package, the first substrate 110 includes a plurality of first supply voltage regions 113, each of which is associated with a corresponding phase of the AC voltage, wherein the first supply voltage regions 113 are electrically connected to each other via electrical connectors 911, 912, as shown in FIG. Fig. 9 Each first power supply voltage region 113 may be arranged on a corresponding portion 110a, 110b, 110c of the first substrate 110, as shown in FIG. Fig. 9 As shown in the example.

[0204] Similarly, the second substrate 120 includes a plurality of second supply voltage regions 114, each second supply voltage region 114 being associated with a corresponding phase of the AC voltage, wherein the second supply voltage regions 114 are electrically connected to each other via electrical connectors 913, 914, as shown in FIG. Fig. 9 Each second power supply voltage region 114 may be arranged on a corresponding portion 110a, 110b, 110c of the first substrate 110, as shown in FIG. Fig. 9 As shown in the example.

[0205] The first substrate 110 may include a plurality of base metal regions 115 ( Figure 8 (not shown), each base metal region 115 is associated with a corresponding phase of the AC voltage, wherein the base metal regions 115 form a common base metal region. Since the base metal regions 115 are arranged on the bottom surface, Fig. 9 The base metal region 115 is not visible in the top view of FIG.

[0206] In such a multi-phase module in one package, the first substrate 110 and the second substrate 120 can be shared between multiple phases. This means that the first supply voltage areas of all phases are fused together, the second supply voltage areas of all phases are fused together, and the base metal areas 115 of all phases are fused to a common base metal area. The second substrate of each module can be mechanically connected. The second substrate can have a lower main surface electrical conductor area that is connected or not connected between multiple phases. The term "fused" in a broad sense can only mean "electrically connected to each other (not mechanically connected)". Therefore, there can be multiple independent modules that function similarly to a three-phase system, such as Fig. 9 shown.

[0207] Fig. 9 Shown by Figure 1 A schematic top view of a multi-phase system 900 implemented with a plurality of power converter packages 100 is shown.

[0208] The multiphase system 900 includes the above-mentioned Figures 1 to 8 The multiple power converter packages 100 , 200 , 300 , 400 , 500 , 600 .

[0209] The first supply voltage regions 113 of the first substrates 110 of the plurality of power converter packages 100 , 200 , 300 , 400 , 500 , 600 are electrically connected to each other through electrical connectors 911 , 912 to form a common first supply voltage region for all phases of the multi-phase system.

[0210] The second supply voltage regions 114 of the first substrates 110 of the plurality of power converter packages 100 , 200 , 300 , 400 , 500 , 600 are electrically connected to each other through electrical connectors 913 , 914 to form a common second supply voltage region for all phases of the multi-phase system.

[0211] The present invention also provides a method for shielding a power converter package (e.g., the power converter package 100, 200, 300, 400, 500, 600 according to any of the above embodiments) to prevent common-mode conducted emissions. The method comprises: disposing a second power supply voltage region 114 between an AC voltage output region 150 and a base metal region 115, Figures 1 to 6 The second supply voltage region of the power converter package 100 , 200 , 300 , 400 , 500 , 600 isolates and shields the AC voltage output region 150 from the base metal region 115 .

[0212] Although specific features or aspects of the present invention may have been disclosed with respect to only one of several implementations, such features or aspects may be advantageously combined with one or more other features or aspects of other implementations as desired and for any given or specific application. In addition, to a certain extent, the terms "include", "have", "have" or other variations of these words are used in the detailed description or claims, and such terms are similar to the term "include" and are both expressions of the meaning of inclusion. Similarly, the terms "exemplary" and "for example" are only represented as examples, rather than the best or optimal. The terms "coupled" and "connected" and derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or they are not in direct contact with each other.

[0213] Although specific aspects have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be used to replace the specific aspects shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or changes to the specific aspects discussed herein.

[0214] Although elements in the following claims are listed in a specific order with corresponding labels, these elements are not necessarily limited to being implemented in this specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0215] According to the above guidance, many substitutions, modifications and changes are obvious to those skilled in the art. Of course, it is easy for those skilled in the art to recognize that, in addition to the applications described herein, there are many other applications of the present invention. Although the present invention has been described with reference to one or more specific embodiments, it is recognized by those skilled in the art that many changes may be made to it without departing from the scope of the present invention. Therefore, it should be understood that, as long as it is within the scope of the appended claims and their equivalents, the present invention may be practiced in a manner different from that specifically described herein.

Claims

1. A power converter package (100, 200, 300, 400, 500, 600) for converting a first DC voltage and a second DC voltage into a common AC voltage, characterized in that: The power converter package (100, 200, 300, 400, 500, 600) comprises: A first power semiconductor (130) and a second power semiconductor (140), the first power semiconductor (130) and the second power semiconductor (140) being used to generate the common AC voltage according to switching between the first DC voltage and the second DC voltage; A first substrate (110), wherein the first substrate (110) has a first substrate upper main surface (111) and a first substrate lower main surface (112) opposite to the first substrate upper main surface (111), the first substrate (110) comprises a first power supply voltage region (113) for providing the first DC voltage and a second power supply voltage region (114) for providing the second DC voltage, the first power supply voltage region (113) and the second power supply voltage region (114) being arranged on the first substrate upper main surface (111), The first substrate (110) comprises a base metal region (115) arranged on a lower main surface (112) of the first substrate, wherein the base metal region (115) is used to extract dissipated heat from the first power semiconductor (130) and the second power semiconductor (140), The first power semiconductor (130) has a first semiconductor upper main surface (131) and a first semiconductor lower main surface (132) opposite to the first semiconductor upper main surface (131), the first power semiconductor (130) comprises an input terminal (133) and an output terminal (134), wherein the input terminal (133) of the first power semiconductor (130) is connected (135) to the first supply voltage region (113), The second power semiconductor (140) has a second semiconductor upper main surface (141) and a second semiconductor lower main surface (142) opposite to the second semiconductor upper main surface (141), the second power semiconductor (140) comprises an input terminal (143) and an output terminal (144), wherein the input terminal (143) of the second power semiconductor (140) is electrically coupled to the second supply voltage region (114); a second substrate (120), the second substrate (120) having a second substrate upper main surface (121) and a second substrate lower main surface (122) opposite to the second substrate upper main surface (121), the second substrate (120) comprising an AC voltage output region (150) for providing the AC voltage, the AC voltage output region (150) being arranged on top of the second substrate upper main surface (121), wherein the AC voltage output region (150) is electrically coupled to the output terminal (134) of the first power semiconductor (130) and the output terminal (144) of the second power semiconductor (140), wherein the second substrate lower main surface (122) is arranged on top of the second power supply voltage region (114), Wherein, by arranging the second power supply voltage region (114) between the AC voltage output region (150) and the base metal region (115), the second power supply voltage region (114) is used to isolate and shield the AC voltage output region (150) from the base metal region (115).

2. The power converter package (100) according to claim 1, characterized in that: The second supply voltage region (114) is arranged at least partially below the second semiconductor lower main surface (142) and extends below the AC voltage output region (150).

3. The power converter package (100) according to claim 1 or 2, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are lateral devices, the input terminal (133) of the first power semiconductor (130) is arranged on the first semiconductor upper main surface (131), and the input terminal (143) of the second power semiconductor (140) is arranged on the second semiconductor upper main surface (141).

4. The power converter package (100) according to any one of the preceding claims, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are mounted face up on the first substrate (110), the first semiconductor lower main surface (132) faces the first power supply voltage region (113), and the second semiconductor lower main surface (142) faces the second power supply voltage region (114).

5. The power converter package (100) according to any one of the preceding claims, characterized in that: The first supply voltage region (113) extends at least partially below the first semiconductor lower main surface (132).

6. The power converter package (200) according to any one of claims 1 to 3 or claim 6, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are mounted face-up on the first substrate (110), and the first semiconductor lower main surface (132) and the second semiconductor lower main surface (142) face the second power supply voltage region (114).

7. The power converter package (200) according to claim 6, characterized in that: The second supply voltage region (114) extends at least partially below the first semiconductor lower main surface (132), at least partially below the second semiconductor lower main surface (142), and below the AC voltage output region (150).

8. The power converter package (200) according to claim 6 or 7, characterized in that: The first supply voltage region (113) is arranged next to the first power semiconductor (130).

9. The power converter package (300) according to any one of claims 1 to 3, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are mounted on the second substrate (120) by flip chip method, and the first semiconductor upper main surface (131) and the second semiconductor upper main surface (141) face the first substrate upper main surface (111).

10. The power converter package (300) according to claim 9, characterized in that: The second supply voltage region (114) extends at least partially below the first semiconductor upper main surface (131), at least partially below the second semiconductor upper main surface (141), and below the AC voltage output region (150).

11. The power converter package (300) according to claim 9 or 10, characterized in that: The first supply voltage region (113) is arranged next to the first power semiconductor (130).

12. The power converter package (400) according to any one of claims 1 to 3, characterized in that: The first power semiconductor (130) is mounted face-up on the first substrate (110), the second power semiconductor (140) is mounted face-up on the second substrate (120), the first semiconductor lower main surface (132) faces the first power supply voltage region (113), and the second substrate lower main surface (122) faces the second power supply voltage region (113).

13. The power converter package (400) according to any one of claims 1 to 3 or claim 12, characterized in that: The first supply voltage region (113) extends at least partially below the first semiconductor lower main surface (132).

14. The power converter package (500) according to any one of claims 1 to 3, characterized in that: The first power semiconductor (130) is mounted face-up on the first substrate (110), the second power semiconductor (140) is mounted on the second substrate (120) by flip-chip method, the lower main surface (132) of the first semiconductor faces the first power supply voltage region (113), and the upper main surface (141) of the second semiconductor faces the upper main surface (121) of the second substrate.

15. The power converter package (500) according to claim 14, characterized in that: The second supply voltage region (114) extends at least partially below the second semiconductor upper main surface (141) and the AC voltage output region (150).

16. The power converter package (500) according to claim 14 or 15, characterized in that: The first supply voltage region (113) extends at least partially below the first semiconductor lower main surface (132).

17. The power converter package (600) according to claim 1 or 2, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are vertical devices; the input terminal (133) and the output terminal (134) of the first power semiconductor (130) are arranged on opposite first semiconductor main surfaces (132, 131); the input terminal (143) and the output terminal (144) of the second power semiconductor (140) are arranged on opposite second semiconductor main surfaces (142, 141).

18. The power converter package (600) according to any one of claims 1 and 2 or claim 17, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are mounted face up on the first substrate (110), the first semiconductor lower main surface (132) faces the first power supply voltage region (113), and the second semiconductor lower main surface (142) faces the second power supply voltage region (114).

19. The power converter package (600) according to claim 18, characterized in that: The first supply voltage region (113) extends at least partially below the first semiconductor lower main surface (132).

20. The power converter package (100, 200, 300, 400, 500, 600) according to any one of the preceding claims, characterized in that: The first power semiconductor (130) and the second power semiconductor (140) are electrically connected to a half-bridge topology.

21. The power converter package (100, 200, 300, 400, 500, 600) according to any one of the preceding claims, characterized in that: The AC voltage includes a plurality of phases; The AC voltage output region (150) formed on the second substrate (120) includes a plurality of isolated phase segments, each phase segment being associated with a corresponding phase of the AC voltage; The first substrate (110) comprises a plurality of first supply voltage regions (113), each first supply voltage region (113) being associated with a corresponding phase of the AC voltage, wherein the first supply voltage regions (113) are electrically connected to each other; The second substrate (120) comprises a plurality of second supply voltage regions (114), each second supply voltage region (114) being associated with a respective phase of the AC voltage, wherein the second supply voltage regions (114) are electrically connected to each other; The first substrate (110) includes a plurality of base metal regions (115), each base metal region (115) being associated with a respective phase of the AC voltage, wherein the base metal regions (115) form a common base metal region.

22. A multiphase system, characterized in that: include: The plurality of power converter packages (100, 200, 300, 400, 500, 600) according to claim 20, wherein the first supply voltage regions (113) of the first substrates (110) of the plurality of power converter packages (100, 200, 300, 400, 500, 600) are electrically connected to each other to form a common first supply voltage region for all phases of the multi-phase system; The second power supply voltage regions (114) of the first substrates (110) of the plurality of power converter packages (100, 200, 300, 400, 500, 600) are electrically connected to each other to form a common second power supply voltage region for all phases of the multi-phase system.

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