Watchdog control device and vehicle

Abstract

The invention discloses a watchdog control device and a vehicle. The watchdog control device comprises a control unit, a watchdog unit and a signal providing unit. A dog feeding signal input end of the watchdog unit is connected with a dog feeding signal output end of the control unit, a reset signal output end of the watchdog unit is connected with a reset signal input end of the control unit, and the signal providing unit is connected with a state control end of the control unit and an enabling end of the watchdog unit. A state control signal output by the signal providing unit is used for controlling the working state of the control unit and enabling of the watchdog unit, so that the watchdog unit is in an enabled state when the control unit is in a normal working state, and the watchdog unit is in a non-enabled state when the control unit is in a dormant state. In this way, the reliability of the reset function of the watchdog unit can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a watchdog control device and a vehicle. Background Art

[0002] The watchdog unit is essentially a timer circuit, which is mainly used to regularly monitor the operation of the control unit to prevent the control unit from freezing. When the control unit is operating normally, it is necessary to feed the watchdog unit correctly at regular intervals. If the control unit fails to feed the watchdog unit correctly within the specified time, the timing of the watchdog unit will time out. At this time, the watchdog unit will output a reset signal to the control unit to reset the control unit. Therefore, ensuring the reliability of the reset function of the watchdog unit is conducive to the normal operation of the system. Summary of the invention

[0003] The main technical problem solved by the present application is to provide a watchdog control device and a vehicle, which can improve the reliability of the reset function of the watchdog unit.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a watchdog control device, including: a control unit; a watchdog unit, the dog feeding signal input terminal of the watchdog unit is connected to the dog feeding signal output terminal of the control unit, and the reset signal output terminal of the watchdog unit is connected to the reset signal input terminal of the control unit; a signal providing unit, the signal providing unit is connected to the state control terminal of the control unit and the enable terminal of the watchdog unit, and the state control signal output by the signal providing unit is used to control the working state of the control unit and the enablement of the watchdog unit, so that the watchdog unit is in an enabled state when the control unit is in a normal working state, and the watchdog unit is in a disabled state when the control unit is in a sleep state.

[0005] Optionally, the state control signal includes at least one of a sleep control signal and a wake-up signal.

[0006] Optionally, the state control signal includes a sleep control signal and a wake-up signal, and the signal providing unit includes a first signal providing subunit and a second signal providing subunit, the first signal providing subunit is used to output the sleep control signal, and the second signal providing subunit is used to output the wake-up signal; the watchdog control device also includes a conversion unit and a first logic gate; the output end of the first signal providing subunit is connected to the sleep control end of the control unit and the first input end of the first logic gate, the output end of the second signal providing subunit is connected to the wake-up end of the control unit, and the output end of the second providing subunit is also connected to the second input end of the first logic gate through the conversion unit, and the output end of the first logic gate is connected to the enable end of the watchdog unit. Among them, when the sleep control signal is used to configure the control unit to a normal working state, the conversion unit is configured to output a first level signal, the first logic gate outputs a first target level signal, and the watchdog unit is configured to be in an enabled state; when the sleep control signal is used to configure the control unit to a sleep state and the wake-up signal is not a preset pulse, the conversion unit is configured to output a first level signal, the first logic gate outputs a second target level signal, and the watchdog unit is configured to be in a disabled state; when the sleep control signal is used to configure the control unit to a sleep state and the wake-up signal is a preset pulse, the conversion unit is configured to output a second level signal, the first logic gate outputs a first target level signal, and the watchdog unit is configured to be in an enabled state; the level states of the first level signal and the second level signal are opposite, the first target level signal is one of the first level signal and the second level signal, and the second target level signal is the other of the first level signal and the second level signal.

[0007] Optionally, the conversion unit includes a first conversion circuit, a second conversion circuit and a D flip-flop; the first input end of the first conversion circuit is used to receive a first signal, the second input end of the first conversion circuit is connected to the first control signal output end of the control unit, the output end of the first conversion circuit is connected to the data input end of the D flip-flop, the first input end of the second conversion circuit is connected to the output end of the second signal providing subunit, the second input end of the second conversion circuit is used to receive a second signal, the third input end of the second conversion circuit is connected to the second control signal output end of the control unit, the output end of the second conversion circuit is connected to the clock input end of the D flip-flop, and the output end of the D flip-flop is connected to the second input end of the first logic gate.

[0008] Optionally, the first input terminal of the first conversion circuit and the third input terminal of the second conversion circuit are both connected to the output terminal of the first signal providing subunit, and the first signal and the second signal are both sleep control signals.

[0009] Optionally, the first conversion circuit includes a first level flip sub-circuit and a second logic gate; the input end of the first level flip sub-circuit is used to receive the first signal, the output end of the first level flip sub-circuit is connected to the first input end of the second logic gate, the second input end of the second logic gate is connected to the first control signal output end of the control unit, and the output end of the second logic gate is connected to the data input end of the D flip-flop.

[0010] Optionally, the second conversion circuit includes a third logic gate, a fourth logic gate and a second level flip sub-circuit; the first input end of the third logic gate is connected to the output end of the second signal providing sub-unit, the input end of the second level flip sub-circuit is used to receive the second signal, the output end of the second level flip sub-circuit is connected to the first input end of the fourth logic gate, the second input end of the fourth logic gate is connected to the second control signal output end of the control unit, the output end of the fourth logic gate is connected to the second input end of the third logic gate, and the output end of the third logic gate is connected to the clock input end of the D flip-flop.

[0011] Optionally, the watchdog control device also includes a fifth logic gate; the first input end of the fifth logic gate is connected to the third control signal output end of the control unit, the second input end of the fifth logic gate is connected to the output end of the first logic gate, and the output end of the fifth logic gate is connected to the enable end of the watchdog unit.

[0012] Optionally, the watchdog control device also includes a level flipping circuit, which is connected between the output end of the first signal providing subunit and the sleep control end of the control unit; and / or, the watchdog control device also includes a first buffer circuit and a second buffer circuit, the first buffer circuit is connected between the output end of the first signal providing subunit and the first input end of the first logic gate, and the second buffer circuit is connected between the output end of the second signal providing subunit and the wake-up end of the control unit.

[0013] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a vehicle, which includes any of the watchdog control devices described above.

[0014] In the above scheme, the signal providing unit is connected to the state control end of the control unit and the enable end of the watchdog unit, and the state control signal output by the signal providing unit is used to simultaneously control the working state of the control unit and the enablement of the watchdog unit, so that the watchdog unit is in an enabled state when the control unit is in a normal working state, and the watchdog unit is in a disabled state when the control unit is in a dormant state. That is, the enablement of the watchdog unit is not controlled by the control unit, but by the state control signal output by the signal providing unit. In this way, on the one hand, the enablement state of the watchdog unit and the working state of the control unit can be synchronized; on the other hand, regardless of whether the control unit is hung or not, it can be ensured that the watchdog unit can reset the control unit, thereby improving the reliability of the reset function of the watchdog unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of an embodiment of a watchdog control device provided by the present application;

[0016] Figure 2 is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application;

[0017] Figure 3 It is a structural schematic diagram of the level flipping circuit provided by the present application;

[0018] Figure 4 It is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application;

[0019] Figure 5 It is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application;

[0020] Figure 6 It is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application;

[0021] Figure 7 It is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application;

[0022] Figure 8 This is a working timing diagram of the watchdog control device provided in this application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0024] It should be noted that the term "and / or" in this document is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the terms "first", "second", etc. in the specification and claims of this document and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] Taking the vehicle scenario as an example, the vehicle control system includes several control units. Since the vehicle control system needs to consider low-power design, each control unit usually has a normal working state and a sleep state. It can be understood that when the watchdog unit is in an enabled state, the watchdog unit can reset the control unit; when the watchdog unit is in a disabled state, the watchdog unit cannot reset the control unit. When the control unit is in a normal working state, the watchdog unit needs to be enabled so that the watchdog unit can reset the control unit; when the control unit enters a sleep state, the enable of the watchdog unit needs to be turned off, otherwise, the control unit will be reset because the control unit does not send a feeding signal to the watchdog unit. At the same time, turning off the enable of the watchdog unit can also reduce system power consumption. Therefore, when the control unit is in different working states, it is necessary to control the watchdog unit to be in the corresponding working state.

[0026] In the related art, the enabling of the watchdog unit is controlled by the control unit. In this method, the control unit and the watchdog unit control each other. On the one hand, the control unit can control the enabling of the watchdog unit. Specifically, when the control unit is in a normal working state, the watchdog unit is controlled to be in an enabled state, and the control unit can control the watchdog unit to be in a disabled state before entering a dormant state; on the other hand, when the watchdog unit is in an enabled state, if the watchdog unit times out and does not receive the dog feeding signal sent by the control unit, the watchdog unit can also reset the control unit.

[0027] However, if the control unit is hung up, the level of the pin used by the control unit to output the enable signal to the watchdog unit will not be controlled. At this time, the enable control of the watchdog unit may be abnormal, resulting in an abnormal reset function of the watchdog unit. For example, when the control unit is hung up during normal operation, the control unit cannot enable the watchdog unit, resulting in the watchdog unit being unable to reset the control unit. For another example, when the control unit is hung up during sleep, since the watchdog unit is not enabled, the watchdog unit cannot reset the control unit, resulting in the control unit being unable to be awakened by the wake-up signal.

[0028] In view of this, the present application provides a watchdog control device to improve the reliability of the reset function of the watchdog unit.

[0029] See also Figure 1 , Figure 1 1 is a flow chart of an embodiment of a watchdog control device provided by the present application. Figure 1 As shown, the watchdog control device includes a control unit 10, a watchdog unit 20 and a signal providing unit 30. The dog feeding signal input terminal of the watchdog unit 20 is connected to the dog feeding signal output terminal of the control unit 10, the reset signal output terminal of the watchdog unit 20 is connected to the reset signal input terminal of the control unit 10, and the signal providing unit 30 is connected to the state control terminal of the control unit 10 and the enable terminal of the watchdog unit 20.

[0030] The state control signal output by the signal providing unit 30 is used to control the working state of the control unit 10 and the enabling of the watchdog unit 20, so that the watchdog unit 20 is enabled when the control unit 10 is in a normal working state, and the watchdog unit 20 is not enabled when the control unit 10 is in a dormant state. Exemplarily, the control unit 10 is an MCU (Microcontroller Unit, micro control unit 10), and the watchdog unit 20 is an external watchdog.

[0031] The signal providing unit 30 can output a sleep control signal and a wake-up signal. Specifically, the signal providing unit 30 includes a first signal providing subunit and a second signal providing subunit ( Figure 1 The first signal providing subunit and the second signal providing subunit are not shown in the figure. The first signal providing subunit is used to output a sleep control signal, and the second signal providing subunit is used to output a wake-up signal.

[0032] Exemplarily, the sleep control signal is a level signal, and the wake-up signal is a pulse signal.

[0033] Exemplarily, the first signal providing subunit is an upper level controller of the control unit 10, such as a central controller of the vehicle. The first signal providing subunit can directly output a sleep control signal. Alternatively, the first signal providing subunit can control whether the power supply is connected through a switch to indirectly output a sleep control signal. For example, the power supply is a 12V ON1 in the vehicle, or the power supply can also be a 3.3V power supply, a 5V power supply, etc. adapted to the control unit, which is not specifically limited in this embodiment.

[0034] Exemplarily, the second signal providing subunit is a wireless module of the control unit 10 , and the wireless module can output a wake-up signal.

[0035] The state control signal includes at least one of a sleep control signal and a wake-up signal. That is, in addition to being used to configure the working state of the control unit 10, at least one of the sleep control signal and the wake-up signal is also used to configure the enablement of the watchdog unit 20. For example, only the sleep control signal can be used to configure the enablement of the watchdog unit 20, or only the wake-up signal can be used to configure the enablement of the watchdog unit 20, or both the sleep control signal and the wake-up signal can be used to configure the enablement of the watchdog unit 20, which is not specifically limited in this embodiment.

[0036] In one embodiment, the sleep control signal is used to configure the control unit 10 to be in a normal working state or a sleep state, and is also used to configure the enablement of the watchdog unit 20 to be in a corresponding state. When the sleep control signal is used to configure the control unit 10 to be in a normal working state, the watchdog unit 20 is configured to be in an enabled state; when the sleep control signal is used to configure the control unit 10 to be in a sleep state, the watchdog unit 20 is configured to be in a disabled state.

[0037] In this embodiment, if the control unit 10 hangs during normal operation, since the enabling of the watchdog unit 20 is controlled by the sleep control signal, the watchdog unit 20 is always in the enabled state during the normal operation of the control unit 10, so the watchdog unit 20 can reset the hung control unit 10.

[0038] In another embodiment, the wake-up signal is used to not wake up the control unit 10 in the dormant state or to wake up the control unit 10 in the dormant state, and is also used to configure the enablement of the watchdog unit 20 to be in a corresponding state. When the wake-up signal is used to not wake up the control unit 10 in the dormant state, the control unit 10 is still in the dormant state, and the watchdog unit 20 is configured to be in a disabled state; when the wake-up signal is used to wake up the control unit 10 in the dormant state, if the control unit 10 is not hung during the dormant period, the control unit 10 is in a normal working state after being awakened by the wake-up signal, and the watchdog unit 20 is configured to be in an enabled state.

[0039] In this embodiment, if the control unit 10 hangs during sleep, since the enabling of the watchdog unit 20 is controlled by the wake-up signal, the watchdog unit 20 can be configured to an enabled state by the wake-up signal. The enabled watchdog unit 20 can reset the hung control unit 10, and the control unit 10 can be in a normal working state after being reset by the watchdog unit 20.

[0040] It should be noted that when the wake-up signal output by the signal providing unit 30 is a pulse signal, considering that the pulse duration is short, the watchdog unit 20 may not be able to complete the reset of the control unit 10 during this short period of time. Therefore, it is also necessary to use the conversion unit ( Figure 1(not shown) the wake-up signal in the form of a pulse output by the signal providing unit 30 is converted into a level signal and then input to the enable terminal of the watchdog unit 20.

[0041] In this embodiment, the signal providing unit is connected to the state control end of the control unit and the enable end of the watchdog unit, and the state control signal output by the signal providing unit is used to simultaneously control the working state of the control unit and the enablement of the watchdog unit, so that the watchdog unit is in an enabled state when the control unit is in a normal working state, and the watchdog unit is in a disabled state when the control unit is in a dormant state. That is, the enablement of the watchdog unit is not controlled by the control unit, but by the state control signal output by the signal providing unit. In this way, on the one hand, the enablement state of the watchdog unit and the working state of the control unit can be synchronized; on the other hand, regardless of whether the control unit is hung or not, it can be ensured that the watchdog unit can reset the control unit, thereby improving the reliability of the reset function of the watchdog unit.

[0042] In one embodiment, the sleep control signal is only used to configure the enablement of the watchdog unit to solve the problem that the control unit is hung during normal operation, resulting in the watchdog unit being unable to reset the control unit.

[0043] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of the structure of another embodiment of the watchdog control device provided by the present application. Figure 2 As shown, the state control end of the control unit 10 includes a sleep control end and a wake-up end, the output end of the first signal providing subunit 31 is connected to the sleep control end of the control unit 10 and the enable end of the watchdog unit 20, and the output end of the second signal providing subunit 32 is only connected to the wake-up end of the control unit 10. The first signal providing subunit 31 outputs a sleep control signal, and the second signal providing subunit 32 outputs a wake-up signal. Exemplarily, when the wake-up signal is not a preset pulse, the level state of the wake-up signal is a high level, and when the wake-up signal is a preset pulse, the level state of the wake-up signal is a low level.

[0044] In one embodiment, the sleep state of the control unit 10 is high-level effective and the enable state of the watchdog unit 20 is high-level effective; or, the sleep state of the control unit 10 is low-level effective and the enable end of the watchdog unit 20 is low-level effective. At this time, if the sleep control signal is directly input into the sleep control end of the control unit 10 and the enable end of the watchdog unit 20, the state of the watchdog unit 20 will be out of sync with the working state of the control unit 10. Take the sleep state of the control unit 10 as high-level effective and the enable state of the watchdog unit 20 as high-level effective as an example: when the sleep control signal is a low-level signal, the control unit 10 will be configured as a normal working state, and the watchdog unit 20 will be configured as a non-enabled state; when the sleep control signal is a high-level signal, the control unit 10 will be configured as a sleep state, and the watchdog unit 20 will be configured as an enabled state, and the state of the watchdog unit 20 will be out of sync with the working state of the control unit 10.

[0045] Therefore, in order to ensure that the state of the watchdog unit 20 is synchronized with the working state of the control unit 10, Figure 2 The watchdog control device in the embodiment further includes a level flipping circuit 41 connected between the output end of the first signal providing subunit 31 and the sleep control end of the control unit 10, and the level flipping circuit 41 is used to flip the level of the sleep control signal output by the first signal providing subunit 31 and then input it to the sleep control end of the control unit 10. Optionally, the level flipping circuit 41 can also be connected between the output end of the first signal providing subunit 31 and the enable end of the watchdog unit 20, and is used to flip the level of the sleep control signal output by the first signal providing subunit 31 and then input it to the enable end of the watchdog unit 20.

[0046] Figure 3 1 is a schematic diagram of the structure of an embodiment of a level flip circuit provided by the present application. Figure 3As shown, the level flip circuit 41 includes a transistor 411, a first resistor 412, a second resistor 413, a third resistor 414, a fourth resistor 415 and a fifth resistor 416. The transistor 411 is an npn-type transistor, the base of the transistor 411 is connected to the first end of the first resistor 412 and the first end of the second resistor 413, the second end of the first resistor 412 and the emitter of the transistor 411 are grounded, the second end of the second resistor 413 is connected to the first end of the third resistor 414, the second end of the second resistor 413 is also used to connect to the output end of the first signal providing subunit 31, the second end of the third resistor 414 is grounded, the collector of the transistor 411 is connected to the first end of the fourth resistor 415 and the first end of the fifth resistor 416, the second end of the fourth resistor 415 is connected to the power supply VCC, and the second end of the fifth resistor 416 is connected to the sleep control end of the control unit 10. The second end of the second resistor 413 is specifically the input end of the level flip circuit 41, and the second end of the fifth resistor 416 is specifically the output end of the level flip circuit 41. The voltage of the power supply VCC is adapted to the voltage required by the control unit 10. Exemplarily, the voltage of the power supply VCC is 5V, 3.3V, etc. The specific resistance values ​​of the first resistor 412, the second resistor 413, the third resistor 414, the fourth resistor 415 and the fifth resistor 416 can be set according to actual needs.

[0047] When the sleep control signal output by the first signal providing subunit 31 is at a high level, the transistor 411 is in a conducting state, and the level flipping circuit 41 outputs a low level. When the sleep control signal output by the first signal providing subunit 31 is at a low level, the transistor 411 is in a shut-off state, and the level flipping circuit 41 outputs a high level.

[0048] Exemplarily, when the sleep control signal is 12V, the level flip circuit 41 outputs 0V, and when the sleep control signal is 0V, the level flip circuit 41 outputs a voltage approximately equal to the power supply VCC. The level flip circuit 41 can play the role of level flipping, and can also avoid damage to the control unit 10 due to excessively high voltage of the input signal.

[0049] In another embodiment, the sleep state of the control unit 10 is low level effective and the enable state of the watchdog unit 20 is high level effective; or, the sleep state of the control unit 10 is high level effective and the enable state of the watchdog unit 20 is low level effective. In this case, if the sleep control signal is directly input to the sleep control terminal of the control unit 10 and the enable terminal of the watchdog unit 20, the state of the watchdog unit 20 is synchronized with the working state of the control unit 10. Therefore, the level flip circuit 41 may not be provided in this embodiment.

[0050] In this embodiment, if the control unit hangs during normal operation, since the enabling of the watchdog unit is controlled by the sleep control signal, the watchdog unit is always in the enabled state during the normal operation of the control unit. Therefore, the watchdog unit can reset the hung control unit, thereby improving the reliability of the reset function of the watchdog unit.

[0051] In another embodiment, the wake-up signal is only used to configure the enablement of the watchdog unit 20 to solve the problem that the control unit 10 is hung during the sleep period, resulting in the watchdog unit 20 being unable to reset the control unit 10 .

[0052] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram of the structure of another embodiment of the watchdog control device provided by the present application. Figure 2 Compared with the watchdog control device shown, Figure 4 The watchdog control device shown further includes a conversion unit 50. And, Figure 4 In the embodiment, the output end of the first signal providing subunit 31 is only connected to the sleep control end of the control unit 10, the output end of the second signal providing subunit 32 is connected to the wake-up end of the control unit 10, and the output end of the second signal providing subunit 32 is also connected to the enable end of the watchdog unit 20 through the conversion unit 50.

[0053] Since the wake-up signal output by the second signal providing subunit 32 is a pulse signal with a short pulse duration, in order to ensure that the watchdog unit 20 has enough time to complete the reset of the control unit 10 after being enabled, the wake-up signal output by the second signal providing subunit 32 is converted into a level signal by the conversion unit 50 and then input into the enable end of the watchdog unit 20. The relevant content of the conversion unit 50 can be found in the following text. Figure 6 or Figure 7 The detailed description of the embodiment shown is omitted here.

[0054] In one embodiment, the watchdog unit 20 is enabled at a high level. During the sleep period of the control unit 10, if the wake-up signal is not a preset pulse, that is, the wake-up signal is not used to wake up the control unit 10, the conversion unit 50 is configured to output a first level signal with a low level state, and the watchdog is configured to be disabled; if the wake-up signal is a preset pulse, that is, the wake-up signal is used to wake up the control unit 10, the conversion unit 50 is configured to output a second level signal with a high level state, and the watchdog is configured to be enabled.

[0055] In another embodiment, the watchdog unit 20 is enabled at a low level. During the sleep period of the control unit 10, if the wake-up signal is not a preset pulse, that is, the wake-up signal is not used to wake up the control unit 10, the conversion unit 50 is configured to output a first level signal with a high level state, and the watchdog is configured to be disabled; if the wake-up signal is a preset pulse, that is, the wake-up signal is used to wake up the control unit 10, the conversion unit 50 is configured to output a second level signal with a low level state, and the watchdog is configured to be enabled.

[0056] Optionally, in this embodiment, in order to ensure that the state of the watchdog unit 20 is synchronized with the working state of the control unit 10, a level flip circuit 41 ( Figure 4 Not shown in the figure), the relevant content can be found in Figure 2 The illustrated embodiments will not be described in detail here.

[0057] In this embodiment, if the control unit hangs during sleep, since the enabling of the watchdog unit is controlled by the wake-up signal, the watchdog unit can be configured to an enabled state by the wake-up signal. The enabled watchdog unit can reset the hung control unit, and the control unit is in a normal working state after being reset by the watchdog unit, thereby improving the reliability of the reset function of the watchdog unit.

[0058] In another embodiment, both the sleep control signal and the wake-up signal are used to configure the enablement of the watchdog unit 20 to solve the problem that the control unit 10 is hung during normal operation or sleep, resulting in the watchdog unit 20 being unable to reset the control unit 10.

[0059] See also Figure 5 , Figure 5 FIG. 1 is a schematic diagram of the structure of another embodiment of the watchdog control device provided by the present application. Figure 4 Compared with the watchdog control device shown, Figure 5 The watchdog control device shown further includes a first logic gate 42. And, Figure 5 In the embodiment, the output end of the first signal providing subunit 31 is connected to the sleep control end of the control unit 10 and the first input end of the first logic gate 42, the output end of the second signal providing subunit 32 is connected to the wake-up end of the control unit 10, and the output end of the second providing subunit is also connected to the second input end of the first logic gate 42 through the conversion unit 50, and the output end of the first logic gate 42 is connected to the enable end of the watchdog unit 20.

[0060] In one embodiment, the first logic gate 42 may be an OR gate, or the first logic gate 42 may be a NOR gate. For example, if the enable of the watchdog unit 20 is effective at a high level, the first logic gate 42 may be an OR gate. In this case, as long as one of the sleep control signal and the converted wake-up signal is at a high level, the first logic gate 42 will output a high level, so that the watchdog unit 20 is configured to be in an enabled state. For another example, if the enable of the watchdog unit 20 is effective at a low level, the first logic gate 42 may be an NOR gate. In this case, as long as one of the sleep control signal and the converted wake-up signal is at a high level, the first logic gate 42 will output a low level, so that the watchdog unit 20 is configured to be in an enabled state.

[0061] In one embodiment, when the sleep control signal is used to configure the control unit 10 to be in a normal working state, the conversion unit 50 is configured to output a first level signal, the first logic gate 42 outputs a first target level signal, and the watchdog unit 20 is configured to be in an enabled state; when the sleep control signal is used to configure the control unit 10 to be in a sleep state and the wake-up signal is not a preset pulse, the conversion unit 50 is configured to output a first level signal, the first logic gate 42 outputs a second target level signal, and the watchdog unit 20 is configured to be in a disabled state; when the sleep control signal is used to configure the control unit 10 to be in a sleep state and the wake-up signal is a preset pulse, the conversion unit 50 is configured to output a second level signal, the first logic gate 42 outputs a first target level signal, and the watchdog unit 20 is configured to be in an enabled state. Wherein, the level states of the first level signal and the second level signal are opposite, the first target level signal is one of the first level signal and the second level signal, and the second target level signal is the other of the first level signal and the second level signal.

[0062] In one example, the enable of the watchdog unit 20 is high level active, and the first logic gate 42 is an OR gate.

[0063] When the level state of the sleep control signal is high, the control unit 10 is configured to be in a normal working state. In order to configure the watchdog unit 20 to be in a non-enabled state when the level state of the sleep control signal is low, the conversion unit 50 should output a first level signal with a low level. At this time, the first logic gate 42 outputs a first target level signal with a high level, so that the watchdog unit 20 is configured to be in an enabled state.

[0064] When the level state of the sleep control signal is low and the wake-up signal is not a preset pulse, the control unit 10 is configured to be in a sleep state, and the conversion unit 50 outputs a first level signal with a low level state. At this time, the first logic gate 42 outputs a second target level signal with a low level state, so that the watchdog unit 20 is configured to be in a disabled state.

[0065] When the level state of the sleep control signal is low and the wake-up signal is a preset pulse, the control unit 10 is configured to be in a sleep state, and the conversion unit 50 outputs a second level signal with a high level. At this time, the first logic gate 42 outputs a first target level signal with a high level, so that the watchdog unit 20 is configured to be in an enabled state.

[0066] In another example, the enable of the watchdog unit 20 is active low and the first logic gate 42 is a NOR gate.

[0067] When the level state of the sleep control signal is high, the control unit 10 is configured to be in a normal working state. In order to configure the watchdog unit 20 to be in a disabled state when the level state of the sleep control signal is low, the conversion unit 50 should output a first level signal with a low level. At this time, the first logic gate 42 outputs a first target level signal with a low level, so that the watchdog unit 20 is configured to be in an enabled state.

[0068] When the level state of the sleep control signal is low and the wake-up signal is not a preset pulse, the control unit 10 is configured to be in a sleep state, and the conversion unit 50 outputs a first level signal with a low level state. At this time, the first logic gate 42 outputs a second target level signal with a high level state, so that the watchdog unit 20 is configured to be in a disabled state.

[0069] When the level state of the sleep control signal is low and the wake-up signal is a preset pulse, the control unit 10 is configured to be in a sleep state, and the conversion unit 50 outputs a second level signal with a high level. At this time, the first logic gate 42 outputs a first target level signal with a low level, so that the watchdog unit 20 is configured to be in an enabled state.

[0070] For further information, see Figure 6 , Figure 6 FIG. 1 is a schematic diagram of the structure of another embodiment of the watchdog control device provided by the present application. Figure 6As shown, the conversion unit 50 specifically includes a first conversion circuit 51, a second conversion circuit 52 and a D flip-flop 53. The first input end of the first conversion circuit 51 is used to receive the first signal, the second input end of the first conversion circuit 51 is connected to the first control signal output end of the control unit 10, the output end of the first conversion circuit 51 is connected to the data input end of the D flip-flop 53, the first input end of the second conversion circuit 52 is connected to the output end of the second signal providing subunit 32, the second input end of the second conversion circuit 52 is used to receive the second signal, the third input end of the second conversion circuit 52 is connected to the second control signal output end of the control unit 10, the output end of the second conversion circuit 52 is connected to the clock input end of the D flip-flop 53, and the output end of the D flip-flop 53 is connected to the second input end of the first logic gate 42. The data input end of the D flip-flop 53 is also connected to the power supply VCC2 through the sixth resistor 54, for example, the power supply VCC2 is 5V. The first control signal output end of the control unit 10 is used to output the first control signal, and the second control signal output end of the control unit 10 is used to output the second control signal.

[0071] The first signal, the second signal, and the first control signal and the second control signal output by the control unit 10 participate in controlling the level state of the output signal of the D flip-flop 53 .

[0072] In one embodiment, the trigger type of the D flip-flop 53 is rising edge triggering, that is, when the rising edge of the clock arrives, the level state of the output signal of the D flip-flop 53 is the same as the level state of the signal at the data input end of the D flip-flop 53 at the moment of the rising edge of the clock. Optionally, in other embodiments, the trigger type of the D flip-flop 53 may also be falling edge triggering, that is, when the falling edge of the clock arrives, the level state of the output signal of the D flip-flop 53 is the same as the level state of the signal at the data input end of the D flip-flop 53 at the moment of the falling edge of the clock.

[0073] In one embodiment, the level state of the first signal and the level state of the second signal are the same as the level state of the sleep control signal. For example, the first signal and the second signal are provided by different circuits. For another example, the first signal and the second signal are provided by the same circuit, such as provided by the first signal providing subunit 31. In this case, the first input end of the first conversion circuit 51 and the third input end of the second conversion circuit 52 are both connected to the output end of the first signal providing subunit 31, and the first signal and the second signal are both sleep control signals.

[0074] In one embodiment, the first conversion circuit 51 includes a first level flip subcircuit 511 and a second logic gate 512. The input end of the first level flip subcircuit 511 is used to receive the first signal (i.e., the input end of the first level flip subcircuit 511 is the first input end of the first conversion circuit 51), the output end of the first level flip subcircuit 511 is connected to the first input end of the second logic gate 512, the second input end of the second logic gate 512 is connected to the first control signal output end of the control unit 10 (i.e., the second input end of the second logic gate 512 is the second input end of the first conversion circuit 51), and the output end of the second logic gate 512 is connected to the data input end of the D flip-flop 53 (i.e., the output end of the second logic gate 512 is the output end of the first conversion circuit 51).

[0075] The first level flipping subcircuit 511 is used to flip the level state of the first signal. For example, when the level state of the first signal is a high level, the first level flipping subcircuit 511 flips the level state of the first signal to a low level, and when the level state of the first signal is a low level, the first level flipping subcircuit 511 flips the level state of the first signal to a high level. The specific circuit structure of the first level flipping subcircuit 511 can be referred to Figure 3 The illustrated embodiments will not be described in detail here.

[0076] Exemplarily, the second logic gate 512 is an OR gate.

[0077] In one embodiment, the second conversion circuit 52 includes a third logic gate 521, a fourth logic gate 522, and a second level flip subcircuit 523. The first input end of the third logic gate 521 is connected to the output end of the second signal providing subunit 32 (i.e., the first input end of the third logic gate 521 is the first input end of the second conversion circuit 52), the input end of the second level flip subcircuit 523 is used to receive the second signal (i.e., the input end of the second level flip subcircuit 523 is the second input end of the first conversion circuit 51), the output end of the second level flip subcircuit 523 is connected to the first input end of the fourth logic gate 522, the second input end of the fourth logic gate 522 is connected to the second control signal output end of the control unit 10 (i.e., the second input end of the fourth logic gate 522 is the third input end of the second conversion circuit 52), the output end of the fourth logic gate 522 is connected to the second input end of the third logic gate 521, and the output end of the third logic gate 521 is connected to the clock input end of the D flip-flop 53 (i.e., the output end of the third logic gate 521 is the output end of the second conversion circuit 52).

[0078] The second level flipping subcircuit 523 is used to flip the level state of the second signal. For example, when the level state of the second signal is a high level, the second level flipping subcircuit 523 flips the level state of the second signal to a low level, and when the level state of the second signal is a low level, the second level flipping subcircuit 523 flips the level state of the second signal to a high level. The specific circuit structure of the second level flipping subcircuit 523 can be referred to Figure 3 The illustrated embodiments will not be described in detail here.

[0079] Exemplarily, the third logic gate 521 is an AND gate, and the fourth logic gate 522 is an OR gate.

[0080] For further information, see Figure 7 , Figure 7 It is a structural schematic diagram of another embodiment of the watchdog control device provided by the present application. Figure 7 In the embodiment, the watchdog control device further includes a fifth logic gate 43, a first input end of the fifth logic gate 43 is connected to the third control signal output end of the control unit 10, a second input end of the fifth logic gate 43 is connected to the output end of the first logic gate 42, and an output end of the fifth logic gate 43 is connected to the enable end of the watchdog unit 20. The third control signal output end of the control unit 10 is used to output a third control signal, and the third control signal is used to control the enablement of the watchdog unit 20. Exemplarily, the fifth logic gate 43 is an OR gate.

[0081] Further, please refer again to Figure 7 The watchdog control device further includes a first buffer circuit 44 and a second buffer circuit 45. The first buffer circuit 44 is connected between the output end of the first signal providing subunit 31 and the first input end of the first logic gate 42, and the second buffer circuit 45 is connected between the output end of the second signal providing subunit 32 and the wake-up end of the control unit 10. By providing the first buffer circuit 44 and the second buffer circuit 45, the driving capability of the sleep control signal and the wake-up signal can be improved, and the reliability of the watchdog control device can be further improved. The circuit structure of the first buffer circuit 44 and the second buffer circuit 45 can refer to the existing buffer circuit structure, and this embodiment will not be described in detail.

[0082] To facilitate understanding of this application, Figure 7 and Figure 8 The technical solution of the present application is exemplified. Figure 8 This is a working timing diagram of the watchdog control device provided in this application. Figure 8Wherein WD_EN represents the signal input to the enable terminal of the watchdog unit 20, Trigger_Out, Trigger Date and Trigger Clk respectively represent the output signal of the D flip-flop 53, the signal input to the data input terminal and the signal input to the clock input terminal, the first control signal, the second control signal and the third control signal respectively correspond to the signals output from the first control signal output terminal, the second control signal output terminal and the third control signal output terminal of the control unit 10, and the sleep control signal and the wake-up signal are respectively the signals output from the first signal providing subunit 31 and the second signal providing subunit 32.

[0083] In this example: the first logic gate 42, the second logic gate 512, the fourth logic gate 522 and the fifth logic gate 43 are all OR gates, and the third logic gate 521 is an AND gate; the sleep state of the control unit 10 is effective at a high level (that is, when a high level is input to the sleep control terminal of the control unit 10, the control unit 10 is configured to be in a sleep state, and when a low level is input to the sleep control terminal of the control unit 10, the control unit 10 is configured to be in a normal working state); the enable of the watchdog unit 20 is effective at a high level (that is, when a high level is input to the enable terminal of the watchdog unit 20 When the enable terminal of the watchdog unit 20 inputs a low level, the watchdog unit 20 is configured to be in the enabled state); the level state of the sleep control signal depends on whether ON1 is powered on. When ON1 is powered on, the sleep control signal is a high level of 12V, and when ON1 is powered off, the sleep control signal is a low level of 0V; when the wake-up signal is not a preset pulse, the level state is a high level, and when the wake-up signal is a preset pulse, the level state is a low level; the trigger type of the D flip-flop 53 is a rising edge trigger.

[0084] When ON1 is powered on, the sleep control signal is a high level of 12V, and the sleep control signal is flipped to a low level by the level flip circuit 41 and input to the sleep control terminal of the control unit 10, and the control unit 10 is configured to be in a normal working state. The third control signal output by the control unit 10 and the sleep control signal are used together as the input of the fifth logic gate 43. Regardless of whether the level state of the third control signal output by the control unit 10 is a high level or a low level, the fifth logic gate 43 outputs a high level, that is, the watchdog unit 20 is in an enabled state, which can shield the enable control of the watchdog unit 20 by the third control signal.

[0085] The sleep control signal with a high level state is flipped to a low level by the first level flip subcircuit 511 and input to the second logic gate 512, so that the level state of the output signal of the second logic gate 512 is controlled by the first control signal output by the control unit 10. That is, when the level state of the first control signal is low, the level state of the output signal of the second logic gate 512 is also low; when the level state of the first control signal is high, the level state of the output signal of the second logic gate 512 is also high. The sleep control signal with a high level state is flipped to a low level by the second level flip subcircuit 523 and input to the fourth logic gate 522, so that the level state of the output signal of the fourth logic gate 522 is controlled by the second control signal output by the control unit 10. Since the wake-up signal is high at this time, the level state of the output signal of the third logic gate 521 is also controlled by the second control signal output by the control unit 10. That is, when the level state of the second control signal is a low level, the level state of the output signal of the fourth logic gate 522 and the level state of the output signal of the third logic gate 521 are both low levels; when the level state of the second control signal is a high level, the level state of the output signal of the fourth logic gate 522 and the level state of the output signal of the third logic gate 521 are both high levels.

[0086] In summary, when ON1 is powered on, the enabling of the watchdog unit 20 is not controlled by the control unit 10, and the level state of the output signal of the D flip-flop 53 is controlled by the first control signal and the second control signal output by the control unit 10. During this period, the control unit 10 will configure the level state of the output signal of the D flip-flop 53 to a low level. For example, the control unit 10 can control the level state of the first control signal to be a low level and the level state of the second control signal to be a high level, so as to configure the level state of the output signal of the D flip-flop 53 to a low level. Furthermore, after outputting the first control signal with a low level and the second control signal with a high level, the control unit 10 can further detect the level state of the output signal of the D flip-flop 53 to ensure that the level state of the output signal of the D flip-flop 53 is configured to be a low level.

[0087] When ON1 is powered off, the sleep control signal is a low level of 0V, and the sleep control signal is flipped to a high level by the level flip circuit 41 and input to the sleep control terminal of the control unit 10, and the control unit 10 is configured to be in a sleep state. Since the level state of the output signal of the D flip-flop 53 and the sleep control signal are both low levels, and the control unit 10 will not enter the sleep state immediately, in a short period of time before the control unit 10 enters the sleep state (or Sleep Mode), the level state of the output signal of the fifth logic gate 43 is controlled by the control unit 10. In this short period of time, the control unit 10 can control the level state of the third control signal to be a high level, so that the fifth logic gate 43 outputs a high level, so that the watchdog unit 20 is still in an enabled state, and the control unit 10 can also control the level state of the third control signal to be a low level before entering the sleep state, so that the fifth logic gate 43 outputs a low level, so that the watchdog unit 20 is not enabled. Furthermore, the control unit 10 may further detect the level state of the enable terminal signal of the watchdog unit 20 when controlling the level state of the third control signal to be low level, so as to ensure that the watchdog unit 20 is configured to be in a disabled state.

[0088] Furthermore, after ON1 is powered off, the sleep control signal with a low level is flipped to a high level by the first level flip subcircuit 511 and input to the second logic gate 512. Regardless of whether the level of the first control signal is high or low, the level of the output signal of the second logic gate 512 is high. The sleep control signal with a low level is flipped to a high level by the second level flip subcircuit 523 and input to the fourth logic gate 522. Regardless of whether the level of the second control signal is high or low, the level of the output signal of the fourth logic gate 522 is high, so that the level of the output signal of the third logic gate 521 is controlled by the wake-up signal and no longer controlled by the second control signal. During this period, the control of the first control signal and the second control signal of the control unit 10 on the D flip-flop 53 can be shielded, so that the level of the output signal of the D flip-flop 53 is only controlled by the wake-up signal. Specifically, when the wake-up signal is a preset pulse, the third logic gate 521 also outputs a preset pulse, and the D flip-flop 53 outputs the same high level as the data input terminal at the rising edge of the clock (corresponding to the rising edge of the preset pulse), so that the first logic gate 42 and the fifth logic gate 43 both output a high level, thereby enabling the watchdog unit 20. By shielding the control of the D flip-flop 53 by the first control signal and the second control signal of the control unit 10, it is possible to avoid the pin level being uncontrollable when the control unit 10 is hung during sleep, resulting in the inability of the preset pulse of the wake-up signal to enable the watchdog unit 20.

[0089] In this embodiment, if the control unit is hung during normal working state, since the enabling of the watchdog unit is controlled by the sleep control signal, the watchdog unit is always in the enabled state during the normal working state of the control unit, so the watchdog unit can reset the hung control unit. If the control unit is hung during sleep, since the enabling of the watchdog unit is controlled by the wake-up signal, the watchdog unit can be configured to the enabled state by the wake-up signal, and the enabled watchdog unit can reset the hung control unit, and the control unit is in the normal working state after being reset by the watchdog unit, thereby improving the reliability of the reset function of the watchdog unit.

[0090] The present application also provides a vehicle, which includes any of the aforementioned watchdog control devices.

[0091] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A watchdog control device, characterized in that: The watchdog control device comprises: Control unit; A watchdog unit, wherein a dog feeding signal input terminal of the watchdog unit is connected to a dog feeding signal output terminal of the control unit, and a reset signal output terminal of the watchdog unit is connected to a reset signal input terminal of the control unit; A signal providing unit, wherein the signal providing unit is connected to a state control terminal of the control unit and an enable terminal of the watchdog unit, and the state control signal output by the signal providing unit is used to control the working state of the control unit and the enablement of the watchdog unit, so that the watchdog unit is in an enabled state when the control unit is in a normal working state, and the watchdog unit is in a disabled state when the control unit is in a sleep state.

2. The watchdog control device according to claim 1, characterized in that: The state control signal includes at least one of a sleep control signal and a wake-up signal.

3. The watchdog control device according to claim 2, characterized in that: The state control signal includes the sleep control signal and the wake-up signal, the signal providing unit includes a first signal providing sub-unit and a second signal providing sub-unit, the first signal providing sub-unit is used to output the sleep control signal, and the second signal providing sub-unit is used to output the wake-up signal; the watchdog control device also includes a conversion unit and a first logic gate; The output end of the first signal providing subunit is connected to the sleep control end of the control unit and the first input end of the first logic gate, the output end of the second signal providing subunit is connected to the wake-up end of the control unit, and the output end of the second providing subunit is also connected to the second input end of the first logic gate through the conversion unit, and the output end of the first logic gate is connected to the enable end of the watchdog unit; Wherein, when the sleep control signal is used to configure the control unit to be in a normal working state, the conversion unit is configured to output a first level signal, the first logic gate outputs a first target level signal, and the watchdog unit is configured to be in an enabled state; when the sleep control signal is used to configure the control unit to be in a sleep state and the wake-up signal is not a preset pulse, the conversion unit is configured to output the first level signal, the first logic gate outputs a second target level signal, and the watchdog unit is configured to be in a disabled state; when the sleep control signal is used to configure the control unit to be in a sleep state and the wake-up signal is a preset pulse, the conversion unit is configured to output a second level signal, the first logic gate outputs the first target level signal, and the watchdog unit is configured to be in an enabled state; the level states of the first level signal and the second level signal are opposite, the first target level signal is one of the first level signal and the second level signal, and the second target level signal is the other of the first level signal and the second level signal.

4. The watchdog control device according to claim 3, characterized in that: The conversion unit includes a first conversion circuit, a second conversion circuit and a D flip-flop; The first input end of the first conversion circuit is used to receive a first signal, the second input end of the first conversion circuit is connected to the first control signal output end of the control unit, the output end of the first conversion circuit is connected to the data input end of the D flip-flop, the first input end of the second conversion circuit is connected to the output end of the second signal providing subunit, the second input end of the second conversion circuit is used to receive a second signal, the third input end of the second conversion circuit is connected to the second control signal output end of the control unit, the output end of the second conversion circuit is connected to the clock input end of the D flip-flop, and the output end of the D flip-flop is connected to the second input end of the first logic gate.

5. The watchdog control device according to claim 4, characterized in that: The first input terminal of the first conversion circuit and the third input terminal of the second conversion circuit are both connected to the output terminal of the first signal providing subunit, and the first signal and the second signal are both the sleep control signals.

6. The watchdog control device according to claim 4, characterized in that: The first conversion circuit includes a first level flip subcircuit and a second logic gate; The input end of the first level flip sub-circuit is used to receive the first signal, the output end of the first level flip sub-circuit is connected to the first input end of the second logic gate, the second input end of the second logic gate is connected to the first control signal output end of the control unit, and the output end of the second logic gate is connected to the data input end of the D flip-flop.

7. The watchdog control device according to claim 4, characterized in that: The second conversion circuit includes a third logic gate, a fourth logic gate, and a second level flip sub-circuit; The first input end of the third logic gate is connected to the output end of the second signal providing sub-unit, the input end of the second level flip sub-circuit is used to receive the second signal, the output end of the second level flip sub-circuit is connected to the first input end of the fourth logic gate, the second input end of the fourth logic gate is connected to the second control signal output end of the control unit, the output end of the fourth logic gate is connected to the second input end of the third logic gate, and the output end of the third logic gate is connected to the clock input end of the D flip-flop.

8. The watchdog control device according to claim 3, characterized in that: The watchdog control device further comprises a fifth logic gate; The first input end of the fifth logic gate is connected to the third control signal output end of the control unit, the second input end of the fifth logic gate is connected to the output end of the first logic gate, and the output end of the fifth logic gate is connected to the enable end of the watchdog unit.

9. The watchdog control device according to claim 3, characterized in that: The watchdog control device further comprises a level flip circuit, wherein the level flip circuit is connected between the output terminal of the first signal providing subunit and the sleep control terminal of the control unit; And / or, the watchdog control device also includes a first buffer circuit and a second buffer circuit, the first buffer circuit is connected between the output end of the first signal providing subunit and the first input end of the first logic gate, and the second buffer circuit is connected between the output end of the second signal providing subunit and the wake-up end of the control unit.

10. A vehicle, characterized in that: The vehicle includes the watchdog control device according to any one of claims 1 to 9.

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