SSD mapping management method and device based on indirect address and computer equipment

Abstract

The invention relates to an SSD mapping management method and device based on an indirect address, computer equipment and a storage medium, and the method comprises the steps: dividing a first-level mapping table fragment into a plurality of sub-fragments, and storing a first-level mapping table by taking the sub-fragments of the first-level mapping table fragment as units; creating and storing an indirect address page used for recording the NAND address where the sub-fragment is located, and pointing the secondary mapping table to the indirect address page; in the process of storing the modified first-level mapping table fragment, only storing the sub-fragment of the modified first-level mapping fragment; and when the first-level mapping table fragment needs to be loaded to the RAM, reading the address of each sub fragment of the first-level mapping fragment according to the second-level mapping table, and then loading all the sub fragments to the RAM. According to the method, the larger fragment size of the first-level mapping table can be maintained, the RAM space occupied by the second-level mapping table is reduced, and the problem that too much data of the first-level mapping table is stored in a large-range random writing scene can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state drives, and in particular to a method, device, computer equipment and storage medium for managing SSD mapping based on indirect addresses. Background Art

[0002] SSD (Solid State Drive) is a new type of storage medium that uses NAND particles as data storage. It has been widely used in various fields such as PCs, notebooks, and servers, and has gradually replaced HDD (Hard Disk Drive) to become the mainstream application product in the storage field.

[0003] Since the RAM space inside DRAM-less SSD is small, the first-level mapping table is usually loaded into RAM on demand, and the second-level mapping table usually resides in RAM for simplicity. In order to reduce the RAM space occupied by the second-level mapping table, in the traditional processing process, it is usually achieved by increasing the size of the first-level mapping table slice. In this way, in a large-scale random write scenario, the first-level mapping table will store too much data, which not only affects performance but also shortens the life of the SSD. Summary of the invention

[0004] Based on this, it is necessary to provide an SSD mapping management method, device, computer equipment and storage medium based on indirect address to address the above technical problems.

[0005] A SSD mapping management method based on indirect address, the method comprising:

[0006] Divide the first-level mapping table shard into a plurality of sub-shards, and save the first-level mapping table using the sub-shards of the first-level mapping table shard as units;

[0007] Create and save an indirect address page for recording the NAND address of the sub-shard, and point the secondary mapping table to the indirect address page;

[0008] In the process of saving the modified first-level mapping table shard, only the sub-shards of the modified first-level mapping shard are saved;

[0009] When it is necessary to load the first-level mapping table slice into the RAM, firstly read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM.

[0010] In one embodiment, the method further comprises:

[0011] Get a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to get all the addresses of the sub-shards;

[0012] Get a dirty sub-slice of the mapping cache, write the allocated address into NAND and update the corresponding sub-slice address;

[0013] Determine whether the dirty sub-shards of the current mapping cache have been stored;

[0014] If yes, the allocated address is written to the indirect address page to NAND and the secondary mapping table of the mapping slice is updated.

[0015] In one embodiment, the step of writing the indirect address page to the NAND and updating the secondary mapping table of the mapping slice also includes:

[0016] Determine whether the dirty mapping cache has been processed;

[0017] If the processing is not completed, the next dirty mapping cache is obtained and the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-slice is executed. If the processing is completed, the process ends.

[0018] In one embodiment, when the first-level mapping table fragment needs to be loaded into the RAM, the steps of first reading out the addresses of each sub-fragment of the first-level mapping fragment according to the second-level mapping table and then loading all the sub-fragments into the RAM include:

[0019] When a mapping slice needs to be loaded from NAND, the indirect address page is first read out according to the secondary mapping table to obtain all sub-slice addresses, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

[0020] An SSD mapping management device based on indirect address, the device comprising:

[0021] A partitioning module, the partitioning module is used to partition the first-level mapping table fragment into a plurality of sub-fragments, and save the first-level mapping table using the sub-fragments of the first-level mapping table fragment as units;

[0022] A creation module, the creation module is used to create and save an indirect address page for recording the NAND address of the sub-shard, and point the secondary mapping table to the indirect address page;

[0023] A storage module, wherein the storage module is used to store only the sub-shards of the modified first-level mapping slice in the process of storing the modified first-level mapping table slice;

[0024] The loading module is used to read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM when the first-level mapping table slice needs to be loaded into the RAM.

[0025] In one embodiment, the device is further used for:

[0026] Get a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to get all the addresses of the sub-shards;

[0027] Get a dirty sub-slice of the mapping cache, write the allocated address into NAND and update the corresponding sub-slice address;

[0028] Determine whether the dirty sub-shards of the current mapping cache have been stored;

[0029] If yes, the allocated address is written to the indirect address page to NAND and the secondary mapping table of the mapping slice is updated.

[0030] In one embodiment, the device is further used for:

[0031] Determine whether the dirty mapping cache has been processed;

[0032] If the processing is not completed, the next dirty mapping cache is obtained and the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-slice is executed. If the processing is completed, the process ends.

[0033] In one embodiment, the loading module is further used for:

[0034] When a mapping slice needs to be loaded from NAND, the indirect address page is first read out according to the secondary mapping table to obtain all sub-slice addresses, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

[0035] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any one of the above methods when executing the computer program.

[0036] A computer-readable storage medium stores a computer program, wherein the computer program implements the steps of any one of the above methods when executed by a processor.

[0037] The above-mentioned SSD mapping management method, device, computer equipment and storage medium based on indirect address divide the first-level mapping table shard into multiple sub-shards, and save the first-level mapping table with the sub-shards of the first-level mapping table shards as units; create and save an indirect address page for recording the NAND address of the sub-shards, and point the second-level mapping table to the indirect address page; in the process of saving the modified first-level mapping table shards, only the sub-shards of the modified first-level mapping shards are saved; when it is necessary to load the first-level mapping table shards into RAM, first read out the addresses of each sub-shard of the first-level mapping shard according to the second-level mapping table and then load all the sub-shards into RAM. The present invention uses the sub-shard size of the first-level mapping table shards as the storage unit of the first-level mapping table, which can not only maintain a larger first-level mapping table shard size and reduce the RAM space occupied by the second-level mapping table, but also avoid the problem of too much first-level mapping table data being saved in a large-scale random write scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 1 is a flow chart of an SSD mapping management method based on indirect address in one embodiment;

[0039] Figure 2 A schematic diagram of a secondary mapping based on an indirect address in one embodiment is shown;

[0040] Figure 3 is a flow chart of an SSD mapping management method based on indirect address in another embodiment;

[0041] Figure 4 A schematic diagram of a process of storing a mapping table based on an indirect address in an embodiment;

[0042] Figure 5 is a structural block diagram of an SSD mapping management device based on indirect address in one embodiment;

[0043] Figure 6 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] At present, due to the small internal RAM space of DRAM-less SSD, the first-level mapping table is usually loaded into RAM on demand, and the second-level mapping table is usually resident in RAM for simplified implementation. In order to reduce the RAM space occupied by the second-level mapping table, in the traditional processing process, it is usually achieved by increasing the first-level mapping table shard size. In this way, in a large-scale random write scenario, the first-level mapping table will store too much data, which will not only affect performance but also shorten the life of the SSD.

[0046] Based on this, the present invention provides an SSD mapping management method based on indirect address, aiming to improve the write performance and life of DRAM-less SSD.

[0047] In one embodiment, Figure 1 As shown, a SSD mapping management method based on indirect address is provided, and the method includes:

[0048] Step 102, dividing the first-level mapping table shard into a plurality of sub-shards, and storing the first-level mapping table using the sub-shards of the first-level mapping table shard as units;

[0049] Step 104, creating and saving an indirect address page for recording the NAND address of the sub-shard, and pointing the secondary mapping table to the indirect address page;

[0050] Step 106, in the process of saving the modified first-level mapping table slice, only the sub-slices of the modified first-level mapping slice are saved;

[0051] Step 108, when it is necessary to load the first-level mapping table slice into the RAM, first read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM.

[0052] In this embodiment, an SSD mapping management method based on indirect address is provided, which divides a larger first-level mapping table slice into multiple sub-segments. In the process of saving the first-level mapping table, only the modified sub-segments of the mapping table slice are stored. After the sub-segments are stored, a page storing the address information of these sub-segments is stored, so that the second-level mapping table points to the page storing the sub-segment addresses. In this way, a larger first-level mapping table slice size can be maintained, reducing the RAM space occupied by the second-level mapping table, and the problem of storing too much first-level mapping table data in a large-scale random write scenario can be avoided.

[0053] Specifically, refer to Figure 2The schematic diagram of the secondary mapping table based on indirect address is shown. In the schematic diagram, the size of each mapping slice of the SSD is 4 pages, and the size of each sub-slice is 1 page. In the schematic diagram, mapping slice 1 points to the indirect address page D_5, which stores the addresses of the 4 sub-slices of mapping slice 1. Compared with the secondary mapping table of direct address, the storage of each mapping slice only needs to store the dirty sub-slices, rather than the entire slice; at the same time, because the mapping slice can be set larger, the size of the secondary mapping table can be kept smaller.

[0054] In one embodiment, when it is necessary to load a first-level mapping table slice to RAM, the steps of first reading out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then loading all the sub-slices into RAM include: when it is necessary to load a mapping slice from NAND, first reading out the indirect address page according to the second-level mapping table to obtain all the sub-slice addresses, and then loading the mapping table cache mapped to RAM according to the sub-slice addresses.

[0055] In the above embodiment, the first-level mapping table shard is divided into a plurality of sub-shards, and the first-level mapping table is saved with the sub-shards of the first-level mapping table shard as units; an indirect address page for recording the NAND address of the sub-shard is created and saved, and the second-level mapping table is pointed to the indirect address page; in the process of saving the modified first-level mapping table shard, only the sub-shards of the modified first-level mapping shard are saved; when the first-level mapping table shard needs to be loaded into RAM, the addresses of the sub-shards of the first-level mapping shard are first read out according to the second-level mapping table, and then all the sub-shards are loaded into RAM. The present invention uses the sub-shard size of the first-level mapping table shard as the storage unit of the first-level mapping table, which can not only maintain a larger first-level mapping table shard size and reduce the RAM space occupied by the second-level mapping table, but also avoid the problem of too much first-level mapping table data being saved in a large-scale random write scenario.

[0056] In one embodiment, Figure 3 As shown, a SSD mapping management method based on indirect address is provided, and the method also includes:

[0057] Step 302, obtain a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-shards;

[0058] Step 304, obtain a dirty sub-slice of the mapping cache, write the allocation address into NAND and update the corresponding sub-slice address;

[0059] Step 306, determining whether the dirty sub-shards of the current mapping cache are stored;

[0060] Step 308: If yes, then write the allocated address to the indirect address page into the NAND and update the secondary mapping table of the mapping slice.

[0061] Step 310, determining whether the dirty mapping cache has been processed;

[0062] Step 312, if the processing is not completed, obtain the next dirty mapping cache and execute the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all the addresses of the sub-shards. If it is completed, end.

[0063] Specifically, please refer to Figure 4 The flowchart of the mapping table storage based on the indirect address is shown in the figure, and the specific implementation steps are as follows:

[0064] For each dirty mapping slice, you need to first read out its current indirect address page to obtain the address of each sub-slice, then traverse the dirty sub-slices according to the bitmap, write to NAND and update the sub-slice addresses previously read in RAM. After the dirty sub-slices are stored, save the indirect address page and point the secondary mapping table to the updated indirect address page.

[0065] When a mapping slice needs to be loaded from NAND, the indirect address page needs to be read out according to the secondary mapping table first, all sub-slice addresses are obtained, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

[0066] In this embodiment, it is possible to maintain a larger first-level mapping table shard size and reduce the RAM space occupied by the second-level mapping table, and also to avoid the problem of storing too much first-level mapping table data in large-scale random write scenarios, thereby improving the write performance and life of the DRAM-less SSD.

[0067] It should be understood that although Figure 1-Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0068] In one embodiment, Figure 5 As shown, a SSD mapping management device 500 based on indirect address is provided, and the device includes:

[0069] A partitioning module 501, the partitioning module is used to partition a first-level mapping table fragment into a plurality of sub-fragments, and store the first-level mapping table in units of sub-fragments of the first-level mapping table fragment;

[0070] A creation module 502, the creation module is used to create and save an indirect address page for recording the NAND address of the sub-shard, and point the secondary mapping table to the indirect address page;

[0071] A storage module 503, wherein the storage module is used to store only the sub-shards of the modified first-level mapping table shards during the process of storing the modified first-level mapping table shards;

[0072] The loading module 504 is used to read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM when the first-level mapping table slice needs to be loaded into the RAM.

[0073] In one embodiment, the device is also used to:

[0074] Get a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to get all the addresses of the sub-shards;

[0075] Get a dirty sub-slice of the mapping cache, write the allocated address into NAND and update the corresponding sub-slice address;

[0076] Determine whether the dirty sub-shards of the current mapping cache have been stored;

[0077] If yes, the allocated address is written to the indirect address page to NAND and the secondary mapping table of the mapping slice is updated.

[0078] In one embodiment, the device is also used to:

[0079] Determine whether the dirty mapping cache has been processed;

[0080] If the processing is not completed, the next dirty mapping cache is obtained and the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-slice is executed. If the processing is completed, the process ends.

[0081] In one embodiment, the loading module 504 is further used to:

[0082] When a mapping slice needs to be loaded from NAND, the indirect address page is first read out according to the secondary mapping table to obtain all sub-slice addresses, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

[0083] The specific limitations of the SSD mapping management device based on the indirect address can be found in the above limitations of the SSD mapping management method based on the indirect address, which will not be repeated here.

[0084] In one embodiment, a computer device is provided, whose internal structure diagram can be as follows: Figure 6 As shown. The computer device includes a processor, a memory and a network interface connected through a device bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating device, a computer program and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an SSD mapping management method based on an indirect address is implemented.

[0085] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0086] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps in the above method embodiments when executing the computer program.

[0087] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0088] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A SSD mapping management method based on indirect address, the method comprising: Divide the first-level mapping table shard into a plurality of sub-shards, and save the first-level mapping table using the sub-shards of the first-level mapping table shard as units; Create and save an indirect address page for recording the NAND address of the sub-shard, and point the secondary mapping table to the indirect address page; In the process of saving the modified first-level mapping table shard, only the sub-shards of the modified first-level mapping shard are saved; When it is necessary to load the first-level mapping table slice into the RAM, firstly read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM.

2. The SSD mapping management method based on indirect address according to claim 1, characterized in that: The method further comprises: Get a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to get all the addresses of the sub-shards; Get a dirty sub-slice of the mapping cache, write the allocated address into NAND and update the corresponding sub-slice address; Determine whether the dirty sub-shards of the current mapping cache have been stored; If yes, the allocated address is written to the indirect address page to NAND and the secondary mapping table of the mapping slice is updated.

3. The SSD mapping management method based on indirect address according to claim 2, characterized in that: After the step of allocating the address to write the indirect address page to the NAND and updating the secondary mapping table of the mapping slice, the following steps are also included: Determine whether the dirty mapping cache has been processed; If the processing is not completed, the next dirty mapping cache is obtained and the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-slice is executed. If the processing is completed, the process ends.

4. The SSD mapping management method based on indirect address according to any one of claims 1 to 3, characterized in that: When the first-level mapping table fragment needs to be loaded into the RAM, the steps of first reading out the addresses of each sub-fragment of the first-level mapping fragment according to the second-level mapping table and then loading all the sub-fragments into the RAM include: When a mapping slice needs to be loaded from NAND, the indirect address page is first read out according to the secondary mapping table to obtain all sub-slice addresses, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

5. An SSD mapping management device based on indirect address, characterized in that: The device comprises: A partitioning module, the partitioning module is used to partition the first-level mapping table fragment into a plurality of sub-fragments, and save the first-level mapping table using the sub-fragments of the first-level mapping table fragment as units; A creation module, the creation module is used to create and save an indirect address page for recording the NAND address of the sub-shard, and point the secondary mapping table to the indirect address page; A storage module, wherein the storage module is used to store only the sub-shards of the modified first-level mapping slice in the process of storing the modified first-level mapping table slice; The loading module is used to read out the addresses of each sub-slice of the first-level mapping slice according to the second-level mapping table and then load all the sub-slices into the RAM when the first-level mapping table slice needs to be loaded into the RAM.

6. The SSD mapping management device based on indirect address according to claim 5, characterized in that: The device is also used for: Get a dirty mapping cache, read the indirect address page of the current dirty mapping according to the secondary mapping table to get all the addresses of the sub-shards; Get a dirty sub-slice of the mapping cache, write the allocated address into NAND and update the corresponding sub-slice address; Determine whether the dirty sub-shards of the current mapping cache have been stored; If yes, the allocated address is written to the indirect address page to NAND and the secondary mapping table of the mapping slice is updated.

7. The SSD mapping management device based on indirect address according to claim 6, characterized in that: The device is also used for: Determine whether the dirty mapping cache has been processed; If the processing is not completed, the next dirty mapping cache is obtained and the step of reading the indirect address page of the current dirty mapping according to the secondary mapping table to obtain all addresses of the sub-slice is executed. If the processing is completed, the process ends.

8. The SSD mapping management device based on indirect address according to any one of claims 5 to 7, characterized in that: The loading module is also used for: When a mapping slice needs to be loaded from NAND, the indirect address page is first read out according to the secondary mapping table to obtain all sub-slice addresses, and then the mapping table cache mapped to RAM is loaded according to the sub-slice addresses.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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