DMA arbiter and DMA arbitration method

Abstract

The invention provides a DMA (Direct Memory Access) arbiter and a DMA arbitration method. The DMA arbiter comprises a priority processing module, a transmission counting module and a configuration module; the configuration module is used for configuring the maximum transmission times corresponding to each DMA channel in the multiple DMA channels; the priority processing module is used for determining a target DMA channel from the multiple DMA channels and sending the target DMA channel to the DMA controller; wherein in the plurality of transmission requests corresponding to the plurality of DMA channels, the priority of the transmission request corresponding to the target DMA channel is the highest; the transmission counting module is used for determining whether the number of transmission times corresponding to the DMA channel reaches the maximum number of transmission times corresponding to the DMA channel. According to the DMA arbiter provided by the embodiment of the invention, priority selection and polling transmission of DMA transmission channels are realized, the priority and fairness of DMA multi-channel transmission are ensured, and the flexibility of the DMA arbiter is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a DMA arbitrator and a DMA arbitration method. Background Art

[0002] Direct Memory Access (DMA) is a technology that enables direct data exchange between hardware peripherals and internal memory without the intervention of the central processing unit (CPU). As a high-speed data transmission technology, it plays an important role in the field of modern memory chips.

[0003] In the related art, when multi-channel DMA data is transmitted, there will be transmission conflicts between different peripherals, which will affect the data transmission efficiency and system performance. The existing arbitration method is fixed and not flexible enough, and cannot meet the needs of some continuous transmission request scenarios. Therefore, how to reasonably design the DMA arbitrator has an important impact on the transmission efficiency. Summary of the invention

[0004] The present invention provides a DMA arbitrator and a DMA arbitration method. By setting a priority processing module and a transmission counting module, priority selection and polling transmission of DMA transmission channels are realized, and the priority and fairness of DMA multi-channel transmission are guaranteed; and by configuring the hardware unit of the DMA arbitrator, the flexibility of the DMA arbitrator is improved.

[0005] The present invention provides a DMA arbiter, comprising: Priority processing module, transmission counting module and configuration module; The configuration module is used to configure the maximum number of transmissions corresponding to each DMA channel in the multiple DMA channels; The priority processing module is used to determine a target DMA channel from a plurality of DMA channels and send the target DMA channel to a DMA controller; wherein, among a plurality of transfer requests corresponding to the plurality of DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; The transmission counting module is used to determine whether the number of transmissions corresponding to the DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

[0006] According to a DMA arbiter provided by the present invention, the transfer counting module comprises: A channel counting unit, a transmission counting unit and a channel enabling unit; wherein,

[0007] The transmission count is used to count the number of transmissions corresponding to each DMA channel to obtain the number of transmissions corresponding to each DMA channel; The channel enabling unit is used to enable the DMA channel when the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel; The channel counting unit is used to count the DMA channels that have completed the transmission.

[0008] According to a DMA arbiter provided by the present invention, the configuration module is also used to configure the channel holding transmission information corresponding to the DMA channel; the channel holding transmission information is used to indicate that when the number of transmissions corresponding to the DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, the transmission continues on the DMA channel.

[0009] According to a DMA arbiter provided by the present invention, the DMA arbiter further includes: A logic processing module; the logic processing module is used to determine whether a transmission request is a valid transmission request.

[0010] According to a DMA arbiter provided by the present invention, the logic processing module is specifically used for: When the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel, or when the channel corresponding to the DMA channel maintains the transmission information as the target value, the transmission request is determined to be a valid transmission request.

[0011] According to a DMA arbiter provided by the present invention, the DMA arbiter further includes: Comparator; the comparator is used to determine whether the target DMA channel has changed based on the current target DMA channel and the cached historical target DMA channel; The channel counting unit is used to determine that the DMA channel has completed transmission when the number of transmissions corresponding to the DMA channel is equal to the maximum number of transmissions corresponding to the DMA channel; or to determine that the DMA channel has completed transmission when the number of transmissions corresponding to the DMA channel is less than the maximum number of transmissions corresponding to the DMA channel but the target DMA channel has changed.

[0012] The present invention also provides a DMA, comprising the DMA arbitrator.

[0013] The present invention also provides a DMA arbitration method, comprising: Configure the maximum number of transfers corresponding to each DMA channel in multiple DMA channels; Determine a target DMA channel from the multiple DMA channels and send it to the DMA controller; wherein, among the multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; Determine whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any one of the above-mentioned DMA arbitration methods is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the DMA arbitration method described above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any one of the above-mentioned DMA arbitration methods.

[0017] The DMA arbiter provided by the present invention realizes the priority selection and polling transmission of DMA transmission channels by setting a priority processing module and a transmission counting module, thereby ensuring the priority and fairness of DMA multi-channel transmission; and the flexibility of the DMA arbiter is improved by configuring the hardware unit of the DMA arbiter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of the arbitrator provided by the present invention.

[0020] Figure 2 It is a schematic diagram of the transmission counting module provided by the present invention.

[0021] Figure 3 is a schematic diagram of another arbitrator provided by the present invention.

[0022] Figure 4 It is a schematic diagram of the priority selection module provided by the present invention.

[0023] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Combine the following Figure 1-Figure 5 The DMA arbitrator and DMA arbitration method of the present invention are described.

[0026] In order to facilitate a clearer understanding of the technical solutions of the embodiments of the present application, some technical contents related to the embodiments of the present application are first introduced.

[0027] Direct Memory Access (DMA) is a technology that enables direct data exchange between hardware peripherals and internal memory without the intervention of the central processing unit (CPU). As a high-speed data transmission technology, it plays an important role in the field of modern memory chips.

[0028] As the system scale of SoC (System on Chip) chips continues to grow, there are higher requirements for the number of chip peripherals and the data transmission rate between memory and peripherals. The traditional single-channel DMA controller can no longer meet the design requirements of current SOC chips, so multi-channel DMA controllers are widely used.

[0029] When transmitting data in multi-channel DMA, there will be transmission conflicts between different peripherals, which will affect data transmission efficiency and system performance. The DMA arbiter can be responsible for making decisions and scheduling multiple peripheral requests to ensure that multiple requests can be processed efficiently and orderly, thereby improving the performance and response speed of the entire system. Therefore, the reasonable design of the DMA arbiter plays an important role in the transmission efficiency of DMA.

[0030] At present, the traditional arbitration method is fixed and not flexible enough, and cannot meet the requirements of some continuous transmission requests and burst high-priority request transmission scenarios.

[0031] Figure 1 Schematic diagram of the DMA arbiter provided by the present invention, including the following: Priority processing module, transmission counting module and configuration module; The configuration module is used to configure the maximum number of transmissions corresponding to each DMA channel in multiple DMA channels; The priority processing module is used to determine a target DMA channel from multiple DMA channels and send it to the DMA controller; wherein, among multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; The transfer counting module is used to determine whether the number of transfers corresponding to the target DMA channel has reached the maximum number of transfers corresponding to the DMA channel.

[0032] Specifically, the DMA arbiter in the embodiment of the present application includes a priority processing module, a transfer counting module and a configuration module.

[0033] The configuration module is used to configure the maximum number of transmissions corresponding to each DMA channel in multiple DMA channels. For example, according to the actual transmission requirements, the configuration is performed through the APB bus interface, the maximum number of continuous requests (i.e., the maximum number of transmissions) for each DMA channel is configured, and the DMA arbiter enters the normal weighted polling arbitration mode.

[0034] The priority processing module is used to determine the target DMA channel from multiple DMA channels and send it to the DMA controller; among the multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority. For example, the priority processing module processes the data transfer requests (rep_ch1~N) and priority level signals (CH1_PL~CHN_PL) of N channels, outputs the DMA channel number (ch_num) with the highest priority and sends it to the DMA controller, so that data can be transferred on the target DMA channel with the highest priority.

[0035] The transfer count module is used to determine whether the number of transfers corresponding to the DMA channel has reached the maximum number of transfers corresponding to the DMA channel. For example, the transfer count module obtains the maximum number of consecutive requests for different channels through the APB bus configuration signal (apb_cfg_reqcnt_ch1~N), and combines it with the highest priority channel number (ch_num) output by the priority processing module. Optionally, when the number of transfers corresponding to the target DMA channel is less than or equal to the maximum number of transfers corresponding to the DMA channel, the current target DMA channel continues to be enabled for data transmission; when the number of transfers corresponding to the target DMA channel is greater than the maximum number of transfers corresponding to the DMA channel, it indicates that the target DMA channel has completed the transfer and can continue to poll other DMA channels for data transmission.

[0036] The DMA arbiter in the above embodiment determines the target DMA channel with the highest priority from multiple DMA channels through the priority processing module, and determines whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel through the transmission counting module, so that on the basis of satisfying the priority and fairness of DMA data transmission, the continuous transmission request of the DMA channel can also be effectively satisfied. That is, the present application realizes the priority selection and polling transmission of the DMA transmission channel by setting the priority processing module and the transmission counting module, and ensures the priority and fairness of DMA multi-channel transmission; and by configuring the DMA arbiter hardware unit, the flexibility of the DMA arbiter is improved.

[0037] In one embodiment, the transmission counting module includes: A channel counting unit, a transmission counting unit and a channel enabling unit; wherein,

[0038] The transmission counting unit is used to count the number of transmissions corresponding to each DMA channel to obtain the number of transmissions corresponding to each DMA channel; The channel enabling unit is used to enable the DMA channel when the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel; The channel counting unit is used to count the DMA channels that have completed the transfer.

[0039] Specifically, the transmission counting module in the embodiment of the present application includes a channel counting unit, a transmission counting unit and a channel enabling unit. Among them, the transmission counting unit is used to count the number of transmissions corresponding to each DMA channel to obtain the number of transmissions corresponding to each DMA channel, and then when the number of transmissions corresponding to the DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, it indicates that the DMA channel has completed the transmission and can continue to poll other DMA channels for data transmission.

[0040] The channel enabling unit is used to enable the DMA channel when the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel. For example, when the number of transmissions corresponding to the DMA channel is less than the maximum number of transmissions corresponding to the DMA channel, the current DMA channel continues to be enabled for data transmission.

[0041] The channel counting unit is used to count the DMA channels that have completed the transmission. For example, if there are 8 DMA channels in total, if all 8 DMA channels have completed the transmission, the polling transmission of the 8 DMA channels can be restarted based on the priority.

[0042] For example, the transmission counting module Figure 2 As shown, the module is mainly divided into a channel counting unit, a transmission counting unit and a channel enabling unit.

[0043] The channel counting unit counts the channels that have completed transmission, and outputs the ch_en_reset signal when all transmissions are completed, which is used to reset the enable signals of all channels; the default initial value of the channel counter is 0. When the count value is equal to the number of DMA channels N, the counter is set to 0 and the ch_en_reset signal is pulled high.

[0044] The transfer counting unit counts the channel transfer requests. When all requests for a channel are transferred, the req_compelet signal is output. The default initial value of the transfer counter is 0. According to the current DMA channel number (ch_num), the maximum number of continuous requests configured for the channel (apb_cfg_reqcnt_ch1~N) is selected as the maximum value (cnt_max) of the transfer counter. When the transfer is completed and the tran_compelet signal is pulled high, the counter is +1. When the count value is equal to the maximum value of the counter cnt_max, the counter is set to 0 and the req_compelet signal is pulled high.

[0045] The channel enable unit is a module that controls the working status of the DMA transmission channel. It outputs the enable signal (ch1_en~chN_en). When the enable signal is high, the DMA channel works normally. The default value of each channel enable signal is 1. When all requests for the channel are transmitted, that is, (tran_change|req_compelet)=1, the corresponding channel enable signal will be pulled low. When all channels are transmitted, that is, ch_en_reset=1, all channel signals will return to the default value, all values ​​1.

[0046] The DMA arbiter in the above embodiment includes a channel counting unit, a transmission counting unit and a channel enabling unit, so that it can accurately and quickly determine whether the number of transmissions corresponding to the DMA channel has reached the maximum number of transmissions corresponding to the DMA channel, thereby effectively satisfying the continuous transmission request of the DMA channel; and when it is determined that all channels have completed the transmission, all DMA channels can be polled and transmitted again based on the priority, making the DMA arbitration method more flexible and accurate.

[0047] In one embodiment, the configuration module is further used to configure the channel holding transmission information corresponding to the DMA channel; the channel holding transmission information is used to indicate that when the number of transmissions corresponding to the DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, continue to transmit on the DMA channel.

[0048] Specifically, in the embodiment of the present application, the configuration module is also used to configure the channel holding transmission information corresponding to the DMA channel; the channel holding transmission information is used to indicate that when the number of transmissions corresponding to the DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, the transmission continues on the DMA channel, so that it is no longer limited by the number of transmissions corresponding to the DMA channel, and burst high-priority request transmissions can be effectively met.

[0049] For example, when the system requires a certain channel (assuming it is channel m) to maintain transmission, the channel hold transmission information (apb_cfg_tran_hold_chm) of the channel can be configured to 1 through the APB bus, and the channel can be configured to have the highest priority level. In this case, continuous transmission of the channel can be guaranteed.

[0050] The DMA arbiter in the above embodiment maintains transmission information by configuring the channel corresponding to the DMA channel, so that the data transmission process is no longer limited by the number of transmissions corresponding to the DMA channel, and burst high-priority request transmissions are effectively satisfied.

[0051] In one embodiment, the DMA arbiter further includes: Logical processing module: The logical processing module is used to determine whether the transmission request is a valid transmission request.

[0052] Specifically, when the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel, or when the channel corresponding to the DMA channel maintains the transmission information as the target value, the transmission request is determined to be a valid transmission request, and the DMA channel can be enabled for data transmission.

[0053] For example, in the initial state, the transmission valid signals of each channel (ch1_en~chN_en) are all 1. Each channel initiates a request, pulls the transmission request signal (rep_ch1~N) high, and transmits its own priority level (CH1_PL~CHN_PL). At this time, the real request valid signal (req_enable_1~N) is obtained through the operation of the AND or logic gate.

[0054] In the DMA arbiter of the above embodiment, the logic processing module can accurately determine whether a transmission request is a valid transmission request based on the number of transmissions corresponding to the DMA channel and the channel-maintained transmission information corresponding to the DMA channel, thereby enabling the DMA channel to quickly and accurately perform data transmission.

[0055] In one embodiment, the DMA arbiter further includes: Comparator; the comparator is used to determine whether the target DMA channel has changed based on the current target DMA channel and the cached historical target DMA channel; The channel counting unit is used to determine that the DMA channel has completed the transmission when the number of transmissions corresponding to the DMA channel is equal to the maximum number of transmissions corresponding to the DMA channel; or, when the number of transmissions corresponding to the DMA channel is less than the maximum number of transmissions corresponding to the DMA channel but the target DMA channel has changed, determine that the DMA channel has completed the transmission.

[0056] Specifically, the DMA arbiter in the embodiment of the present application also includes a comparator; wherein the comparator is used to determine whether the target DMA channel has changed based on the current target DMA channel and the cached historical target DMA channel. For example, if DMA channel 1 is used for data transmission at the current time T, and DMA channel 2 is used for data transmission at the cached historical time T-1, it is determined that the target DMA channel has changed. That is, the role of the comparator is to process the channel number (ch_num), and output a channel change signal (tran_change) when the channel number changes.

[0057] The channel counting unit is used to determine that the DMA channel has completed the transmission when the number of transmissions corresponding to the DMA channel is equal to the maximum number of transmissions corresponding to the DMA channel; or when the number of transmissions corresponding to the DMA channel is less than the maximum number of transmissions corresponding to the DMA channel but the target DMA channel has changed, determine that the DMA channel has completed the transmission. For example, when the maximum number of transmissions corresponding to DMA channel 1 is 100, if the number of transmissions corresponding to DMA channel 1 is equal to 50 times and all data has been transmitted, it is determined that DMA channel 1 has completed the transmission, and the polling transmission of the remaining 7 DMA channels can continue based on the priority.

[0058] The DMA arbiter of the above embodiment, when the DMA channel changes, determines that the DMA channel has completed the transmission, and can continue the polling transmission of the remaining DMA channels based on the priority, so that on the basis of priority transmission and fairness, it can be flexibly configured and adjusted to meet the data transmission requirements of different peripherals.

[0059] Exemplarily, the DMA arbiter in the embodiment of the present application is as follows: Figure 3 As shown, it includes a priority processing module, a transmission counting module, a configuration module, a comparator and a logic processing module.

[0060] The priority processing module mainly processes the data transmission requests (rep_ch1~N) and priority level signals (CH1_PL~CHN_PL) of N channels, and at the same time receives the APB configuration signal (apb_cfg_tran_hold_ch1~N) and the transmission valid signal (ch1_en~chN_en) fed back by the transmission counting module, and outputs the DMA channel number (ch_num) with the highest priority.

[0061] Exemplarily, the implementation block diagram of the priority selection module is as follows Figure 4 As shown, the specific implementation process is as follows: first, the request valid signals and priority level signals of N DMA channels are sent to the decoding module.

[0062] Taking channel 1 as an example, CH1_PL corresponds to four priority levels: 0, 1, 2, and 3 (the higher the number, the higher the priority), which correspond to the channel decoding unit output signals ch1_dec0~ch1_dec3 respectively. When the request valid signal is 1, the decoding output result is valid, the corresponding signal is pulled high, and the other signals are low.

[0063] Then, the decoding results generated by the N DMA channels are sent to the four data processing units according to the level. Taking the highest level data processing unit as an example, the unit judges and selects the input signals ch1_dec3~chN_dec3. The module outputs ch_num3 as the corresponding channel number of the input signal equal to 1. If there are multiple signals equal to 1, the smallest channel number is output. If the input signals are all 0, ch_num3=0 is output; at the same time, another output signal ch_sel_3 of the data processing unit is equal to the result of the OR operation of the N input signals. Finally, the selection logic is formed by combining the two-choice data selector and the logic gate, and the channel number (ch_num0~ch_num3) is selected according to the selection signals (ch_sel_0~ch_sel_3) output by the four data processing units, and the channel number signal (ch_num) with the highest priority is output.

[0064] The transmission counting module mainly obtains the maximum number of continuous requests for different channels through the APB bus configuration signal (apb_cfg_reqcnt_ch1~N), and combines the highest priority channel number (ch_num) output by the priority processing module, the single request transmission completion signal (tran_compelet) and the channel change signal (tran_change), and pulls down the enable signal (ch1_en~chN_en) of the current transmission channel through the counter logic.

[0065] The function of the comparator is to process the channel number (ch_num) and output a channel change signal (tran_change) when the channel number changes.

[0066] The function of the APB bus configuration part is that the software configures the parameters of the DMA arbiter through the APB bus, and configures the maximum number of continuous requests (apb_cfg_reqcnt_ch1~N) and the channel hold transmission signal (apb_cfg_tran_hold_ch1~N) for N DMA channels respectively.

[0067] The purpose of the logic gates is to implement the necessary logic for data processing within the DMA arbiter.

[0068] The DMA arbiter of the embodiment of the present application effectively solves the multi-channel DMA data transmission requirements in the SOC chip, designs the DMA arbiter, and proposes a DMA arbiter that can implement weighted polling. The present application implements the priority selection and polling transmission of the DMA transmission channel by setting a priority processing module and a transmission counting module, thereby ensuring the priority and fairness of DMA multi-channel transmission; and configures the DMA arbiter hardware unit through the APB interface, thereby improving the flexibility of the DMA arbiter.

[0069] The embodiment of the present application also provides an arbitration method, including: Configure the maximum number of transfers corresponding to each DMA channel in multiple DMA channels; Determine a target DMA channel from the multiple DMA channels and send it to the DMA controller; wherein, among the multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; Determine whether the number of transfers corresponding to the target DMA channel has reached the maximum number of transfers corresponding to the DMA channel.

[0070] Specifically, firstly, the maximum continuous request quantity (ie, the maximum number of transmission times) of each DMA channel can be configured through the APB bus interface according to the actual transmission demand, and the DMA arbiter enters the normal weighted polling arbitration mode.

[0071] Then, the target DMA channel is determined from the multiple DMA channels and sent to the DMA controller; wherein, among the multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority. For example, the priority processing module processes the data transfer requests (rep_ch1~N) and priority level signals (CH1_PL~CHN_PL) of N channels, outputs the DMA channel number (ch_num) with the highest priority and sends it to the DMA controller, so that the target DMA channel with the highest priority can be used for data transmission.

[0072] Finally, determine whether the number of transmissions corresponding to the DMA channel has reached the maximum number of transmissions corresponding to the DMA channel. For example, the maximum number of continuous requests for different channels is obtained through the APB bus configuration signal (apb_cfg_reqcnt_ch1~N), and combined with the highest priority channel number (ch_num) output by the priority processing module. Optionally, if the number of transmissions corresponding to the target DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel, the current target DMA channel continues to be enabled; if the number of transmissions corresponding to the target DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, it indicates that the target DMA channel has completed the transmission and can continue to poll other DMA channels for data transmission.

[0073] The above-mentioned embodiment method determines the target DMA channel with the highest priority from multiple DMA channels, and determines whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel, thereby effectively satisfying the continuous transmission request of the DMA channel on the basis of satisfying the priority and fairness of DMA data transmission.

[0074] Exemplarily, the specific process of the DMA arbitration method is as follows: 1. Configure the DMA arbiter through the APB bus interface according to the actual transmission requirements, configure the maximum number of continuous requests for each transmission channel, and configure all channels to hold the transmission signal (apb_cfg_tran_hold_ch1~N) to 0. The DMA arbiter enters the normal weighted polling arbitration mode.

[0075] 2. After the configuration is completed, the DMA arbiter works normally. In the initial state, the transmission valid signals of each channel (ch1_en~chN_en) are all 1. Each channel initiates a request, pulls the transmission request signal (rep_ch1~N) high, and transmits its own priority level (CH1_PL~CHN_PL). At this time, the real request valid signal (req_enable_1~N) is obtained through the operation of the AND or logic gate.

[0076] 3. The priority processing module obtains the request valid signal and priority level of each channel for processing, and outputs the channel number (ch_num) with the highest priority at the current moment. This signal is output to the DMA controller for selecting the DMA transmission channel, and is also passed to the transmission counter module and comparator.

[0077] 4. After the channel is selected, the data is transmitted normally. Each time a request transmission is completed, the DMA arbiter will receive a transmission completion signal (tran_compelet). At the same time, the comparator receives the current ch_num and the cached ch_num signals for comparison. When the signals are inconsistent, the transmission channel changes and the output signal tran_change.

[0078] 5. The transmission counter module receives tran_compelet, ch_num, and tran_change signals for processing. When the number of transmission requests reaches the maximum number of times configured by APB and does not reach the maximum number of transmissions and the transmission channel changes, the module pulls down the transmission valid signal of the transmission completion channel. When the transmission valid signals of all channels are pulled low, a polling transmission is completed and the signal is reset.

[0079] 6. When a channel DMA transmission is completed, the transmission valid signal will be pulled low, which will pull down the request valid signal of the corresponding channel. The priority selection module will re-output the new highest priority channel. When there is no more request in the current DMA transmission channel, the request valid signal will also be pulled low, and a new transmission channel will be selected again. The above steps 2 to 6 will be repeated until a weighted polling arbitration is completed.

[0080] 7. As an exception, when the system requires a certain channel (assuming it is channel m) to maintain transmission, the channel hold transmission signal (apb_cfg_tran_hold_chm) of the channel can be configured to 1 through the APB bus, and the channel can be configured to the highest priority level. At this time, continuous transmission of the channel can be guaranteed.

[0081] The above embodiment uses a priority processing module, a transmission counting module and a logic processing module to implement a weighted polling arbiter with priority, which can realize the priority selection and polling transmission of the DMA transmission channel, and ensure the priority and fairness of DMA multi-channel transmission. In addition, the DMA arbiter hardware unit can be configured through the APB bus interface according to the transmission requirements of different peripherals, which greatly improves the flexibility of the DMA arbiter, and the implementation method is simple and easy to implement in hardware. The DMA arbiter in this application can realize that the DMA controller can be flexibly configured and adjusted to meet the data transmission requirements of different peripherals on the basis of priority transmission and fairness.

[0082] Figure 5The physical structure diagram of an electronic device is illustrated, and the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the DMA arbitration method, and the method includes: configuring the maximum number of transmissions corresponding to each DMA channel in a plurality of DMA channels; determining the target DMA channel from the plurality of DMA channels and sending it to the DMA controller; wherein, among the plurality of transmission requests corresponding to the plurality of DMA channels, the transmission request corresponding to the target DMA channel has the highest priority; determining whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

[0083] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0084] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the DMA arbitration method provided by the above-mentioned methods, which includes: configuring the maximum number of transmissions corresponding to each DMA channel in a plurality of DMA channels; determining a target DMA channel from a plurality of DMA channels and sending it to a DMA controller; wherein, among a plurality of transmission requests corresponding to a plurality of DMA channels, a transmission request corresponding to a target DMA channel has the highest priority; determining whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

[0085] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the DMA arbitration method provided by the above-mentioned methods, the method comprising: configuring a maximum number of transmissions corresponding to each DMA channel in a plurality of DMA channels; determining a target DMA channel from a plurality of DMA channels and sending it to a DMA controller; wherein, among a plurality of transmission requests corresponding to a plurality of DMA channels, a transmission request corresponding to a target DMA channel has the highest priority; and determining whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

[0086] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0087] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DMA arbiter, characterized in that: include: Priority processing module, transmission counting module and configuration module; The configuration module is used to configure the maximum number of transmissions corresponding to each DMA channel in the multiple DMA channels; The priority processing module is used to determine a target DMA channel from a plurality of DMA channels and send the target DMA channel to a DMA controller; wherein, among a plurality of transfer requests corresponding to the plurality of DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; The transmission counting module is used to determine whether the number of transmissions corresponding to the DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

2. The DMA arbiter according to claim 1, characterized in that: The transmission counting module comprises: A channel counting unit, a transmission counting unit and a channel enabling unit; wherein, The transmission counting unit is used to count the number of transmissions corresponding to each DMA channel to obtain the number of transmissions corresponding to each DMA channel; The channel enabling unit is used to enable the DMA channel when the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel; The channel counting unit is used to count the DMA channels that have completed the transmission.

3. The DMA arbiter according to claim 1, wherein: The configuration module is also used to configure the channel holding transmission information corresponding to the DMA channel; the channel holding transmission information is used to indicate that when the number of transmissions corresponding to the DMA channel is greater than the maximum number of transmissions corresponding to the DMA channel, the transmission on the DMA channel continues.

4. The DMA arbiter according to any one of claims 1 to 3, characterized in that: The DMA arbiter also includes: A logic processing module; the logic processing module is used to determine whether a transmission request is a valid transmission request.

5. The DMA arbiter according to claim 4, characterized in that: The logic processing module is specifically used for: When the number of transmissions corresponding to the DMA channel is less than or equal to the maximum number of transmissions corresponding to the DMA channel, or when the channel corresponding to the DMA channel maintains the transmission information as the target value, the transmission request is determined to be a valid transmission request.

6. The DMA arbiter according to claim 2, characterized in that: The DMA arbiter also includes: Comparator; the comparator is used to determine whether the target DMA channel has changed based on the current target DMA channel and the cached historical target DMA channel; The channel counting unit is used to determine that the DMA channel has completed transmission when the number of transmissions corresponding to the DMA channel is equal to the maximum number of transmissions corresponding to the DMA channel; or to determine that the DMA channel has completed transmission when the number of transmissions corresponding to the DMA channel is less than the maximum number of transmissions corresponding to the DMA channel but the target DMA channel has changed.

7. A direct memory access DMA device, characterized in that: Comprising a DMA arbiter as claimed in any one of claims 1 to 6.

8. A DMA arbitration method, characterized in that: The DMA arbiter according to any one of claims 1 to 6 comprises: Configure the maximum number of transfers corresponding to each DMA channel in multiple DMA channels; Determine a target DMA channel from the multiple DMA channels and send it to the DMA controller; wherein, among the multiple transfer requests corresponding to the multiple DMA channels, the transfer request corresponding to the target DMA channel has the highest priority; Determine whether the number of transmissions corresponding to the target DMA channel has reached the maximum number of transmissions corresponding to the DMA channel.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the DMA arbitration method according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the DMA arbitration method according to any one of claims 1 to 6 is implemented.

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