Method and device for parameterizing filter based on FPGA, electronic equipment and storage medium

Abstract

The invention provides a method and device for parameterizing a filter based on an FPGA, electronic equipment and a storage medium, is applied to the technical field of communication, dynamically generates a corresponding number of multipliers according to the number of filter coefficients, and realizes flexible configuration of the filter. The filter coefficients are sequentially input into the corresponding multipliers through the input ports, so that the filter coefficients can be flexibly adjusted according to requirements; the shift register module is used for carrying out multi-stage processing on the filtering signals, and the processed signals are sequentially input into the multiplier, so that a cascade structure of the filter is realized, the filtering signals processed at each stage and corresponding filter coefficients are simultaneously subjected to product operation, the calculation efficiency is improved, and the product result is subjected to weighted calculation; through the design, the universality and the flexibility of the filter are greatly improved, the same filter module can be applied to different scenes, and therefore the development time is shortened, and the development cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, device, electronic device and storage medium based on FPGA parameterized filter. Background Art

[0002] With the rapid development of information technology, digital signal processing technology has become increasingly important in the fields of audio processing, image processing and communication systems. The demand for accuracy, speed and resource efficiency in digital signal processing is increasing. FIR digital filters are widely used in communication systems in the system design process such as cross-domain communication and underwater acoustic communication. Among them, FIR filters are mainly used for signal pulse shaping and noise elimination. With the continuous development of cross-domain communication, the communication environment has become increasingly complex and unstable factors have increased. For the signal at the transmitting end, it is required to eliminate inter-code interference as much as possible; for the receiving end, the noise reduction capability is required to be higher and higher. Therefore, in order to ensure the overall communication efficiency and reduce the development complexity, a flexible, adjustable and easy-to-package parameterized FIR digital filter is needed in the cross-domain communication system.

[0003] In order to meet the needs of parameterized design of FIR filters, it has become a trend to use field programmable gate arrays (FPGAs) to implement filters. Typically, digital filter design on FPGAs relies on parameters exported through MATLAB and deployed through specific IP cores. Although this approach can achieve filtering goals, it requires the system to reconfigure the filter module to cope with changes in parameters such as symbol rate or carrier rate, which limits the versatility and portability of the filter module and increases development time costs.

[0004] Therefore, the prior art lacks a more universal and flexible FIR filter module. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present application provides a method, device, electronic device and storage medium based on FPGA parameterized filter, which is applied to the field of communication technology, and realizes the parameterized design of FIR filter by dynamically configuring the number of multipliers (i.e., filter order), the corresponding register storage and flexible input filter coefficients. It allows to adapt to different filtering requirements by adjusting the input parameters without changing the hardware structure. This design greatly improves the versatility and flexibility of the filter, so that the same filter module can be applied to different scenarios, thereby reducing development time and cost.

[0006] In a first aspect, a method for parameterizing a filter based on an FPGA is applied to an FIR filter, wherein the FIR filter comprises at least an input port, a shift register module, a multiplication calculation module, and an output port, wherein the input port is respectively connected to the shift register module and the multiplication calculation module, and is used to input a filter signal and a filter coefficient into the shift register module and the multiplication calculation module, respectively, and the multiplication calculation module is connected to the output port, and is used to output a calculated filter result through the output port; The method comprises the steps of: S1: Acquire a plurality of filter coefficients, and generate a corresponding number of multipliers in the multiplication calculation module according to the number of the filter coefficients; S2: inputting the plurality of filter coefficients into the corresponding multipliers in sequence through the input ports; S3: The filter signal is connected to the shift register module through the input port, and the filter signal is sequentially input into the multiplier after multi-stage processing by the shift register module, so that the filter signal after each stage of processing is multiplied by the corresponding filter coefficient, and the product is weightedly calculated to obtain the filter data; S4: Output the filtered data through the output port.

[0007] The present application proposes a method based on FPGA parameterized filter, which dynamically generates a corresponding number of multipliers according to the number of filter coefficients, thereby realizing flexible configuration of the filter; the filter coefficients are sequentially input into the corresponding multipliers through the input port, so that the filter coefficients can be flexibly adjusted according to the demand; the filter signal is then processed in multiple stages using the shift register module, and the processed signal is sequentially input into the multiplier, thereby realizing the cascade structure of the filter, and the filtered signal after each stage of processing is multiplied with the corresponding filter coefficient at the same time, thereby improving the calculation efficiency, performing weighted calculation on the product result, obtaining the final filter data, and realizing the core function of the FIR filter. This method realizes the parameterized design of the FIR filter by dynamically configuring the number of multipliers (i.e., the filter order), the corresponding register storage, and the flexible input filter coefficients. It allows to adapt to different filtering requirements by adjusting the input parameters without changing the hardware structure. This design greatly improves the versatility and flexibility of the filter, so that the same filter module can be applied to different scenarios, thereby reducing development time and cost.

[0008] Furthermore, the input port at least includes a filter coefficient input terminal and a data shift input terminal, and the output port at least includes a data shift output terminal and a filter data output terminal. The filter coefficient input terminal is connected to the multiplication calculation module to input the filter coefficient into the corresponding multiplier; the data displacement input terminal is connected to the shift register module, and the shift register module is provided with multiple levels of chain-connected registers, each of the registers is connected to the corresponding multiplier through the data shift output terminal, and the multiplier is connected to the filter data output terminal.

[0009] The present application proposes a method for parameterized filter based on FPGA. The technical solution realizes the input, processing and output of filter coefficients and filtered signals by setting special input ports and output ports. The filter coefficient input terminal is connected to the multiplication calculation module, and the filter coefficient can be directly input into the corresponding multiplier, which improves the efficiency and accuracy of coefficient input. The data shift input terminal is connected to the shift register module, and the shift register module is provided with a multi-stage chain-connected register, which can perform multi-stage processing on the input filtered signal to realize the delay and shift operation of the signal. The present invention optimizes the traditional shift register module, uses parallel processing to process multiple data samples at the same time, further improves the processing speed, optimizes the pipeline design, reduces data transmission delay, and improves the acceptable clock frequency of the filter. Each register is connected to the corresponding multiplier through the data shift output terminal, ensuring that the filtered signal after each stage of processing can be multiplied with the corresponding filter coefficient. Through accurate multiplication operation, it is ensured that the filtered data output by the filter has a high signal-to-noise ratio and precision, thereby improving the signal processing quality. In addition, by utilizing the parallel processing capability of FPGA and deploying multiple multiplication calculation modules, multiple input samples and filter coefficients can be processed simultaneously, improving the processing speed and data throughput of the FIR filter. The multiplier is connected to the filter data output port to facilitate the output of the filtered data. This design structure makes the input, processing and output process of the filter coefficients and filtered signals clearer and more efficient, which is conducive to improving the performance and reliability of the FPGA parameterized filter. Through dedicated input and output ports and modular design, this solution improves the flexibility and configurability of the filter, enabling it to adapt to different filtering requirements.

[0010] Further, in step S2, the filter coefficients to The filter coefficients are sequentially input into the corresponding multipliers through the filter coefficient input terminals, wherein +1 indicates the number of filter coefficients, +1 of the filter coefficients.

[0011] This application proposes a method based on FPGA parameterized filter. This technical solution inputs the filter coefficients into the multiplier in an orderly, flexible, efficient and parallel manner, laying the foundation for subsequent filtering calculations and effectively solving the problem of filter coefficient input in FPGA parameterized filter. This method makes full use of the parallel processing capability of FPGA and improves the working efficiency and performance of the filter.

[0012] Furthermore, in step S3, the filtered signal The data shift input terminal is connected to the shift register module, and after being processed by multiple levels of registers, each level of register inputs the processed filtered signal to the corresponding multiplier through the data shift output terminal, multiplies it with the filter coefficient in the corresponding multiplier, and performs weighted sum calculation on the product result to obtain filtered data: ,in, is the number of stages of the filtered signal processed by the register, is the number of the multipliers, It is the filtered signal after being processed by the register at the last stage.

[0013] The present application proposes a method based on FPGA parameterized filter, which inputs the filter signal into a multi-stage register in sequence, multiplies it with the corresponding filter coefficient, and then performs weighted summation to finally obtain the filtered filter data. This method not only realizes the basic functions of the FIR filter, but also improves the flexibility and reusability of the system through parameterized design.

[0014] Further, in step S3, the multiplier is a Wallace tree multiplier.

[0015] Further, in step S3, the Wallace tree multiplier multiplies the filtered signal and the filter coefficient, and performs weighted sum calculation on the product, and the step of obtaining the filtered data includes: S31: performing a multiplication operation on each bit of the filter signal and the corresponding filter coefficient to generate a partial product; S32: compressing the partial products layer by layer through a full adder and a half adder, and repeating the compression process until only two layers of the partial products remain, and then using an adder to sum the remaining two layers of the partial products to obtain filtered data.

[0016] Furthermore, in step S1, a generate statement is used to repeatedly generate a corresponding number of multipliers.

[0017] In a second aspect, a device for parameterizing a filter based on an FPGA is provided, the device comprising: A generating module: used for obtaining a plurality of filter coefficients, and generating a corresponding number of multipliers in the multiplication calculation module according to the number of the filter coefficients; Input module: used for sequentially inputting the plurality of filter coefficients into the corresponding multipliers through the input port; Calculation module: used for filtering signals to be connected to the shift register module from the input port, and the filtered signals are sequentially input into the multiplier after being processed by the shift register module at multiple stages, so that the filtered signals after each stage of processing are multiplied by the corresponding filter coefficients, and the results of the multiplication are weightedly calculated to obtain filtered data; Output module: used to output the filtered data through an output port.

[0018] In a third aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method provided in the first aspect are performed.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, runs the steps in the method provided in the first aspect above.

[0020] Beneficial effects: The method, device, electronic device and storage medium based on FPGA parameterized filter proposed in this application dynamically generate a corresponding number of multipliers according to the number of filter coefficients, so as to realize flexible configuration of the filter; the filter coefficients are sequentially input into the corresponding multipliers through the input port, so that the filter coefficients can be flexibly adjusted according to the demand; the filter signal is processed in multiple stages by the shift register module, and the processed signal is sequentially input into the multiplier, so as to realize the cascade structure of the filter, and the filtered signal after each stage of processing is multiplied with the corresponding filter coefficient at the same time, so as to improve the calculation efficiency, and the product result is weighted to obtain the final filter data, so as to realize the core function of the FIR filter. This method realizes the parameterized design of the FIR filter by dynamically configuring the number of multipliers (i.e., the filter order), the corresponding register storage and the flexible input filter coefficient. It allows to adapt to different filtering requirements by adjusting the input parameters without changing the hardware structure. This design greatly improves the versatility and flexibility of the filter, so that the same filter module can be applied to different scenarios, thereby reducing development time and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a flowchart of a method for parameterizing a filter based on FPGA proposed in the present invention.

[0022] Figure 2 This is a schematic diagram of the structure of a device based on FPGA parameterized filter proposed in this application.

[0023] Figure 3 A schematic diagram of the structure of the electronic device provided in this application.

[0024] Figure 4 This is a schematic diagram of the structure of the FIR filter proposed in this application.

[0025] Figure 5 A schematic diagram of a shift operation performed by the shift register module proposed in this application.

[0026] Figure 6 This is a calculation diagram of the multiplication calculation module proposed in this application.

[0027] Description of reference numerals: 201, generation module; 202, input module; 203, calculation module; 204, output module; 3, electronic device; 301, processor; 302, memory; 303, communication bus. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application usually described and marked in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0029] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first, second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0030] The disclosure below provides many different implementations or examples for achieving the purpose of the present invention, which solves the problem in the prior art of exporting parameters through MATLAB and deploying using specific IP cores, where each parameter change requires reconfiguring the filter module, resulting in increased system complexity and development time costs.

[0031] Please refer to Figure 1, a method for parameterizing filters based on FPGA, applied to FIR filters, the FIR filters at least comprising an input port, a shift register module, a multiplication calculation module and an output port, the input port is respectively connected to the shift register module and the multiplication calculation module, and is used to input a filter signal and a filter coefficient into the shift register module and the multiplication calculation module, respectively, the multiplication calculation module is connected to the output port, and is used to output the calculated filter result through the output port; The method comprises the steps of: S1: obtaining a plurality of filter coefficients, and generating a corresponding number of multipliers in a multiplication calculation module according to the number of the filter coefficients; S2: Input multiple filter coefficients into corresponding multipliers in sequence through input ports; S3: The filter signal is connected to the shift register module from the input port. After the multi-stage processing of the shift register module, the filter signal is sequentially input into the multiplier, so that the filter signal after each stage of processing is multiplied by the corresponding filter coefficient, and the product of the product is weighted to obtain the filter data; S4: Output the filtered data through the output port.

[0032] Please refer to Figure 4In practical applications, the FIR filter in the present application at least includes an input port, a shift register module, a multiplication calculation module and an output port. The input port at least inputs: filter coefficients, the number of filter coefficients, a 16-bit wide filter signal (this is the filter signal to be filtered input by the FIR filter, with a width of 16 bits, and the width determines the resolution of the filter signal), a high effective signal input (referring to a control signal, used to indicate the validity of the filter coefficient), a system clock (referring to the clock signal that drives the entire filter system) and a reset signal input (this is a control signal, used to reset the state of the filter system to the initial state). The number of filter coefficients will affect the number of data at the filter input end. The data shift input end of the 16-bit wide filter signal is connected to the signal effective port and the signal source, and the clock is connected to the reset signal and the filter system. The shift register module is used to store and delay the input signal, realize the pipeline processing of the data, simplify the design and resource utilization, etc. In the present invention, the traditional shift register module is optimized, and parallel processing is used to process multiple data samples at the same time, further improve the processing speed, and optimize the pipeline design, reduce data transmission delay, and increase the acceptable clock frequency of the filter. The main function of the multiplication calculation module is to realize the weighted operation of the input filter signal and the filter coefficient, which is the core step of the FIR filter. Through precise multiplication operations, the filter data output by the filter is guaranteed to have a high signal-to-noise ratio and accuracy, thereby improving the quality of filter signal processing. In addition, by utilizing the parallel processing capability of FPGA, multiple multiplication calculation modules can be deployed, so that multiple input samples (filtered signals) and filter coefficients can be processed simultaneously, improving the processing speed and data throughput of the FIR filter. The main function of the output port is to adjust the bit width of the filter data generated by the multiplication calculation module to the required width. The output port also contains a signal valid flag to indicate whether the output filter is valid. This usually corresponds to the signal high valid input in the input port, ensuring that the output filter data is considered valid only when the input filter signal is valid.

[0033] Among them, in step S1, the method first obtains multiple filter coefficients, and dynamically generates a corresponding number of multipliers in the multiplication calculation module according to the number of coefficients. This realizes the dynamic configuration of the filter structure, so that the filter order can be flexibly adjusted according to demand. For example, for a 16-order FIR filter, the system will generate 16 multipliers.

[0034] Next, in step S2, the filter coefficients are sequentially input into the corresponding multipliers through the input ports. This parameterized input enables the same hardware structure to achieve different filtering characteristics and adapt to various environmental conditions. The filtered signal is processed in multiple stages through the shift register module to achieve the cascade structure of the filter. Each stage of processing corresponds to a filter coefficient, and filters of different orders can be achieved by adjusting the number of stages.

[0035] In step S3, during the multiplication calculation stage, the system fully utilizes the parallel processing capability of the FPGA. Taking a 16-order FIR filter as an example, 16 multiplication operations can be performed simultaneously, significantly improving the calculation efficiency. The multiplication results are then quickly weighted summed through the addition tree structure to obtain the final filtered data.

[0036] Finally, in step S4, the filtered data is output through the output port.

[0037] In practical applications, by dynamically generating multipliers, the filter system can easily adjust the order of the filter to adapt to different filtering requirements. For example, when a higher-order filter is needed in a noisy environment, the filter system will automatically generate more multipliers by simply increasing the number of filter coefficients. At the same time, the parameterized input of the filter coefficients allows the same hardware structure to achieve a variety of filtering characteristics, and can adapt to different application scenarios without modifying the hardware design.

[0038] Taking a 16-order FIR filter as an example, the filtering system first obtains 16 filter coefficients and dynamically generates 16 multipliers using a Wallace tree structure in the multiplication calculation module. The filter coefficients are input through the input port and can be optimized according to the actual channel characteristics. The filtered signal is processed through 16 levels of chain-connected registers to realize the delay line structure of the filter. In each clock cycle, 16 multipliers work simultaneously to multiply the current input sample (filtered signal) and its previous 15 historical samples (filtered signals) with the corresponding filter coefficients. This parallel processing greatly improves the computational efficiency. The multiplication results are then quickly weighted summed through the addition tree structure to obtain the final filtered data. The entire process is repeated in each clock cycle to achieve continuous real-time filtering.

[0039] Compared with the traditional method, the method of the present application achieves high flexibility through parameterized design and dynamic configuration. For example, when the filter needs to be adjusted from 16th order to 32nd order, only 32 filter coefficients need to be obtained, and the system will automatically generate 32 multipliers. Changing the filtering characteristics only requires entering new filter coefficients without modifying the hardware structure.

[0040] In addition, the method of the present application makes full use of the parallel processing capability of FPGA, significantly improving the processing speed of the filter by performing multiple multiplication operations simultaneously and using an efficient addition tree structure. This makes the method particularly suitable for high-speed digital communication systems and can meet strict real-time processing requirements.

[0041] Furthermore, the input port at least includes a filter coefficient input terminal and a data shift input terminal, and the output port at least includes a data shift output terminal and a filter data output terminal. The filter coefficient input terminal is connected to the multiplication calculation module to input the filter coefficient into the corresponding multiplier; the data displacement input terminal is connected to the shift register module, and the shift register module is provided with multiple levels of chain-connected registers, each register is connected to the corresponding multiplier through the data shift output terminal, and the multiplier is connected to the filter data output terminal.

[0042] Among them, in actual applications, the filter coefficient input terminal can be implemented in a variety of ways. One way is to use a serial interface, such as SPI or I2C, to input the filter coefficients one by one; another way is to use a parallel interface to input multiple filter coefficients at the same time. For high-speed applications, you can consider using a high-speed serial interface such as LVDS or PCIe. The data shift input terminal can be designed as a single-bit input or a multi-bit parallel input, and the appropriate bit width can be selected according to the actual application requirements.

[0043] There are also many possibilities for the design of the shift register module. You can use a simple D flip-flop chain or a more complex shift register IP core. To improve processing efficiency, you can insert pipeline registers between each register stage to achieve a higher clock frequency. In addition, you can also consider using a dual-port RAM to implement the shift register, which can read and write data simultaneously, further improving processing speed.

[0044] The multiplier can use the DSP module built into the FPGA to implement efficient multiplication operations, or it can use a lookup table (LUT) based multiplier design.

[0045] The filter data output can use FIFO buffering to smooth the output data flow, or use a double buffering mechanism to ensure continuous data output. For high-speed applications, consider using differential signal output, such as LVDS, to improve signal integrity.

[0046] These implementation methods and design choices are interrelated and together affect the performance of the entire filter. For example, high-speed data input requires matching efficient shift register modules and multiplier designs, while high-precision multipliers require corresponding high-bitwidth data output designs. Through reasonable combination and optimization, efficient, flexible and accurate FPGA parameterized filters can be achieved.

[0047] Further, in step S2, the filter coefficients to The coefficients are input into the corresponding multipliers in sequence through the filter coefficient input terminals, where +1 indicates the number of filter coefficients, +1 filter coefficient.

[0048] Among them, the technical solution uses the filter coefficient input terminal to to The input is sequentially input into the corresponding multiplier. This input method has the advantages of orderliness, flexibility, high efficiency and parallelism, which effectively solves the problem of filter coefficient input in FPGA parameterized filter, makes full use of the parallel processing capability of FPGA, and improves the working efficiency and performance of the filter.

[0049] In the specific implementation process, the input of the filter coefficient can use a multiplexer (MUX) and an address decoder. In this method, all filter coefficients are stored in a ROM or RAM, and a specific filter coefficient is selected by an address decoder, and then routed to the corresponding multiplier through a multiplexer. This method provides greater flexibility and allows the filter coefficients to be changed dynamically to adapt to different filtering requirements.

[0050] Further, in step S3, the filtered signal The data shift input terminal is connected to the shift register module, and after multi-level register processing, each level of register inputs the processed filtered signal to the corresponding multiplier through the data shift output terminal, multiplies it with the filter coefficient in the corresponding multiplier, and performs weighted sum calculation on the product result to obtain the filtered data: ,in, is the number of levels of filter signal processed by registers, is the number of multipliers, It is the filtered signal after being processed by the register at the last stage.

[0051] Please refer to Figure 5 , D represents the register, and the parallel 16-bit data represents the 16-bit filter signal; among them, the output of the shift register module is controlled by the clock signal. Figure 5In the example, the first cycle, the second cycle, ... ... the 16th cycle are clock signals. In each clock signal cycle, the data in the register will shift one position to the right. Since it is 16-bit data, 16 clock cycles are required to output all bits one by one. The shift register module processes the filter signal through a multi-stage register to realize signal delay and storage; the multiplier performs a product operation on the processed filter signal and the corresponding filter coefficient; the weighted sum calculation performs a weighted summation on the product result to obtain the final filter data. These technical features work together to realize the core function of the FIR filter. The shift register module ensures the correct delay and storage of the filter signal, the multiplier realizes the product operation of the signal and the coefficient, and the weighted sum calculation completes the generation of the final filter data. For example, in some specific implementations, for a 16-order FIR filter, a 16-stage shift register, 16 multipliers, and a 16-input addition tree can be set. The filter coefficient can be a 16-bit fixed-point number, and the filter signal can be a 16-bit fixed-point number. This configuration can effectively utilize FPGA resources while ensuring accuracy.

[0052] Further, in step S3, the multiplier is a Wallace tree multiplier.

[0053] Please refer to Figure 6 In practical applications, the Wallace tree multiplier is an efficient parallel multiplier structure. Using the Wallace tree multiplier in the multiplication calculation module of the FIR filter can improve the speed and efficiency of the multiplication operation. Specifically, the Wallace tree multiplier processes the partial products in parallel and uses full adders and half adders to compress the partial products, and finally only one addition operation is needed to obtain the final result. Compared with the traditional array multiplier, this structure can significantly reduce the number of adder stages, thereby reducing delay and improving the operation speed. In the FIR filter, a large number of multiplication operations are required to calculate the product of the filter signal and the filter coefficient. The use of the Wallace tree multiplier can speed up the speed of these multiplication operations and improve the processing efficiency of the entire filter. At the same time, the Wallace tree multiplier also has good area efficiency and is suitable for implementation in FPGA. By using the Wallace tree multiplier in the multiplication calculation module, the method of FPGA-based parameterized filter can effectively improve the filtering operation speed and reduce resource consumption while ensuring the calculation accuracy, thereby realizing efficient parameterized filtering.

[0054] There are many ways to implement the Wallaces tree multiplier. A common implementation method is to use a tree structure consisting of 3-2 compressors and full adders. In this structure, all partial products are first generated, and then the three-level partial products are compressed into two-level partial products using a 3-2 compressor. This process is repeated until only two levels of partial products are left. Finally, a full adder is used to add the remaining two levels of partial products to get the final result.

[0055] Another implementation method is to use a 4-2 compressor, which can further reduce the number of compression layers and increase the operation speed. The 4-2 compressor can compress four layers of input into two outputs, which can reduce the number of partial products faster than the 3-2 compressor. Although the efficiency of the 4-2 compressor is better than the 3-2 compressor, its internal logic structure is more complex, resulting in an increase in area. This is a way to increase performance at the cost of increasing area. Therefore, the 3-2 compressor mode is adopted in this application.

[0056] Furthermore, in step S3, the Wallace tree multiplier multiplies the filtered signal and the filter coefficient, and performs weighted sum calculation on the product, and the step of obtaining the filtered data includes: S31: performing a multiplication operation on each bit of the filtered signal and the corresponding filter coefficient to generate a partial product; S32: compressing the partial products layer by layer through full adders and half adders, and repeating the compression process until only two layers of partial products are left, and then using an adder to sum the remaining two layers of partial products to obtain filtered data.

[0057] Among them, in practical applications, in some specific implementations, it is assumed that there is an 8th order FIR filter, the filter coefficient is 16 bits, and the input signal (filtered signal) is 16 bits. First, 256 partial products (16x16) can be generated using an AND gate array. Then the 256 partial products are compressed into three layers using full adders and half adders. In the first layer of compression, partial integral groups with the same weight are processed. These partial products are compressed using full adders and half adders. The specific process is: three partial products with the same weight are input into the full adder, and a partial product with the same weight and a partial product with a higher weight are output; if only two partial products with the same weight are left, half adders are used for compression. This process is repeated until two layers of partial products are left. In the middle layer, the partial integral groups with the same weight continue to be processed, and the number of partial products is gradually reduced using full adders and half adders. For example, in the second layer, partial products with a weight of 8 continue to be input into the full adder, and partial products with a weight of 8 and a weight of 16 are output. In the last layer, the partial products compressed to only two numbers are input into a fast adder for final summation to obtain the multiplication result. The Wallace tree multiplier increases the speed of multiplication operations by processing partial products in parallel, and reduces the amount of data that needs to be processed through multiple layers of compression.

[0058] Furthermore, in step S1, a generate statement is used to repeatedly generate a corresponding number of multipliers.

[0059] Among them, by using the generate statement, the corresponding number of multipliers can be dynamically generated according to the number of filter coefficients, thereby realizing the parameterized design of the filter. This method realizes the flexible configuration of the filter structure by utilizing the programmable characteristics of FPGA and the generate statement function of Verilog HDL. Specifically, when the order or number of coefficients of the filter needs to be changed, only the parameters in the generate statement need to be modified to automatically generate the corresponding number of multipliers without manually modifying a large amount of repeated hardware description code. This not only improves the design efficiency, but also enhances the scalability and maintainability of the filter.

[0060] Please refer to Figure 2 , a device based on FPGA parameterized filter, the device comprising: Generating module 201: used to obtain multiple filter coefficients, and generate a corresponding number of multipliers in the multiplication calculation module according to the number of filter coefficients; Input module 202: used to input multiple filter coefficients into corresponding multipliers in sequence through input ports; Calculation module 203: used for filtering signals to be connected to the shift register module from the input port, and the filtered signals are sequentially input into the multiplier after being processed by the shift register module at multiple stages, so that the filtered signals after each stage of processing are multiplied by the corresponding filter coefficients, and the product of the products is weightedly calculated to obtain the filtered data; Output module 204: used to output the filtered data through an output port.

[0061] The device realizes a flexible FIR filter through modular design. The generation module 201 dynamically generates multipliers according to the number of filter coefficients, so that the filter can adapt to coefficients of different lengths. The input module 202 ensures that the filter coefficients are correctly input into the corresponding multipliers. The calculation module 203 realizes the core function of FIR filtering by shift register and multiplication operation, and obtains the filtering result through multi-stage processing and multiplication accumulation. Finally, the output module 204 outputs the processed data.

[0062] The generation module 201 can dynamically generate a corresponding number of multipliers according to the number of filter coefficients input. This design can be implemented through the programmable characteristics of the FPGA, for example, using a generate statement to repeatedly generate multiplier instances. The generation module 201 can support different numbers of filter coefficients, ranging from 8 to 128, so that the filter can adapt to different application requirements.

[0063] The input module 202 is responsible for inputting the filter coefficients into the corresponding multipliers. It can input the coefficients in serial or parallel mode. In the serial input mode, a shift register can be used to input the coefficients into each multiplier in turn; in the parallel input mode, a multiplexer can be used to simultaneously input multiple coefficients into the corresponding multipliers. The calculation module 203 is the core processing unit of the filter. It first performs multi-stage processing on the input filter signal through the shift register module. The shift register module can adopt a chain structure, and the output of each register is connected to the input of the next register to form a delay line. The processed filter signal is input into the multiplier in turn and multiplied with the corresponding filter coefficient. The multiplier can adopt an efficient Wallace tree multiplier to increase the calculation speed. Finally, all the product results are weighted summed to obtain the filter data. The weighted summation can be implemented using an addition tree with a pipeline structure to improve the processing efficiency.

[0064] The output module 204 is responsible for outputting the calculated filtered data through the output port. It can select different output modes as needed, such as serial output or parallel output. In some applications, data format conversion or caching functions can also be added to the output module 204 to adapt to different subsequent processing requirements.

[0065] This modular design makes the responsibilities of each functional unit clear, and is easy to implement and maintain. The collaborative work of the generation module 201 and the calculation module 203 enables the filter to flexibly adjust its structure according to different filter coefficients, thereby adapting to different filtering requirements. For example, when a high-order filter is needed, the number of filter coefficients can be increased, and the generation module 201 will generate more multipliers accordingly, while the calculation module 203 can process longer data sequences and realize more complex filtering functions.

[0066] Figure 3 The present invention provides a structural schematic diagram of an electronic device provided in an embodiment of the present application. The present application provides an electronic device 3, including: a processor 301 and a memory 302. The processor 301 and the memory 302 are interconnected and communicate with each other through a communication bus 303 and / or other forms of connection mechanisms (not shown). The memory 302 stores computer-readable instructions executable by the processor 301. When the electronic device is running, the processor 301 executes the computer-readable instructions to execute the method in any optional implementation of the above embodiment to achieve the following functions: obtaining multiple filter coefficients, generating a corresponding number of multipliers in a multiplication calculation module according to the number of filter coefficients; inputting the multiple filter coefficients into the corresponding multipliers in sequence through the input port; the filter signal is connected to the shift register module from the input port, and the filter signal is sequentially input into the multiplier after multi-stage processing of the shift register module, so that the filter signal after each stage of processing is multiplied with the corresponding filter coefficient, and the product is weightedly calculated to obtain filter data; and the filter data is output through the output port.

[0067] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method in any optional implementation of the above embodiment is executed to achieve the following functions: obtaining multiple filter coefficients, and generating a corresponding number of multipliers in a multiplication calculation module according to the number of filter coefficients; inputting the multiple filter coefficients into the corresponding multipliers in sequence through an input port; connecting a filter signal to a shift register module through the input port, and inputting the filter signal into the multiplier in sequence after multi-stage processing by the shift register module, so that the filter signal after each stage of processing is multiplied by the corresponding filter coefficient, and the product is weightedly calculated to obtain filter data; and outputting the filter data through an output port.

[0068] Among them, the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable red-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0069] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0070] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0071] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0072] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0073] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for parameterizing a filter based on FPGA, characterized in that: Applied to an FIR filter, the FIR filter at least comprises an input port, a shift register module, a multiplication calculation module and an output port, the input port is respectively connected to the shift register module and the multiplication calculation module, and is used to input a filter signal and a filter coefficient into the shift register module and the multiplication calculation module, respectively, and the multiplication calculation module is connected to the output port, and is used to output a calculated filter result through the output port; The method comprises the steps of: S1: Acquire a plurality of filter coefficients, and generate a corresponding number of multipliers in the multiplication calculation module according to the number of the filter coefficients; S2: inputting the plurality of filter coefficients into the corresponding multipliers in sequence through the input ports; S3: The filter signal is connected to the shift register module through the input port, and the filter signal is sequentially input into the multiplier after multi-stage processing by the shift register module, so that the filter signal after each stage of processing is multiplied by the corresponding filter coefficient, and the product is weightedly calculated to obtain the filter data; S4: Output the filtered data through the output port.

2. The method for parameterizing a filter based on FPGA according to claim 1, characterized in that: The input port at least includes a filter coefficient input terminal and a data shift input terminal, and the output port at least includes a data shift output terminal and a filter data output terminal. The filter coefficient input terminal is connected to the multiplication calculation module and is used to input the filter coefficient into the corresponding multiplier; the data displacement input terminal is connected to the shift register module, and the shift register module is provided with multiple levels of chain-connected registers, each of the registers is connected to the corresponding multiplier through the data shift output terminal, and the multiplier is connected to the filter data output terminal.

3. The method for parameterizing a filter based on FPGA according to claim 2, characterized in that: In step S2, the filter coefficients to The filter coefficients are sequentially input into the corresponding multipliers through the filter coefficient input terminals, wherein +1 indicates the number of filter coefficients, +1 of the filter coefficients.

4. The method for parameterizing a filter based on FPGA according to claim 3, characterized in that: In step S3, the filtered signal The data shift input terminal is connected to the shift register module, and after multiple levels of register processing, each level of register inputs the processed filtered signal to the corresponding multiplier through the data shift output terminal, multiplies it with the filter coefficient in the corresponding multiplier, and performs weighted sum calculation on the product result to obtain the filtered data. ,in, is the number of stages of the filtered signal processed by the register, is the number of the multipliers, It is the filtered signal after being processed by the register at the last stage.

5. The method for parameterizing a filter based on FPGA according to claim 4, characterized in that: In step S3, the multiplier is a Wallace tree multiplier.

6. The method for parameterizing a filter based on FPGA according to claim 5, characterized in that: In step S3, the Wallace tree multiplier multiplies the filtered signal and the filter coefficient, and performs weighted sum calculation on the product, and the step of obtaining the filtered data includes: S31: performing a multiplication operation on each bit of the filter signal and the corresponding filter coefficient to generate a partial product; S32: compressing the partial products layer by layer through a full adder and a half adder, and repeating the compression process until only two layers of the partial products remain, and then using an adder to sum the remaining two layers of the partial products to obtain filtered data.

7. The method for parameterizing a filter based on FPGA according to claim 1, characterized in that: In step S1, a generate statement is used to repeatedly generate a corresponding number of multipliers.

8. A device based on FPGA parameterized filter, characterized in that: The device comprises: A generation module: used for obtaining a plurality of filter coefficients, and generating a corresponding number of multipliers in a multiplication calculation module according to the number of the filter coefficients; Input module: used for sequentially inputting the plurality of filter coefficients into the corresponding multipliers through input ports; Calculation module: used for filtering signals to be connected to the shift register module from the input port, and the filtered signals are sequentially input into the multiplier after being processed by the shift register module at multiple stages, so that the filtered signals after each stage of processing are multiplied by the corresponding filter coefficients, and the product is weightedly calculated to obtain the filtered data; Output module: used to output the filtered data through an output port.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the steps in the method according to any one of claims 1 to 7 are executed.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are executed.

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