Linear Hall chip with anti-backflow function and control method

Abstract

The invention discloses a linear Hall chip with an anti-backflow function and a control method, the linear Hall chip comprises a secondary operational amplifier arranged in the linear Hall chip, an anti-backflow circuit is arranged in a Hall output end, and the anti-backflow circuit comprises an anti-backflow processor. The anti-backflow processor comprises a first input end, a second input end, a load tube, a first output end and a second output end, the first input end is connected with a Hall output end VOUT, the second input end is connected with a power supply end VDD, two paths of input are respectively connected with the load tube for adjusting trigger voltage difference after passing through a current-limiting resistor, and the first output end is connected with the first output end. The first output end is connected with the second output end through a switching device, the second output end is connected with the secondary operational amplifier through a switching tube, and the secondary operational amplifier is further connected with the first input end of the anti-backflow processor through the switching tube; the beneficial effects are that the output end is protected by arranging the anti-backflow circuit in the Hall output end, and external electric signals are prevented from flowing backwards.

Description

Technical Field

[0001] The present invention relates to the technical field of Hall chips, and in particular to a linear Hall chip with a backflow prevention function and a control method thereof. Background Art

[0002] The Hall chip is a chip used to detect magnetic fields and works based on the Hall effect. The output signal level of the full-range linear Hall effect sensor is determined by the strength of the magnetic field applied to the sensitive part and changes proportionally with the strength of the magnetic field.

[0003] At present, linear Hall sensors generally use a row-column scanning method when working in a magnetic axis keyboard. The main control chip receives the output signals of the Hall sensors row by row in the layout order within a certain period of time, and then scans the next row until the full keyboard key signal is received to form a signal receiving cycle. In this way, fast key response can be achieved. However, since the output ports of the Hall sensors in the same row work in parallel, the output ports of the Hall sensor chips in the same row will be affected by the outputs of other Hall sensor units in parallel with them. The output current of the chip that is working will flow back into other chips that are not working, causing them to generate a reverse input voltage to pull up the chip power supply, causing the working state of the sensor to be confused, thereby causing it to enter an incorrect working state.

[0004] Although some anti-backflow solutions have emerged, the existing anti-backflow processing on magnetic axis keyboards is generally divided into two types; one is to connect a diode in series to the output port of each Hall sensor, and then process the output signal in parallel, which is very expensive and the output voltage value will reduce the voltage difference of the conduction voltage of a diode; the other is to connect the output of the Hall sensor in parallel to a multi-select analog switch, and select the key signal output by controlling the on and off of the switch, but this will also increase the cost and increase the computing pressure of the main control chip. Summary of the invention

[0005] In view of the defects in the prior art, the present invention provides a linear Hall chip with anti-backflow function and a control method to prevent the backflow of external electrical signals.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] In a first aspect, a linear Hall chip with anti-backflow function and a control method are applied to a Hall sensor, including a secondary operational amplifier deployed in the linear Hall chip, wherein the linear Hall chip has a built-in anti-backflow circuit at the Hall output end, the anti-backflow circuit includes an anti-backflow processor, and the anti-backflow processor includes a first input end, a second input end, a load tube, a first output end, and a second output end, wherein the first input end is connected to the Hall output end VOUT of the linear Hall chip, the second input end is connected to the power supply end VDD of the linear Hall chip, the two inputs are connected to the load tube for adjusting the trigger voltage difference after passing through a current limiting resistor, the first output end is connected to the second output end through a switch device, the second output end is connected to the secondary operational amplifier through a switch tube, and the secondary operational amplifier is also connected to the first input end of the anti-backflow processor through the switch tube.

[0008] Preferably, the switch device is a PMOS tube, a substrate of the PMOS tube is connected to the second output end, and an output signal of the second output end is used to control the power input of the switch tube.

[0009] Preferably, the anti-backflow processor is configured to determine whether anti-backflow protection is required based on a voltage relationship between the Hall output terminal voltage VOUT and the power supply terminal VDD.

[0010] Preferably, the control signal output from the first output terminal also outputs a synchronous control signal with opposite polarity to the control signal through an inverter, and transmits it to the control terminal of the previous stage signal transmission switch for controlling the input path of the secondary operational amplifier.

[0011] Preferably, the secondary operational amplifier includes a secondary output amplifier, and the secondary output amplifier is connected to the switch tube and the first input end respectively.

[0012] Preferably, a sensitivity analog switch is further disposed in the linear Hall chip, the anti-backflow circuit is further connected to the sensitivity analog switch, and the sensitivity analog switch is further connected to the secondary operational amplifier.

[0013] In a second aspect, a control method of a linear Hall chip is provided, characterized in that it is applied to the linear Hall chip with anti-backflow function described in the first aspect, and the control method comprises:

[0014] Acquire a first input signal; wherein the first signal comprises a Hall output signal;

[0015] Compare the first signal with a preset reference signal, determine whether backflow protection is required based on the obtained voltage relationship, and output a corresponding switch control signal; wherein the reference signal includes a power supply terminal VDD;

[0016] If so, the control switch of the secondary op amp output is turned off to block the previous stage signal path and prevent the Hall output terminal from driving the power supply terminal to generate working voltage;

[0017] If not, turn on the control switch of the secondary op amp output, open the previous signal path, and enable the chip to work normally.

[0018] Preferably, the method further comprises:

[0019] The input path of the second-stage operational amplifier is controlled based on the switch control signal corresponding to the output.

[0020] Preferably, the method further comprises:

[0021] A sensitivity analog switch is deployed in the linear Hall chip, and the sensitivity analog switch is connected to the secondary operational amplifier to achieve sensitivity adjustment.

[0022] The beneficial effects of the present invention are as follows: by building an anti-backflow circuit into the Hall output end to protect the output end and prevent the backflow of external electrical signals, and by using a PMOS tube device as the switch device for controlling the output of the secondary operational amplifier, no conduction voltage drop will be generated when turned on, and the voltage output height of the chip during normal operation will not be affected, thereby achieving non-voltage difference anti-backflow protection, thereby preventing the voltage and current at the chip output port from backflowing back to the chip and entering an erroneous working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0024] Figure 1 A circuit schematic diagram of an anti-backflow circuit of a linear Hall chip with an anti-backflow function provided in an embodiment of the present invention;

[0025] Figure 2 An internal structural block diagram of a linear Hall chip with anti-backflow function provided by an embodiment of the present invention;

[0026] Figure 3 The present invention provides a flowchart of a method for controlling a linear Hall chip. DETAILED DESCRIPTION

[0027] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0028] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0029] like Figure 1 , Figure 2 As shown, a linear Hall chip with anti-backflow function is applied to a Hall sensor, including a secondary operational amplifier deployed in the linear Hall chip, the linear Hall chip has a built-in anti-backflow circuit at the Hall output end, the anti-backflow circuit includes an anti-backflow processor, the anti-backflow processor includes a first input end, a second input end, a load tube, a first output end, and a second output end, the first input end is connected to the Hall output end VOUT of the linear Hall chip, the second input end is connected to the power supply end VDD of the linear Hall chip, the two inputs are connected to the load tube for adjusting the trigger voltage difference after passing through a current limiting resistor, the first output end is connected to the second output end through a switch device, the second output end is connected to the secondary operational amplifier through a switch tube, and the secondary operational amplifier is also connected to the first input end of the anti-backflow processor through the switch tube.

[0030] In this embodiment, the two-stage operational amplifier includes a two-stage output amplifier, and the two-stage output amplifier is connected to the switch tube and the first input end respectively.

[0031] The switching device adopts a PMOS tube, the substrate of the PMOS tube is connected to the second output terminal, and the output signal of the second output terminal is used to control the power input of the switching tube; wherein the output voltage value of the output signal is equal to the voltage of the power terminal VDD.

[0032] It is important to note that the substrate of the switch tube [P1] PMOS cannot be connected to the power supply VDD like the source, but must be connected to the drain terminal V_ch. This is a key step in preventing backflow.

[0033] This is because for the general circuit connection structure, the substrate end of a PMOS tube must be connected to the highest potential in the chip, that is, the power supply potential VDD, in order to work normally; however, in this solution, the anti-backflow effect is required, and the substrate end of the PMOS tube can only be connected to the low potential end, that is, V_ch, otherwise the structure of the PMOS tube will have a constant conduction state and cannot achieve the anti-backflow effect.

[0034] The control signal output from the first output terminal also outputs a synchronous control signal with a polarity opposite to that of the control signal through an inverter, and is transmitted to the control terminal of the previous stage signal transmission switch, which is used to control the input path of the secondary operational amplifier and to turn on or off the input signal of the secondary operational amplifier.

[0035] It should be noted that the linear Hall chip of this embodiment also includes an existing clock circuit, a logic circuit, a bias source circuit, a reference source circuit, etc., which should be well known to those skilled in the art and will not be described in detail here;

[0036] The anti-backflow circuit is Figure 1 The structure of the dotted frame portion is removed; the dotted frame is a portion of the secondary operational amplifier; the switch device is Figure 1 In P1, the switch tube is Figure 1 P2 in Figure 2 The output amplifier in is the secondary output amplifier;

[0037] The input signal is Figure 2 In the embodiment, the front stage signal is transmitted through the Hall plate, the Hall voltage amplifier and the offset circuit; the front stage signal transmission switch and Figure 2 The transfer switches in have the same meaning.

[0038] In this embodiment, the control signal output by the first output terminal is represented by P_g in the accompanying drawings, and the synchronous control signal with opposite polarity is represented by N_g; the output signal of the second output terminal is represented by V_ch in the accompanying drawings, and the V_ch signal is also an output signal, and the output voltage value is equal to the power supply voltage VDD, but is controlled by the control of the switching device to turn on or off; it is used to control the remaining circuits that are directly connected to the VOUT output port, and V_ch needs to be used instead of the power supply voltage interface VDD.

[0039] In this embodiment, the anti-backflow processor is configured to determine whether anti-backflow protection is required based on the voltage relationship between the Hall output terminal voltage VOUT and the power supply terminal VDD.

[0040] To better understand this solution, its working process is as follows:

[0041] When the voltage VOUT of the Hall output terminal is greater than the power supply voltage VDD, it is considered that anti-backflow protection is required at this time, and the output P_g is high level, turning off the secondary op amp output control switch PMOS[P1], blocking the previous stage signal path; thereby preventing the Hall output terminal from driving the power supply terminal to generate a working voltage;

[0042] When the voltage VOUT at the Hall output terminal is lower than the power supply voltage VDD, the Hall sensor works normally without the need for backflow protection, and outputs P_g low level, turning on the secondary op amp output control switch PMOS[P1], turning on the previous stage signal path, and allowing the chip to work normally.

[0043] Since the output control switch of the secondary op amp is a PMOS tube device, no conduction voltage drop will be generated when it is turned on, so it will not affect the voltage output level when the chip is working normally.

[0044] The above technical solution protects the output end by building an anti-backflow circuit into the Hall output end to prevent the backflow of external electrical signals, and uses a PMOS tube device to control the output of the secondary operational amplifier. When it is turned on, no conduction voltage drop will be generated, and the voltage output level of the chip will not be affected during normal operation, thereby achieving no-voltage difference anti-backflow protection, thereby preventing the voltage and current at the chip output port from flowing back into the chip and entering an erroneous working state; at the same time, since the Hall sensor has its own anti-backflow function, it can reduce the circuit cost of the magnetic axis keyboard solution for anti-backflow processing, reduce material costs, alleviate the calculation and output pressure of the keyboard main control chip, and effectively reduce the solution cost.

[0045] Further, in another embodiment, based on the above technical solution, referring to Figure 2 A sensitivity analog switch is also deployed in the linear Hall chip, the anti-backflow circuit is also connected to the sensitivity analog switch, and the sensitivity analog switch is also connected to the secondary operational amplifier.

[0046] During implementation, an adjustment device is also connected between the sensitivity analog switch and the secondary operational amplifier to perform sensitivity adjustment; the adjustment device uses an adjustable resistor, and the sensitivity analog switch is a multi-bit sensitivity analog switch; through the implementation of the above scheme, on the basis of realizing the anti-backflow function, sensitivity adjustment can also be performed.

[0047] Reference Figure 3 , a control method of a linear Hall chip is also provided, which is applied to the linear Hall chip with anti-backflow function mentioned above, and the control method includes:

[0048] S101, obtaining a first input signal; wherein the first signal includes a Hall output signal;

[0049] S102, comparing the first signal with a preset reference signal, judging whether backflow protection is required based on the obtained voltage relationship, and outputting a corresponding switch control signal; wherein the reference signal includes a power supply terminal VDD;

[0050] S103, if yes, turn off the control switch of the secondary operational amplifier output to block the previous stage signal path and prevent the Hall output terminal from driving the power supply terminal to generate a working voltage;

[0051] S104, if not, turn on the control switch of the secondary operational amplifier output, open the previous stage signal path, and enable the chip to work normally.

[0052] In this embodiment, anti-backflow protection is performed, and the switch control signal is the output P_g high level in the foregoing text; if anti-backflow protection is not required, the switch control signal is the output P_g low level in the foregoing text; that is, based on the obtained voltage relationship, the level state of the switch control signal is controlled.

[0053] When implemented, the method further includes:

[0054] The input path of the second-stage operational amplifier is controlled based on the switch control signal corresponding to the output.

[0055] In another embodiment, the method further comprises:

[0056] A sensitivity analog switch is deployed in the linear Hall chip, and the sensitivity analog switch is connected to the secondary operational amplifier to achieve sensitivity adjustment.

[0057] It should be noted that the above method steps can be executed by the anti-backflow circuit and / or the anti-backflow processor;

[0058] The control switch is the switch device described above; the switch device adopts a PMOS tube. Since the control switch of the secondary operational amplifier output is a PMOS tube device, no conduction voltage drop will be generated when it is turned on, thereby not affecting the voltage output height when the chip is working normally.

[0059] For a more specific description of the workflow of the method embodiment, please refer to the description of the aforementioned linear Hall chip embodiment, which will not be repeated here.

[0060] The above technical solution can protect the output end and prevent the external electrical signal from flowing back; and the switch device for controlling the output of the secondary operational amplifier is a PMOS tube device, which will not produce a conduction voltage drop when turned on, and will not affect the voltage output level of the chip when it works normally, thereby realizing non-voltage difference anti-backflow protection;

[0061] At the same time, due to the anti-backflow function, it can reduce the circuit cost of the magnetic axis keyboard whole machine solution used for anti-backflow processing, and optimize the multi-select analog switch chip and anti-backflow diode chip required by the existing solution, thereby reducing material costs and alleviating the computing pressure of the main control chip.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

[0063] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0064] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product.

Claims

1. A linear Hall chip with anti-backflow function, applied to a Hall sensor, comprising a secondary operational amplifier deployed in the linear Hall chip, characterized in that: The linear Hall chip has a built-in anti-backflow circuit at the Hall output end, and the anti-backflow circuit includes an anti-backflow processor. The anti-backflow processor includes a first input end, a second input end, a load tube, a first output end, and a second output end. The first input end is connected to the Hall output end VOUT of the linear Hall chip, and the second input end is connected to the power supply end VDD of the linear Hall chip. The two inputs are connected to the load tube for adjusting the trigger voltage difference after passing through a current limiting resistor. The first output end is connected to the second output end through a switch device, and the second output end is connected to the secondary operational amplifier through a switch tube. The secondary operational amplifier is also connected to the first input end of the anti-backflow processor through the switch tube.

2. A linear Hall chip with anti-backflow function according to claim 1, characterized in that: The switch device is a PMOS tube, the substrate of the PMOS tube is connected to the second output end, and the output signal of the second output end is used to control the power input of the switch tube.

3. A linear Hall chip with anti-backflow function and control method according to claim 2, characterized in that: The anti-backflow processor is configured to determine whether anti-backflow protection is required based on a voltage relationship between the Hall output terminal voltage VOUT and the power supply terminal VDD.

4. A linear Hall chip with anti-backflow function according to claim 3, characterized in that: The control signal outputted from the first output terminal also outputs a synchronous control signal with opposite polarity to the control signal through an inverter, and transmits it to the control terminal of the preceding signal transmission switch for controlling the input path of the secondary operational amplifier.

5. A linear Hall chip with anti-backflow function according to claim 4, characterized in that: The two-stage operational amplifier includes a two-stage output amplifier, and the two-stage output amplifier is connected to the switch tube and the first input end respectively.

6. A linear Hall chip with anti-backflow function according to claims 1 to 5, characterized in that: A sensitivity analog switch is also disposed in the linear Hall chip, the anti-backflow circuit is also connected to the sensitivity analog switch, and the sensitivity analog switch is also connected to the secondary operational amplifier.

7. A control method for a linear Hall chip, characterized in that: The linear Hall chip with anti-backflow function applied to claim 6, wherein the control method comprises: Acquire a first input signal; wherein the first signal comprises a Hall output signal; Compare the first signal with a preset reference signal, determine whether backflow protection is required based on the obtained voltage relationship, and output a corresponding switch control signal; wherein the reference signal includes a power supply terminal VDD; If so, the control switch of the secondary op amp output is turned off to block the previous stage signal path and prevent the Hall output terminal from driving the power supply terminal to generate working voltage; If not, turn on the control switch of the secondary op amp output, open the previous signal path, and enable the chip to work normally.

8. The control method of a linear Hall chip according to claim 7, characterized in that: The method further comprises: The input path of the second-stage operational amplifier is controlled based on the switch control signal corresponding to the output.

9. A control method for a linear Hall chip according to claim 7 or 8, characterized in that: The method further comprises: A sensitivity analog switch is deployed in the linear Hall chip, and the sensitivity analog switch is connected to the secondary operational amplifier to achieve sensitivity adjustment.

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