General parallel CRC generation and verification method capable of being flexibly configured

Abstract

The invention belongs to the field of reliable coding and decoding, and relates to a software and hardware combined universal parallel CRC (cyclic redundancy check) generation and verification method capable of being flexibly configured. Two modes of CRC generation and CRC check are supported, the CRC initial value can be configured to be all 0 / all 1, the degree of parallelism of CRC generation and check can be configured, any generator polynomial can be configured, and the length of generated CRC can be configured. According to the method provided by the invention, traditional serial CRC calculation can be changed into parallel CRC calculation, parameters can be flexibly configured, compared with serial calculation, time consumption can be reduced, limitation caused by fixed parameters is avoided, and the overall working efficiency of a system is greatly improved.

Description

Technical Field

[0001] The invention belongs to the field of reliability coding and decoding, and relates to a flexible and configurable universal parallel CRC generation and verification method combining software and hardware. Background Art

[0002] Cyclic redundancy check (CRC) is a verification algorithm widely used in the communication field. After the verification code is calculated and generated by the generation algorithm, it is added after the data bit to be transmitted and sent. At the receiving end, the data error can be detected and verified, providing verification capability for the entire communication process, which can greatly improve the reliability of system data transmission.

[0003] Traditional CRC coding is serial data coding, that is, only one data bit is input in each cycle and entered into the circuit for calculation. Usually, a linear feedback shift register is used for serial coding calculation. This method is still usable when processing small amounts of data, but in the process of gradual development of communications, various problems such as long time consumption and high resource consumption have been highlighted.

[0004] In response to the above problems, CRC encoding of parallel data came into being. This method can input multiple bits of data at the same time in each cycle. For example, if 8 bits of data are input per cycle, the computational efficiency of 8 degrees of parallelism can be achieved. The parameter of parallelism is the number of data bits that the method calculates simultaneously per cycle. Compared with the traditional CRC encoding of serial data, the CRC encoding of parallel data is more efficient, but correspondingly, the computational complexity of the method will also increase.

[0005] The CRC encoding of parallel data is usually performed by table lookup, that is, a table is calculated in advance, which stores the CRC of the required data, and the CRC to be calculated is obtained by table lookup. The disadvantage of this method is obvious. Different sizes of tables need to be made according to different sizes of data. For example, when 32-bit data is calculated with 8 degrees of parallelism, the size of the table is 2 32 Bytes, for longer data streams and greater parallelism, the table will take up too much storage space. At the same time, the method has very fixed requirements for parallelism. Each data stream and each parallelism needs to re-create the corresponding table, which cannot be flexibly configured and is inefficient. There are other methods for CRC encoding of parallel data, such as calculating multiple serial data CRC codes at the same time to complete parallel encoding, or converting the encoding process into matrix multiplication operations for encoding. These methods usually have the disadvantages of excessive resource usage, high computational complexity, and long time consumption. They can usually only support one or several fixed parallelism requirements and have low flexibility. Summary of the invention

[0006] In view of the defects in the prior art, the purpose of the present invention is to provide a flexible and configurable general parallel CRC generation and verification method, support CRC generation and CRC verification two modes, configurable CRC initial value is all 0 / all 1, configurable CRC generation and verification parallelism, configurable arbitrary generator polynomial, configurable CRC generation length. According to the method provided by the present invention, the traditional serial CRC calculation can be converted into a parallel CRC calculation, and the parameters can be flexibly configured, which can reduce the time consumption compared to the serial calculation, avoid the limitations brought by the fixed parameters, and greatly improve the overall working efficiency of the system.

[0007] The technical solution adopted by the present invention is:

[0008] A flexibly configurable universal parallel CRC generation and verification method comprises the following steps:

[0009] Step 1: Information codeword initial value processing:

[0010] Suppose the information codeword before encoding is [m'0,m'1,…,m' l-1 ]; When the CRC initial value is required to be all 0, execute step 2; When the CRC initial value is required to be all 1, perform XOR processing on the first crc_len number of information codewords and 1, where crc_len is the length of the generated CRC;

[0011] Step 2: Information codeword parallel processing:

[0012] When the codeword length l is divisible by the parallelism P, execute step 3; when the codeword length l is not divisible by the parallelism P, perform data zero padding, that is, pad 0 in front of the information codeword until the length is a multiple of P, and the information codeword is [0,0,…,0,m'0,m'1,…,m' l-1 ], let the information codeword after zero padding be [m0,m1,…m k-1 ],in

[0013] Step 3: Calculate the parameters:

[0014] make The information codeword [m0,m1,…m k-1 ] is divided into M'0=[m0,m1,…m P-1 ]、M'1=[m P ,m P+1 ,…m 2*P-1 ]…M' C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ] A total of C vectors;

[0015] When the parallelism P≤crc_len,

[0016] Remainder polynomial b(0) = [0,…,0] T , length is crc_len;

[0017] F=F' P , is a matrix of size crc_len×crc_len;

[0018] According to the matrix calculation rules, M'0 to M' C-1 The end of the vector is filled with 0 until the length of the vector is crc_len, and then transposed to get M0 to M C-1 :

[0019] M0=[m0,m1,…m P-1 ,0,…,0] T

[0020] M1=[m P ,m P+1 ,…m 2*P-1 ,0,…,0] T

[0021] …

[0022] M C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ,0,…,0] T

[0023] When the parallelism P ≥ crc_len,

[0024] Remainder polynomial b(0) = [0,…,0] T , length is P;

[0025] The F matrix is ​​a P×P matrix. P Expand on this basis and fill the first crc_len rows of the F matrix into F' in order by crc_len columns. P-i×crc_len ,in If P is an integer multiple of crc_len, F' P-i×crc_len The matrix is ​​directly filled in order; otherwise, the extra columns in the last F' are discarded when filling in;

[0026] According to the matrix calculation rules, M'0 to M' C-1 The end of the vector is filled with 0 until the length of the vector is P, and then transposed to get M0 to M C-1 :

[0027] M0=[m0,m1,…m P-1 ,0,…,0] T

[0028] M1=[m P ,m P+1 ,…m 2*P-1 ,0,…,0] T

[0029] …

[0030] M C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ,0,…,0] T ;

[0031] in, g0,g1,…,g n-k-1 are the coefficients of the generating polynomial g(x);

[0032] Step 4: Calculate CRC:

[0033] Calculate step by step according to the following formula:

[0034] b(0+P)=F×[b(0)+M0]

[0035] b(1+P)=F×[b(P)+M1]

[0036] b(2+P)=F×[b(1+P)+M2]

[0037] …

[0038] b(N+P)=F×[b(N+P-1)+N N ]

[0039] …

[0040] b(C-1+P)=F×[b((C-2)+P)+M C-1 ]

[0041] When the parallelism P≤crc_len, take b(C-1+P) as the register result b;

[0042] When the parallelism P ≥ crc_len, take the first crc_len number of b(C-1+P) as the register result b;

[0043] If configured as CRC generation mode, the register result is the CRC check code b; if configured as CRC check mode, it is determined whether the CRC check code b is all zeros. If it is all zeros, the check is successful, and if it is not all zeros, the check fails.

[0044] The advantages of the present invention compared with the prior art are:

[0045] (1) Greatly reduce computing time

[0046] The present invention converts traditional serial CRC calculation into parallel CRC calculation. The input data is not encoded one by one in series, but encoded in batches with the number of parallelism as the unit. Compared with serial, parallel processing reduces the calculation time by almost multiples.

[0047] (2) Multiple parameters can be flexibly configured to adapt to different scenarios and are highly robust

[0048] Different from the traditional CRC generator which can only perform certain specific CRC initial values, parallelism, fixed generating polynomials and CRC lengths, the present invention can configure two modes, CRC generation and CRC verification, according to different scenario requirements, configure different parallelism, CRC lengths and arbitrary generating polynomials, and support the CRC register initial value to be all 0 or all 1, with high flexibility and better robustness.

[0049] (3) Combining software and hardware to improve work efficiency

[0050] Considering that the calculation of the F matrix of the parallel CRC requires multi-level combinational logic feedback, which will lead to a large gate delay, the present invention uses a method combining software and hardware, in which the software performs preprocessing of input data and calculation and generation of the F matrix, and then the hardware performs the CRC encoding process, thereby reducing the time consumption to the greatest extent and improving the working efficiency of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a serial CRC encoding circuit.

[0052] Figure 2 This is a structural diagram of the F matrix according to an embodiment of the present invention.

[0053] Figure 3 This is a structural diagram of a parallel CRC encoding circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The CRC encoding principle of parallel data provided by the method is derived from serial encoding.

[0055] The encoding process of a (n, k) system cyclic code (where n represents the code length and k represents the length of the information bit) is as follows. Assume that the information codeword before encoding is [m0,m1,…,m k-1 ], then the information code can be expressed as a polynomial m(x) = m0+m1x+…+m k-1 x k-1 , let the message polynomial be m(x), the generator polynomial be g(x), divide x by the generator polynomial g(x) n-k m(x) obtains the remainder b(x), and the codeword polynomial c(x) = x n-k m(x)+b(x).

[0056] According to the polynomial operation circuit, the serial coding operation is as follows Figure 1 As shown, multiplication and addition are both operations on GF(2). g0,g1,…,g k-1 b0,b1,…,b are the coefficients of the generating polynomial g(x). When the coefficient is 1, the line is connected, and when the coefficient is 0, the line is disconnected. k-1 is the coefficient of the remainder polynomial b(x). The gate is opened in the first k clocks, indicating that the input of the encoder is the information codeword at this time, and is closed at the last nk clocks, indicating that the input of the encoder is 0. Figure 1 Output 1 is the output of the first k bits of the encoder, that is, the information codeword, and output 2 is the check bit output of the last nk bits. When the k-bit information codeword and the nk-bit 0s pass through the encoding circuit, the value of the register obtained is the check bit of the CRC.

[0057] Figure 1 In the circuit, the order of the information codes entering the encoder is m k ,m k-1 ,…,m1,m0, the order of the output remainder register is b n-k-1 ,b n-k-2 ,…,b1,b0.

[0058] Assume that the contents of the nk remainder registers at time T are b0(T), b1(T), ..., b n-k-1 (T), the input information bit is m(T+1), and the register status at time T+1 is b0(T+1), b1(T+1),…, b n-k-1 (T+1), then the relationship between the register values ​​at time T+1 and time T is as follows:

[0059]

[0060] remember

[0061]

[0062] The above formula can be expressed as b(T+1)=F'×[b(T)+M(T+1)], and the relationship between the register state between time T+P and time T and the P information codewords can be further obtained as follows:

[0063] b(T+P)=F' P ×b(T)+F' P ×M(T+1)+F' P-1 ×M(T+2)+…+F'×M(T+P)

[0064] When i varies from 2 to P, F' i and F'i-1 The following relationship exists:

[0065]

[0066] From the above, it can be concluded that when parallel data is input, CRC calculation is performed according to the following steps.

[0067] Step 1: Information codeword initial value processing:

[0068] Suppose the information codeword before encoding is [m'0,m'1,…,m' l-1 ]; When the CRC initial value is required to be all 0, execute step 2; When the CRC initial value is required to be all 1, perform XOR processing on the first crc_len number of information codewords and 1, where crc_len is the length of the generated CRC;

[0069] Step 2: Information codeword parallel processing:

[0070] When the codeword length l is divisible by the parallelism P, execute step 3; when the codeword length l is not divisible by the parallelism P, perform data zero padding, that is, pad 0 in front of the information codeword until the length is a multiple of P, and the information codeword is [0,0,…,0,m'0,m'1,…,m' l-1 ], let the information codeword after zero padding be [m0,m1,…m k-1 ],in

[0071] Step 3: Calculate the parameters:

[0072] make The information codeword [m0,m1,…m k-1 ] is divided into M'0=[m0,m1,…m P-1 ]、M'1=[m P ,m P+1 ,…m 2*P-1 ]…M' C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ] A total of C vectors;

[0073] When the parallelism P≤crc_len,

[0074] Remainder polynomial b(0) = [0,…,0] T , length is crc_len;

[0075] F=F' P , is a matrix of size crc_len×crc_len;

[0076] According to the matrix calculation rules, M'0 to M' C-1The end of the vector is filled with 0 until the length of the vector is crc_len, and then transposed to get M0 to M C-1 :

[0077] M0=[m0,m1,…m P-1 ,0,…,0] T

[0078] M1=[m P ,m P+1 ,…m 2*P-1 ,0,…,0] T

[0079] …

[0080] M C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ,0,…,0] T

[0081] When the parallelism P ≥ crc_len,

[0082] Remainder polynomial b(0) = [0,…,0] T , length is P;

[0083] like Figure 2 As shown, the F matrix is ​​a P×P matrix. P Expand on this basis and fill the first crc_len rows of the F matrix into F' in order by crc_len columns. P-i×crc_len ,in If P is an integer multiple of crc_len, F' P-i×crc_len The matrix is ​​directly filled in order; otherwise, the extra columns in the last F' are discarded when filling in;

[0084] According to the matrix calculation rules, M'0 to M' C-1 The end of the vector is filled with 0 until the length of the vector is P, and then transposed to get M0 to M C-1 :

[0085] M0=[m0,m1,…m P-1 ,0,…,0] T

[0086] M1=[m P ,m P+1 ,…m 2*P-1 ,0,…,0] T

[0087] …

[0088] M C-1 =[m (C-1)*P ,m (C-1)*P+1,…m C*P-1 ,0,…,0] T ;

[0089] Step 4: Calculate CRC:

[0090] like Figure 3 As shown, calculate according to the following formula:

[0091] b(N+P)=F×(b(N+P-1)+M N )N=0,1,…,C-1

[0092] Split into each step, the calculation is done in the following order:

[0093] b(0+P)=F×[b(0)+M0]

[0094] b(1+P)=F×[b(P)+M1]

[0095] b(2+P)=F×[b(1+P)+M2]

[0096] …

[0097] b(N+P)=F×[b(N+P-1)+M N ]

[0098] …

[0099] b(C-1+P)=F×[b((C-2)+P)+M C-1 ]

[0100] When the parallelism P≤crc_len, take b(C-1+P) as the register result b, that is, b0, b1, ..., b n-k-1 ;

[0101] When the parallelism P ≥ crc_len, take the first crc_len number of b(C-1+P) as the register result b, that is, b0, b1, ..., b n-k-1 ;

[0102] If configured as CRC generation mode, the register result is the CRC check code b; if configured as CRC check mode, it is determined whether the CRC check code b is all zeros. If it is all zeros, the check is successful, and if it is not all zeros, the check fails.

[0103] Among them, step one, step two, and step three are implemented by software, and step four is implemented by hardware circuit.

[0104] Implementation Example 1

[0105] The method of the present invention is used to generate a CRC result with a parallel degree of 8, a standard generating polynomial of CRC-16, and a CRC initial value of 0.

[0106] Given that the input data is 01000000010101010100110111000100, the generating polynomial of CRC-16 is x 16 +x 15 +x 2 +1, the F_P matrix of the parallel CRC can be obtained as follows:

[0107]

[0108]

[0109] The storage value of the register in each round according to the degree of parallelism is as follows:

[0110]

[0111]

[0112] The first column is the initial value, and the last column is the final CRC calculation result, which is 0010100010000111.

Claims

1. A flexibly configurable general parallel CRC generation and verification method, characterized in that: The following steps are involved: Step 1: Information codeword initial value processing: Suppose the information codeword before encoding is [m'0,m'1,…,m' l-1 ]; When the CRC initial value is required to be all 0, execute step 2; When the CRC initial value is required to be all 1, perform XOR processing on the first crc_len number of information codewords and 1, where crc_len is the length of the generated CRC; Step 2: Information codeword parallel processing: When the codeword length l is divisible by the parallelism P, execute step 3; when the codeword length l is not divisible by the parallelism P, perform data zero padding, that is, pad 0 in front of the information codeword until the length is a multiple of P, and the information codeword is [0,0,…,0,m'0,m'1,…,m' l-1 ], let the information codeword after zero padding be [m0,m1,…m k-1 ],in Step 3: Calculate the parameters: make The information codeword [m0,m1,…m k-1 ] is divided into M'0=[m0,m1,…m P-1 ]、M'1=[m P ,m P+1 ,…m 2*P-1 ]…M' C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ] A total of C vectors; When the parallelism P≤crc_len, Remainder polynomial b(0) = [0,…,0] T , length is crc_len; F=F' P , is a matrix of size crc_len×crc_len; According to the matrix calculation rules, M'0 to M' C-1 The end of the vector is filled with 0 until the length of the vector is crc_len, and then transposed to get M0 to M C-1 : M0=[m0,m1,…m P-1 ,0,…,0] T M1=[m P ,m P+1 ,…m 2*P-1 ,0,…,0] T … M C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ,0,…,0] T When the parallelism P ≥ crc_len, Remainder polynomial b(0) = [0,…,0] T , length is P; The F matrix is ​​a P×P matrix. P Expand on this basis and fill the first crc_len rows of the F matrix into F' in order by crc_len columns. P-i×crc_len ,in If P is an integer multiple of crc_len, F' P-i×crc_len The matrix is ​​directly filled in sequence; otherwise, the extra columns in the last F' are discarded when filling in; According to the matrix calculation rules, M'0 to M' C-1 The end of the vector is filled with 0 until the length of the vector is P, and then transposed to get M0 to M C-1 : M0=[m0,m1,…m P-1 ,0,…,0] T M1=[m P ,m P+1 ,…m 2-P-1 ,0,…,0] T … M C-1 =[m (C-1)*P ,m (C-1)*P+1 ,…m C*P-1 ,0,…,0] T ; in, g0,g1,…,g n-k-1 are the coefficients of the generating polynomial g(x); Step 4: Calculate CRC: Calculate step by step according to the following formula: b(0+P)=F×[b(0)+M0] b(1+P)=F×[b(P)+M1] b(2+P)=F×[b(1+P)+M2] … b(N+P)=F×[b(N+P-1)+M N ] … b(C-1+P)=F×[b((C-2)+P)+M C-1 ] When the parallelism P≤crc_len, take b(C-1+P) as the register result b; When the parallelism P ≥ crc_len, take the first crc_len number of b(C-1+P) as the register result b; If configured as CRC generation mode, the register result is the CRC check code b; if configured as CRC check mode, it is determined whether the CRC check code b is all zeros. If it is all zeros, the check is successful, and if it is not all zeros, the check fails.

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