Three-dimensional integration method and structure based on storage and calculation integrated chip

Abstract

The invention provides a three-dimensional integration method and structure based on a storage and calculation integrated chip, and relates to the technical field of semiconductors, and the method comprises the steps: preparing the storage and calculation integrated chip which is obtained by bonding a storage unit chip and a calculation unit chip; a chip packaging body is prepared on a first adapter plate by using the storage and calculation integrated chip, and the chip packaging body is an embedded fan-out packaging body; and bonding the plurality of chip packaging bodies through the micro bumps to obtain the storage and calculation integrated three-dimensional integrated structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a three-dimensional integration method and structure based on a storage and computing integrated chip. Background Art

[0002] Compute-In-Memory (CIM) chip is a new type of computing architecture that can improve computing efficiency and energy efficiency by closely integrating computing units with storage units and reducing data transmission between processors and memories.

[0003] However, the existing integrated storage and computing chips have complex stacking designs and high manufacturing process requirements, which leads to high design difficulty and high production costs. In addition, complex stacking methods will also introduce more complex signal transmission problems, such as signal delay, noise and interference. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a three-dimensional integration method and structure based on a storage and computing integrated chip to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a three-dimensional integration method based on a storage-computing integrated chip is provided, the method comprising:

[0006] Prepare a storage-computing integrated chip, wherein the storage-computing integrated chip is obtained by bonding a storage unit chip and a computing unit chip;

[0007] Using the integrated storage and computing chip, a chip package is prepared on a first adapter board, wherein the chip package is an embedded fan-out package;

[0008] The plurality of chip packages are bonded to each other through micro-bumps to obtain a three-dimensional integrated storage and computing structure.

[0009] In a possible implementation, the preparation of the storage-computing integrated chip includes:

[0010] Depositing a silicon dioxide layer on the surface to be bonded of the storage unit chip and the surface to be bonded of the computing unit chip respectively;

[0011] Using a Damascus process, a hybrid bonding structure is prepared on the silicon dioxide layer of the storage unit chip and the computing unit chip respectively;

[0012] The storage unit chip and the computing unit chip are bonded via the hybrid bonding structure and annealed to obtain the storage-computing integrated chip.

[0013] In a possible implementation manner, using the integrated storage and computing chip to prepare a chip package on a first adapter board includes:

[0014] Prepare a first metal-filled through-hole structure on the first adapter plate;

[0015] Based on the size of the integrated storage and computing chip to be embedded, etching a chip embedding groove on the first surface of the first adapter plate;

[0016] Embedding the integrated storage and computing chip in the center of the chip embedding groove;

[0017] Prepare a wiring dielectric layer on the first surface of the first adapter board;

[0018] A window is opened for the integrated storage and computing chip, and one or more first interconnect structures embedded in the wiring dielectric layer are prepared. The first interconnect structures realize metal interconnection between the integrated storage and computing chip and the through-hole structure to obtain the chip package.

[0019] In a possible implementation manner, preparing a wiring dielectric layer on the first surface of the first adapter board includes:

[0020] On the first surface of the first adapter plate, a layer of polyparaxylene film is prepared by deposition or dry film lamination process, so that the polyparaxylene film completely fills the gap between the chip embedding groove and the storage-computing integrated chip;

[0021] Removing excess polyparaxylene film on the first surface by oxygen plasma etching;

[0022] The wiring dielectric layer is prepared on the first surface by using polyimide through spin coating or dry film lamination process.

[0023] In a possible implementation manner, bonding the plurality of chip packages via micro-bumps includes:

[0024] Prepare micro bumps on the surface of the n-th level chip package;

[0025] Micro-bumps are prepared on the surface to be bonded of the chip package of the n+1th level, wherein the surface to be bonded of the chip package of the n+1th level is the surface of the chip package of the n+1th level on the side where the storage-computing-in-one chip is embedded, or the surface of the chip package of the n+1th level away from the side where the storage-computing-in-one chip is embedded;

[0026] Aligning the micro-bumps on the surface of the chip package of the nth level with the micro-bumps on the surface to be bonded of the chip package of the n+1th level one by one for bonding;

[0027] Repeat the above steps until the bonding of the last chip package is completed to obtain the storage and computing three-dimensional integrated structure.

[0028] In a possible implementation manner, after the storage-computing integrated three-dimensional structure is prepared, the method further includes:

[0029] Using a ball planting process, solder balls are prepared on the surface of the storage-computing integrated three-dimensional integrated structure;

[0030] The storage-computing three-dimensional integrated structure is bonded to an organic substrate through the solder balls to obtain a packaged storage-computing three-dimensional integrated structure.

[0031] In a possible implementation manner, the thickness of the silicon dioxide layer is 2-10 um.

[0032] In a possible implementation manner, the first adapter plate is: a silicon adapter plate, a glass adapter plate, or an organic adapter plate.

[0033] In a possible implementation manner, the wiring dielectric layer has a thickness of 3-10 um.

[0034] The second aspect of the embodiment of the present application also provides a three-dimensional integrated structure of storage and computing, which is prepared by the method described in the first aspect of the embodiment of the present application, and the three-dimensional integrated structure of storage and computing includes: a plurality of chip packages bonded by micro-bumps, each of the chip packages having a storage and computing chip embedded therein, and the storage and computing chip is obtained by bonding a storage unit chip and a computing unit chip.

[0035] The embodiment of the present application provides a three-dimensional integration method based on a storage-computing integrated chip, the method comprising: preparing a storage-computing integrated chip, the storage-computing integrated chip being obtained by bonding a storage unit chip and a computing unit chip; using the storage-computing integrated chip to prepare a chip package on a first adapter board, the chip package being a buried fan-out package; bonding a plurality of the chip packages through micro-bumps to obtain a storage-computing integrated three-dimensional integrated structure. The three-dimensional integration method based on a storage-computing integrated chip provided in the present application, on the one hand, adopts a hybrid bonding method of a single storage unit chip and a single computing unit chip to minimize the physical distance between the computing unit chip and the storage unit chip, reduce the length of the signal transmission path, thereby reducing signal delay, increasing data transmission speed, and making the interaction between storage and computing more efficient. On the other hand, the integrated storage and computing chip obtained after bonding is packaged based on the embedded fan-out packaging process to obtain a chip package, so that multiple chip packages are bonded through micro-bumps to achieve multi-level chip stacking. Compared with the traditional three-dimensional integration method of integrated storage and computing chips (stacking a single LOGIC and multiple SRAMs), it reduces the design complexity, shortens the development cycle, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 It is a flowchart of the steps of a three-dimensional integration method based on a storage-computing integrated chip provided in an embodiment of the present application;

[0038] Figure 2 It is a schematic diagram of the structure of a storage-computing integrated chip provided in an embodiment of the present application;

[0039] Figure 3 It is a schematic diagram of a bonding process of a storage-computing integrated chip provided in an embodiment of the present application;

[0040] Figure 4 is a schematic structural diagram of a chip package provided in an embodiment of the present application;

[0041] Figure 5 is a structural schematic diagram of a first adapter board provided in an embodiment of the present application;

[0042] Figure 6 It is a schematic diagram of a preparation process of a chip package provided in an embodiment of the present application.

[0043] Figure 7 It is a schematic diagram of a two-to-two bonding structure of a chip package provided in an embodiment of the present application;

[0044] Figure 8 It is a structural schematic diagram of a storage-computing integrated three-dimensional structure provided in an embodiment of the present application;

[0045] Fig. 9 It is a structural schematic diagram of a packaged storage-computing integrated three-dimensional integrated structure provided in an embodiment of the present application;

[0046] Fig.10 is a schematic structural diagram of a three-dimensional integrated device provided in an embodiment of the present application;

[0047] Description of the drawings: storage unit chip 100, first silicon dioxide layer 101, metal through-hole structure 102 in the storage unit chip, first hybrid bonding structure 103; computing unit chip 200, second silicon dioxide layer 201, second hybrid bonding structure 202; first adapter board 300, through-hole structure 301 in the first adapter board, chip buried groove 302, wiring dielectric layer 303, first interconnect structure 304, DAF film 305, micro bumps 306; solder balls 401, organic substrate 402. DETAILED DESCRIPTION

[0048] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0049] Compute-In-Memory (CIM) chip is a new type of computing architecture that can improve computing efficiency and energy efficiency by closely integrating computing units with storage units and reducing data transmission between processors and memories.

[0050] Traditional storage and computing integrated chips are designed by stacking a single LOGIC (i.e., computing unit chip) and multiple SRAMs (i.e., storage unit chips) in a three-dimensional integrated manner. Although this method can greatly increase the storage capacity, the stacking design of multiple SRAMs is complex and the manufacturing process requirements are high, which brings higher design difficulty and higher production cost. In addition, the stacking of multiple SRAMs will also introduce more complex signal transmission problems, such as signal delay, noise and interference problems, which require more complex design and optimization; finally, the stacking of multiple SRAMs will also increase the overall power consumption and thermal management difficulty of the chip; and the current three-dimensional stacking structure designed for storage and computing integrated chips is generally on the storage chip. If a single LOGIC-SRAM integrated structure is required, the three-dimensional design of the LOGIC and SRAM chips needs to be readjusted, which has high costs and time cycles.

[0051] In view of the above problems, the embodiment of the present application proposes a three-dimensional integration method and structure based on a storage-computing integrated chip. The following is a detailed description of a three-dimensional integration method based on a storage-computing integrated chip provided by the embodiment of the present application through some embodiments and their application scenarios in conjunction with the accompanying drawings.

[0052] The first aspect of the embodiment of the present application provides a three-dimensional integration method based on a storage and computing integrated chip, referring to Figure 1 , Figure 1 A flowchart of a three-dimensional integration method based on a storage-computing integrated chip provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method includes:

[0053] Step S101, preparing a storage-computing integrated chip, wherein the storage-computing integrated chip is obtained by bonding a storage unit chip and a computing unit chip.

[0054] In the related art, for a storage-computing integrated chip, a chip structure is often obtained by stacking and integrating a computing unit chip (i.e., LOGIC) with multiple storage unit chips (i.e., SRAM). However, the stacking design of a LOGIC and multiple SRAMs is complex, which brings about higher design difficulty and higher production cost, as well as more complex signal transmission and other issues.

[0055] In order to simplify the three-dimensional integrated structure of the storage and computing integrated chip, the present application first proposes to integrate a single storage unit chip and a single computing unit chip. Figure 2 , Figure 2 A schematic diagram of the structure of a storage and computing integrated chip is shown in FIG. Figure 2 As shown, the integrated storage and computing chip is obtained by bonding a storage unit chip 100 and a computing unit chip 200 through a hybrid bonding structure.

[0056] The embodiment of the present application adopts an integrated method in which a single LOGIC and a single SRAM are bonded and work directly. Since only one storage unit chip and one logic unit chip are involved in each storage-computing integrated chip, the design complexity is low. This simple design makes the development cycle shorter and the debugging and verification process more efficient. Circuit layout and wiring are easier to optimize, because there is only one storage unit chip and one logic unit chip, which can more easily manage the layout of power, clock and signal lines. Due to the simple design, less design and verification time is required, thereby reducing development costs. The stacking of a single SRAM and a LOGIC minimizes the physical distance between the storage unit and the computing unit, which reduces the path length of the signal transmission between the two, thereby reducing signal delay. A shorter signal transmission path not only reduces delays, but also increases data transmission speeds, making the interaction between storage and computing more efficient. Lower delays and faster data transmission speeds are particularly important for applications that require real-time processing, such as image processing and artificial intelligence reasoning. The energy consumption of data transmission between the storage unit and the computing unit is proportional to the transmission distance. A shorter transmission path means lower energy consumption, thereby improving the overall energy efficiency of the chip. By reducing data movement, energy loss caused by frequent data transmission can be reduced.

[0057] In a possible implementation, the step S101, preparing a storage-computing integrated chip, includes:

[0058] Step S1011, depositing a silicon dioxide layer on the surface to be bonded of the storage unit chip and the surface to be bonded of the computing unit chip respectively.

[0059] Reference Figure 3 , Figure 3 A schematic diagram of the bonding process of a storage-computing integrated chip is shown. Figure 3 As shown in (a), firstly, a silicon dioxide layer on the storage unit chip 100 (the surface to be bonded), namely, a first silicon dioxide layer 101, and a silicon dioxide layer on the computing unit chip 200 (the surface to be bonded), namely, a second silicon dioxide layer 201, are prepared respectively. Figure 3 As shown in (a), the memory cell chip 100 includes a plurality of TSV metal through hole structures 102 .

[0060] In a possible implementation, the thickness of the silicon dioxide layer is 2-10 um. Exemplarily, the thickness of the silicon dioxide layer can be 2 um, 6 um or 10 um. Preferably, the thickness of the silicon dioxide layer (i.e., the silicon dioxide layer 201 on the computing unit chip 200 or the silicon dioxide layer 101 on the storage unit chip 100) can be set to 5 um.

[0061] Step S1012: using a Damascene process to prepare a hybrid bonding structure on the silicon dioxide layers of the storage unit chip and the computing unit chip, respectively.

[0062] Hybrid bonding structures such as Figure 3 As shown in (b), a standard Damascus process is used to prepare a first hybrid bonding structure 103 (i.e., a hybrid bonding structure on the surface to be bonded of the storage unit chip) on the first silicon dioxide layer 101, and a second hybrid bonding structure 202 (i.e., a hybrid bonding structure on the surface to be bonded of the computing unit chip) on the second silicon dioxide layer 201. The specific structure and shape of the hybrid bonding structure can be determined according to the actual application requirements and are not limited in this embodiment. Specifically, the standard process flow of the Damascus process is: photolithography (the photolithography pattern can be adjusted according to the design requirements), silicon oxide etching (the etching depth is generally required to penetrate the silicon dioxide layer to form a structure connected to the bottom PAD), seed layer sputtering (Ti / Cu), electroplating, and CMP.

[0063] Step S1013, bonding the storage unit chip and the computing unit chip through the hybrid bonding structure, performing annealing treatment, and obtaining the storage and computing integrated chip.

[0064] In this embodiment, the storage unit chip and the computing unit chip are hybrid bonded at room temperature (e.g., 22° C.) (so that the first hybrid bonding structure 103 is aligned and in contact with the second hybrid bonding structure 202), and then a high-temperature annealing treatment is performed to obtain a LOGIC-SRAM hybrid bonding chipset, i.e., a storage-computation integrated chip. In a possible implementation, the temperature condition for the high-temperature annealing treatment may be 300° C.

[0065] Step S102, using the integrated storage and computing chip, preparing a chip package on a first adapter board, wherein the chip package is an embedded fan-out package.

[0066] For the integrated storage and computing chip obtained after bonding, the embodiment of the present application proposes packaging based on the buried fan-out packaging process to obtain a chip package, so that multiple chip packages are bonded through micro-bumps to achieve multi-level chip stacking. The embodiment of the present application aims to achieve a three-dimensional stacking and reintegration design of chips after hybrid bonding without changing or adding to the existing chip design. Compared with the traditional three-dimensional integration method of integrated storage and computing chips (stacking a single LOGIC and multiple SRAMs), it reduces the design complexity, shortens the development cycle, and reduces production costs, achieving high-efficiency, low-power consumption, and real-time processing capability three-dimensional packaging of integrated storage and computing chips. Specifically, refer to Figure 4 , Figure 4 A schematic structural diagram of a chip package is shown.

[0067] In a possible implementation, the step S102, using the integrated storage and computing chip to prepare a chip package on a first adapter board, includes:

[0068] Step S1021: preparing a first metal-filled through-hole structure on the first adapter plate.

[0069] Specifically, refer to Figure 5 , Figure 5 A schematic diagram of the structure of a first adapter board is shown, such as Figure 5 As shown, for the first adapter board 300, firstly, a TSV, TGV or TPV standard process is used to prepare one or more first metal-filled through-hole structures 301 on the first adapter board. The first metal may be copper or tungsten.

[0070] In a possible implementation manner, the first adapter plate is: a silicon adapter plate, a glass adapter plate, or an organic adapter plate.

[0071] Step S1022, based on the size of the integrated storage and computing chip to be embedded, etching a chip embedding groove on the first surface of the first adapter plate.

[0072] Specifically, refer to Figure 6 , Figure 6 A schematic diagram of a chip package preparation process is shown. Figure 6 As shown in (a), etching is performed on the first surface of the first adapter plate 300 based on the size of the storage-computing integrated chip to obtain a chip embedding groove 302. The position of the chip embedding groove 302 (i.e., the position of the storage-computing integrated chip) can be determined according to actual application requirements and is not limited in this embodiment.

[0073] In a possible implementation, after the step S101 is completed and the storage-computing integrated chip is obtained, a layer of DAF film needs to be deposited on the storage-computing integrated chip. Specifically, a layer of DAF film needs to be prepared on the surface of one side of the computing unit chip. When executing step 1022, the height of the chip landfill groove 302 obtained by etching needs to be the same as the height of the storage-computing integrated chip (that is, the same as the height after the DAF film is deposited on the storage-computing integrated chip), and the width of the chip landfill groove is 3-30 microns longer than the width of the storage-computing integrated chip. In order to ensure that the storage-computing integrated chip can be accurately placed in the chip landfill groove, according to the capacity of the placement machine, when etching the chip landfill groove, a certain width can be reserved, that is, the chip landfill groove is designed to be 3-30 microns wider than the storage-computing integrated chip.

[0074] Step S1023, burying the integrated storage and computing chip in the center of the chip embedding groove.

[0075] Specifically, Figure 6As shown in (b), the integrated storage and computing chip can be embedded in the center of the chip embedding groove using a submicron bonding machine or a flip-chip bonding machine under heating and pressurizing conditions, and the integrated storage and computing chip is bonded to the bottom of the chip embedding groove through the DAF film 305. Furthermore, considering that multiple layers of chip packages need to be stacked later, a DAF film needs to be prepared on one side of the computing unit chip in the integrated storage and computing chip, so that one side of the computing unit chip is fixed to the bottom of the chip embedding groove through the DAF film 305, as shown in FIG. Figure 6 As shown in (b), the memory unit chip 100 is located above the computing unit chip 200.

[0076] Step S1024: preparing a wiring dielectric layer on the first surface of the first adapter board.

[0077] Specifically, Figure 6 As shown in (c), after filling the gap between the integrated storage and computing chip and the chip embedding groove, a wiring dielectric layer 303 is prepared on the first surface of the first adapter plate 300. In a possible implementation, the thickness of the wiring dielectric layer is 3-10 um. Exemplarily, the thickness of the wiring dielectric layer can be 3 um, 5 um or 10 um.

[0078] In a possible implementation manner, the step S1024, preparing a wiring dielectric layer on the first surface of the first adapter board, includes:

[0079] Step S1, on the first surface of the first adapter plate, a layer of polyparaxylene film is prepared by deposition or dry film lamination process, so that the polyparaxylene film completely fills the gap between the chip embedding groove and the storage-computing integrated chip.

[0080] Specifically, since the etched chip embedding groove is wider than the integrated storage and computing chip, a gap exists between the integrated storage and computing chip and the chip embedding groove. In this embodiment, room temperature chemical vapor deposition or dry film lamination process can be used to make the polyparaxylene film (i.e., Parylene material) completely fill the gap between the chip embedding groove and the integrated storage and computing chip.

[0081] Step S2, removing the excess polyparaxylene film on the first surface by oxygen plasma etching.

[0082] Step S3, preparing the wiring dielectric layer on the first surface by using polyimide (ie, PI material) through spin coating or dry film lamination process.

[0083] Step S1025, opening a window for the integrated storage and computing chip, preparing one or more first interconnect structures embedded in the wiring dielectric layer, the first interconnect structure realizing metal interconnection between the integrated storage and computing chip and the through-hole structure, and obtaining the chip package.

[0084] In this embodiment, the first interconnect structure (ie, interconnect RDL) is used to realize metal interconnection between the storage-computing integrated chip and the through-hole structure (prepared in step S1021) in the adapter board, such as Figure 4 As shown, one end of the first interconnect structure 304 is connected to the TSV in the storage unit chip in the storage-computing integrated chip, and the other end is connected to the through-hole structure in the first adapter plate. In a possible implementation, the metal material for preparing the first interconnect structure is copper, which has excellent conductive properties and is conducive to realizing metal interconnection between chips. Among them, the specific shape and position of the first interconnect structure 105 can be set according to actual needs, so as to determine the specific position according to the actual metal interconnection requirements between the first chips.

[0085] Step S103, bonding the plurality of chip packages together through micro-bumps to obtain a three-dimensional storage and computing integrated structure.

[0086] In a possible implementation manner, the step S103 of bonding the plurality of chip packages via micro-bumps includes:

[0087] Step S1031 , preparing micro bumps on the surface of the n-th level chip package.

[0088] Step S1032, preparing micro-bumps on the bonding surface of the n+1-th level chip package, wherein the bonding surface of the n+1-th level chip package is the surface of the n+1-th level chip package on the side where the storage-computing integrated chip is embedded, or the surface of the n+1-th level chip package on the side away from the embedded storage-computing integrated chip.

[0089] Step S1033, aligning the micro bumps on the surface of the n-th level chip package with the micro bumps on the to-be-bonded surface of the n+1-th level chip package one by one for bonding.

[0090] Specifically, the chip packages are bonded in pairs through microbumps. In a possible implementation, the material of the microbumps is copper or tin. The microbumps serve as bonding points for subsequent bonding of the chip packages. The positions of the microbumps can be set according to actual needs and are not specifically limited in this embodiment.

[0091] Multiple chip packages are bonded and stacked in a certain hierarchical order. For any two adjacent hierarchical chip packages, there may be multiple bonding methods. Figure 7 , Figure 7 A schematic diagram of a chip package bonding structure is shown. Figure 7As shown in (a), (b) and (c), when the chip package of the nth level is bonded to the chip package of the n+1th level, the chip package of the nth level is at the bottom and the chip package of the n+1th level is at the top. The micro-bumps on the chip package of the nth level and the micro-bumps on the chip package of the n+1th level are in a one-to-one correspondence, so that the two can be aligned and bonded under conditions of heating and pressure.

[0092] Figure 7 (a) shows that when two chip packages are bonded through micro-bumps 306, the bonding surface of the n-th level chip package is the surface on the side where the integrated storage and computing chip is embedded, and the bonding surface of the n+1-th level chip package is the surface away from the side where the integrated storage and computing chip is embedded. Figure 7 (b) shows that when two chip packages are bonded through micro-bumps 306, the bonding surface of the n-th level chip package is the surface on the side of the embedded storage-computing chip, and the bonding surface of the n+1-th level chip package is the surface on the side of the embedded storage-computing chip. Figure 7 (c) shows that when two chip packages are bonded via micro bumps 306, the surface to be bonded of the chip package at the nth level is the surface away from the embedded storage-computing integrated chip, and the surface to be bonded of the chip package at the n+1th level is the surface away from the embedded storage-computing integrated chip. Where n represents any positive integer less than the total number of chip packages.

[0093] Step S1034, repeat the above steps until the bonding of the last chip package is completed to obtain the storage and computing three-dimensional integrated structure.

[0094] Reference Figure 8 , Figure 8 A schematic diagram of a three-dimensional integrated storage and computing structure is shown. Figure 8 As shown, assuming that the three-dimensional integrated structure has a total of 4 layers, after the first stacking is completed, continue to prepare RDL and Microbump structure on the stacked structure and then stack it to form a 4-layer three-dimensional stacked structure (a storage and computing three-dimensional integrated structure obtained by bonding 4 chip packages in sequence through microbumps).

[0095] In a possible implementation manner, after the storage-computing integrated three-dimensional structure is prepared, the method further includes:

[0096] Using a ball planting process, solder balls are prepared on the surface of the storage-computing integrated three-dimensional integrated structure;

[0097] The storage-computing three-dimensional integrated structure is bonded to an organic substrate through the solder balls to obtain a packaged storage-computing three-dimensional integrated structure.

[0098] In the embodiment of the present application, after stacking multiple chip packages to obtain a three-dimensional integrated storage and computing structure, a ball planting process is used to package the three-dimensional integrated storage and computing structure onto a substrate. Fig. 9 , Fig. 9 A schematic diagram of a packaged three-dimensional storage and computing integrated structure is shown. Fig. 9 As shown, an insulating layer is first deposited on the surface of the storage and computing three-dimensional integrated structure, and then a plurality of solder balls 401 are prepared on the insulating layer by a ball planting process. The solder balls 401 are bonded to an organic substrate 402 under heating and pressure conditions to complete the packaging and obtain a packaged storage and computing three-dimensional integrated structure.

[0099] The three-dimensional integration method based on the integrated storage and computing chip provided in the present application, on the one hand, adopts a hybrid bonding method of a single storage unit chip and a single computing unit chip to minimize the physical distance between the computing unit chip and the storage unit chip, reduce the length of the signal transmission path, and thus reduce the signal delay, increase the data transmission speed, and make the interaction between storage and computing more efficient. On the other hand, for the integrated storage and computing chip obtained after bonding, it is packaged based on the embedded fan-out packaging process to obtain a chip package, so that multiple chip packages are bonded through micro-bumps to achieve multi-level chip stacking. Compared with the traditional three-dimensional integration method of the integrated storage and computing chip (using a single LOGIC and multiple SRAMs for stacking), it reduces the design complexity, shortens the development cycle, and reduces production costs.

[0100] The second aspect of the embodiment of the present application also provides a three-dimensional integrated structure of storage and computing, which is prepared by the three-dimensional integration method based on the storage and computing chip described in the first aspect of the embodiment of the present application. The three-dimensional integrated structure of storage and computing includes: a plurality of chip packages bonded by micro-bumps, each of the chip packages having a storage and computing chip embedded therein, and the storage and computing chip is obtained by bonding a storage unit chip and a computing unit chip.

[0101] Specifically, the structure of the storage-computing integrated three-dimensional structure is as follows: Fig. 9 As shown, multiple chip packages are bonded by micro-bumps to achieve multi-level stacking. Each chip package is formed by etching a chip embedding groove on the first adapter board, and then embedding a storage and computing integrated chip in the chip embedding groove. Each storage and computing integrated chip is provided with a wiring dielectric layer, and RDL and multiple micro-bumps are prepared on the wiring dielectric layer. Each storage and computing integrated chip is obtained by hybrid bonding at room temperature by a storage unit chip and a computing unit chip through their respective hybrid bonding structures.

[0102] The third aspect of the embodiment of the present application provides a three-dimensional integrated device based on a storage-computing integrated chip, which is used to execute the steps of the three-dimensional integrated method based on a storage-computing integrated chip provided in the first aspect, referring to Fig.10 , Fig.10 A schematic diagram of the structure of a three-dimensional integrated device is shown. Fig.10 As shown, the device comprises:

[0103] A storage-computing integrated chip preparation module, used to prepare a storage-computing integrated chip, wherein the storage-computing integrated chip is obtained by bonding a storage unit chip and a computing unit chip;

[0104] A chip package preparation module, used to prepare a chip package on a first adapter board using the storage-computing integrated chip, wherein the chip package is an embedded fan-out package;

[0105] The three-dimensional integrated module is used to bond the plurality of chip packages together through micro-bumps to obtain a three-dimensional integrated storage and computing structure.

[0106] In a possible implementation, the storage-computing integrated chip preparation module is used to:

[0107] Depositing a silicon dioxide layer on the surface to be bonded of the storage unit chip and the surface to be bonded of the computing unit chip respectively;

[0108] Using a Damascus process, a hybrid bonding structure is prepared on the silicon dioxide layer of the storage unit chip and the computing unit chip respectively;

[0109] The storage unit chip and the computing unit chip are bonded via the hybrid bonding structure and annealed to obtain the storage-computing integrated chip.

[0110] In a possible implementation manner, the chip package preparation module is used to:

[0111] Prepare a first metal-filled through-hole structure on the first adapter plate;

[0112] Based on the size of the integrated storage and computing chip to be embedded, etching a chip embedding groove on the first surface of the first adapter plate;

[0113] Embedding the integrated storage and computing chip in the center of the chip embedding groove;

[0114] Prepare a wiring dielectric layer on the first surface of the first adapter board;

[0115] A window is opened for the integrated storage and computing chip, and one or more first interconnect structures embedded in the wiring dielectric layer are prepared. The first interconnect structures realize metal interconnection between the integrated storage and computing chip and the through-hole structure to obtain the chip package.

[0116] In a possible implementation manner, preparing a wiring dielectric layer on the first surface of the first adapter board includes:

[0117] On the first surface of the first adapter plate, a layer of polyparaxylene film is prepared by deposition or dry film lamination process, so that the polyparaxylene film completely fills the gap between the chip embedding groove and the storage-computing integrated chip;

[0118] Removing excess polyparaxylene film on the first surface by oxygen plasma etching;

[0119] The wiring dielectric layer is prepared on the first surface by using polyimide through spin coating or dry film lamination process.

[0120] In a possible implementation, the three-dimensional integrated module is used to:

[0121] Prepare micro bumps on the surface of the n-th level chip package;

[0122] Micro-bumps are prepared on the surface to be bonded of the chip package of the n+1th level, wherein the surface to be bonded of the chip package of the n+1th level is the surface of the chip package of the n+1th level on the side where the storage-computing-in-one chip is embedded, or the surface of the chip package of the n+1th level away from the side where the storage-computing-in-one chip is embedded;

[0123] Aligning the micro-bumps on the surface of the chip package of the nth level with the micro-bumps on the surface to be bonded of the chip package of the n+1th level one by one for bonding;

[0124] Repeat the above steps until the bonding of the last chip package is completed to obtain the storage and computing three-dimensional integrated structure.

[0125] In a possible implementation manner, the device further includes: a packaging module, configured to:

[0126] Using a ball planting process, solder balls are prepared on the surface of the storage-computing integrated three-dimensional integrated structure;

[0127] The storage-computing three-dimensional integrated structure is bonded to an organic substrate through the solder balls to obtain a packaged storage-computing three-dimensional integrated structure.

[0128] In a possible implementation manner, the thickness of the silicon dioxide layer is 2-10 um.

[0129] In a possible implementation manner, the first adapter plate is: a silicon adapter plate, a glass adapter plate, or an organic adapter plate.

[0130] In a possible implementation manner, the wiring dielectric layer has a thickness of 3-10 um.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0133] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0135] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0136] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0137] The three-dimensional integration method and structure based on the storage and computing integrated chip provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A three-dimensional integration method based on a storage and computing integrated chip, characterized in that: The method comprises: Prepare a storage-computing integrated chip, wherein the storage-computing integrated chip is obtained by bonding a storage unit chip and a computing unit chip; Using the integrated storage and computing chip, a chip package is prepared on a first adapter board, wherein the chip package is an embedded fan-out package; The plurality of chip packages are bonded to each other through micro-bumps to obtain a three-dimensional integrated storage and computing structure.

2. The three-dimensional integration method based on the integrated storage and computing chip according to claim 1 is characterized in that: The method of preparing the integrated storage and computing chip comprises: Depositing a silicon dioxide layer on the surface to be bonded of the storage unit chip and the surface to be bonded of the computing unit chip respectively; Using a Damascus process, a hybrid bonding structure is prepared on the silicon dioxide layer of the storage unit chip and the computing unit chip respectively; The storage unit chip and the computing unit chip are bonded via the hybrid bonding structure and annealed to obtain the storage-computing integrated chip.

3. The three-dimensional integration method based on the integrated storage and computing chip according to claim 1 is characterized in that: The method of using the integrated storage and computing chip to prepare a chip package on a first adapter board includes: Prepare a first metal-filled through-hole structure on the first adapter plate; Based on the size of the integrated storage and computing chip to be embedded, etching a chip embedding groove on the first surface of the first adapter plate; Embedding the integrated storage and computing chip in the center of the chip embedding groove; Prepare a wiring dielectric layer on the first surface of the first adapter board; A window is opened for the integrated storage and computing chip, and one or more first interconnect structures embedded in the wiring dielectric layer are prepared. The first interconnect structures realize metal interconnection between the integrated storage and computing chip and the through-hole structure to obtain the chip package.

4. The three-dimensional integration method based on the integrated storage and computing chip according to claim 3 is characterized in that: The step of preparing a wiring dielectric layer on the first surface of the first adapter board comprises: On the first surface of the first adapter plate, a layer of polyparaxylene film is prepared by deposition or dry film lamination process, so that the polyparaxylene film completely fills the gap between the chip embedding groove and the storage-computing integrated chip; Removing excess polyparaxylene film on the first surface by oxygen plasma etching; The wiring dielectric layer is prepared on the first surface by using polyimide through spin coating or dry film lamination process.

5. The three-dimensional integration method based on the integrated storage and computing chip according to claim 1 is characterized in that: The method of bonding the plurality of chip packages together through micro-bumps comprises: Prepare micro bumps on the surface of the n-th level chip package; Micro-bumps are prepared on the surface to be bonded of the chip package of the n+1th level, wherein the surface to be bonded of the chip package of the n+1th level is the surface of the chip package of the n+1th level on the side where the storage-computing-in-one chip is embedded, or the surface of the chip package of the n+1th level away from the side where the storage-computing-in-one chip is embedded; Aligning the micro-bumps on the surface of the chip package of the nth level with the micro-bumps on the surface to be bonded of the chip package of the n+1th level one by one for bonding; Repeat the above steps until the bonding of the last chip package is completed to obtain the storage and computing three-dimensional integrated structure.

6. The three-dimensional integration method based on the integrated storage and computing chip according to claim 1 is characterized in that: After the storage-computing integrated three-dimensional structure is prepared, the method further includes: Using a ball planting process, solder balls are prepared on the surface of the storage-computing integrated three-dimensional integrated structure; The storage-computing three-dimensional integrated structure is bonded to an organic substrate through the solder balls to obtain a packaged storage-computing three-dimensional integrated structure.

7. The three-dimensional integration method based on the integrated storage and computing chip according to claim 2 is characterized in that: The thickness of the silicon dioxide layer is 2-10 um.

8. The three-dimensional integration method based on the integrated storage and computing chip according to claim 1 is characterized in that ,The first adapter board is: a silicon adapter board, a glass adapter board or an organic adapter board.

9. The three-dimensional integration method based on the integrated storage and computing chip according to claim 3 is characterized in that , the thickness of the wiring dielectric layer is 3-10um.

10. A three-dimensional integrated storage and computing structure, characterized in that: The storage-computing integrated three-dimensional integrated structure is prepared by the three-dimensional integration method based on the storage-computing integrated chip described in any one of claims 1-9, comprising: a plurality of chip packages bonded by micro-bumps, each of the chip packages having a storage-computing integrated chip embedded therein, and the storage-computing integrated chip is obtained by bonding a storage unit chip and a computing unit chip.

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