MEMS device manufacturing method for improving surface flatness and MEMS device

Abstract

The invention discloses an MEMS device manufacturing method for improving surface flatness and an MEMS device. The method comprises the following steps: obtaining a basic SOI sheet, and constructing a substrate by sequentially depositing a metal bottom electrode, a piezoelectric material and a metal top electrode; the metal layer is etched by ion beams, the piezoelectric material is etched by a wet method, and accurate patterning is ensured. And then, growing an insulation protection layer, depositing a metal wiring layer after inductively coupled plasma etching, and then finely etching the wiring layer. The top silicon oxide, the top silicon, the buried oxide layer and the bottom silicon oxide are sequentially processed by utilizing reactive ion etching and deep reactive ion etching technologies, so that the fine structure is ensured. And finally, performing deep reactive ion etching on the bottom silicon twice, releasing a mirror surface structure, and completing manufacturing of the high-flatness MEMS device. By designing and accurately etching the support structure on the bottom silicon, the mirror surface structure can be ensured to stably suspend in the release cavity after being released, and the problem of uneven surface caused by uneven support is avoided.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a method for manufacturing a MEMS device and a MEMS device for improving surface flatness. Background Art

[0002] Micro-electro-mechanical systems (MEMS), also known as micro-electro-mechanical systems, microsystems, micro-machines, etc., refer to high-tech devices with a size of a few millimeters or even smaller. They are mainly composed of three parts: sensors, actuators, and micro-energy. MEMS involves multiple disciplines and engineering technologies such as physics, semiconductors, optics, electronic engineering, chemistry, materials engineering, mechanical engineering, medicine, information engineering, and bioengineering, and has opened up a wide range of uses in the fields of intelligent systems, consumer electronics, wearable devices, smart homes, synthetic biology of system biotechnology, and microfluidics.

[0003] MEMS focuses on ultra-precision machining, involving many disciplines such as microelectronics, materials, mechanics, chemistry, and mechanics. Its disciplines cover various branches of physics, chemistry, and mechanics such as force, electricity, light, magnetism, sound, and surface at the microscale. MEMS is an independent intelligent system that can be mass-produced. Its system size is a few millimeters or even smaller, and its internal structure is generally in the micron or even nanometer level. For example, the size of common MEMS products is generally 3mm×3mm×1.5mm, or even smaller.

[0004] MEMS devices use single crystal silicon wafers / SOI as substrate materials, and use thin film deposition technology, metal micromachining technology and other processes. The silicon-based MEMS preparation process is similar to the IC device industry process, and can be used for photolithography patterning on silicon substrate wafers, including thin film deposition, dry and wet etching, ion implantation diffusion doping, chemical mechanical polishing, etc. Its material performance advantages are: 1. Stable mechanical properties, and the matching MEMS processing technology is mature and controllable, with low cost; 2. Single crystal silicon has a high Young's modulus but low density, which can make the device lightweight; 3. High melting point and low thermal expansion coefficient can adapt to extreme working conditions; 4. Low mechanical hysteresis, etc., and is widely used in sensor device manufacturing. MEMS technology mainly constructs characteristic structures by micromachining the body and surface on silicon wafers / SOI, and derives a large number of new MEMS processes, such as sacrificial layer technology, deep reactive ion etching and LIGA technology to prepare high aspect ratio structures to achieve electrical and mechanical signal conversion.

[0005] Usually, piezoelectric MEMS micromirror devices adopt a subtractive process, that is, various thin film layers are deposited first, and then useless thin film materials are removed in sequence through various dry etching and wet etching, and finally the bottom silicon layer is etched all at once to release the piezoelectric MEMS micromirror device. However, this traditional method will cause the mirror surface tension of the piezoelectric MEMS micromirror device to be large and the mirror surface to bend, resulting in poor mirror flatness and mirror roughness of the piezoelectric MEMS micromirror device, affecting the working performance of the piezoelectric device. Therefore, it will be difficult to improve the manufacturing yield of piezoelectric MEMS micromirror devices using traditional manufacturing processes. Summary of the invention

[0006] In view of this, the embodiments of the present application provide a MEMS device manufacturing method and a MEMS device for improving surface flatness. By designing and accurately etching a support structure on the bottom silicon, it can ensure that the mirror structure can be stably suspended in the release cavity after release, avoiding the problem of surface unevenness caused by uneven support, and improving the manufacturing yield of MEMS micromirror devices.

[0007] According to one aspect of the present application, a method for manufacturing a MEMS device for improving surface flatness is provided, wherein the method comprises:

[0008] Obtain a base SOI wafer, and sequentially deposit a metal bottom electrode, a piezoelectric material, and a metal top electrode on the SOI wafer to obtain a substrate material, wherein the base SOI wafer sequentially comprises bottom silicon oxide, bottom silicon, buried oxide layer silicon oxide, top silicon, and top silicon oxide from bottom to top;

[0009] Etching the metal top electrode by ion beam etching to achieve patterning of the metal top electrode, etching the piezoelectric material by wet etching to achieve patterning of the piezoelectric material, and etching the metal bottom electrode by ion beam etching to achieve patterning of the metal bottom electrode;

[0010] Growing an insulating protective layer on the patterned substrate material, etching the insulating protective layer by inductively coupled plasma etching, and continuing to deposit a metal wiring layer, etching the metal wiring layer by ion beam etching or wet etching;

[0011] Etching the top silicon oxide by reactive ion etching, etching the top silicon by deep reactive ion etching, etching the buried oxide layer silicon oxide by reactive ion etching, and etching the bottom silicon oxide by reactive ion etching;

[0012] The bottom silicon is subjected to two deep reactive ion etchings to release the mirror structure, so as to complete the manufacture of the MEMS device.

[0013] In an embodiment of the present application, optionally, deep reactive ion etching is performed twice on the bottom silicon, including:

[0014] After applying a preset pattern of glue at the bottom silicon position corresponding to the support on the back of the mirror, a first deep reactive ion etching is performed, wherein the etching thickness of the first deep reactive ion etching is 10um-30um;

[0015] The entire micromirror back cavity of the bottom silicon after the first etching is subjected to a second deep reactive ion etching, wherein the etching thickness of the second deep reactive ion etching is 100um-500um.

[0016] In an embodiment of the present application, optionally, the thickness of the metal top electrode is 50nm-200nm, the material of the metal top electrode is one of Pt, Au, Cu, and Ti, the thickness of the piezoelectric material is 1um-5um, the piezoelectric material is one of lead zirconate titanate, aluminum nitride, zinc oxide, and lithium nickelate, and the thickness of the metal bottom electrode is 50nm-200nm, and the material of the metal bottom electrode is one of Pt, Au, Cu, and Ti.

[0017] In an embodiment of the present application, optionally, the piezoelectric material is etched by wet etching, including:

[0018] At least a buffered hydrofluoric acid etching solution and a buffered etching solution are mixed to obtain an etching solution, and the piezoelectric material is etched by wet etching based on the etching solution.

[0019] In an embodiment of the present application, optionally, growing an insulating protective layer on the patterned substrate material includes:

[0020] Silicon nitride is grown on the patterned substrate material as an insulating protective layer by plasma enhanced chemical vapor deposition, wherein the gas source for growing silicon nitride is SiH4 and NH3, the growth temperature is 200°C-400°C, and the thickness of the insulating protective layer is 300nm-500nm.

[0021] In an embodiment of the present application, optionally, etching the insulating protection layer by inductively coupled plasma etching includes:

[0022] CF4 and O2, or CHF3, or C2F6, or SF6 and He are selected as gas sources, and the insulating protection layer is etched by inductively coupled plasma etching.

[0023] In the embodiment of the present application, optionally, continuing to deposit a metal wiring layer includes:

[0024] One of Ag, Au, Cu and Pt is used as the metal material, and a metal wiring layer is deposited by magnetron sputtering. The thickness of the metal wiring layer is 100nm-300nm.

[0025] In the embodiment of the present application, optionally, the etching thickness of the top silicon oxide and the buried oxide layer silicon oxide are both 1 um, and the etching thickness of the top silicon is 5 um-50 um.

[0026] In an embodiment of the present application, optionally, etching the bottom silicon oxide by reactive ion etching includes:

[0027] CHF3 and SF6, or C2F6, are selected as etching source gases, and the bottom silicon oxide is etched by reactive ion etching to a thickness of 1 um.

[0028] According to another aspect of the present application, a MEMS device is provided, which is manufactured by the above-mentioned MEMS device manufacturing method for improving surface flatness.

[0029] By means of the above technical scheme, a method for manufacturing a MEMS device for improving surface flatness and a MEMS device are provided in an embodiment of the present application, wherein a base SOI wafer composed of bottom silicon oxide, bottom silicon, buried oxide layer silicon oxide, top silicon and top silicon oxide is obtained; a metal bottom electrode, a piezoelectric material and a metal top electrode are sequentially deposited on the top silicon to form a substrate material; the metal top electrode is etched by ion beam etching to achieve its patterning; the piezoelectric material is etched by wet etching to achieve its patterning; the metal bottom electrode is etched again by ion beam etching to complete its patterning; and a substrate material is grown on the patterned substrate material. Insulating protective layer; etching the insulating protective layer by inductively coupled plasma etching, and depositing a metal wiring layer; patterning the metal wiring layer by ion beam etching or wet etching; etching the top silicon oxide by reactive ion etching, etching the top silicon by deep reactive ion etching, and etching the buried oxide layer silicon oxide by reactive ion etching; also performing reactive ion etching on the bottom silicon oxide; applying glue at the bottom silicon position corresponding to the support on the back of the mirror, and performing the first deep reactive ion etching, and performing the second deep reactive ion etching on the entire micromirror back cavity of the bottom silicon after the first etching to release the mirror structure. The embodiment of the present application can accurately control the patterning process of electrodes and piezoelectric materials through ion beam etching and wet etching technology, reduce the roughness and unevenness of the material edge, and the growth and patterning process of the insulating protective layer helps to protect the underlying structural layer, reduce the pollution and damage that may be introduced in the subsequent process, thereby maintaining the flatness of the surface. Reactive ion etching and deep reactive ion etching technology can achieve high-precision etching of multilayer materials, control the etching depth and shape, reduce lateral erosion and bottom bulges during the etching process, and improve the flatness of the device surface. By designing and accurately etching the support structure on the bottom silicon, it can be ensured that the mirror structure can be stably suspended in the release cavity after release, avoiding the problem of surface unevenness caused by uneven support. In summary, the technical solution effectively improves the surface flatness of MEMS devices through measures such as precise patterning control, high-quality insulating protective layer, fine etching of multilayer materials, optimized design of support structure, and fine adjustment of process parameters.

[0030] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0032] Figure 1 A schematic flow chart of a method for manufacturing a MEMS device for improving surface flatness provided in an embodiment of the present application is shown;

[0033] Figure 2 A schematic cross-sectional view of a substrate material provided in an embodiment of the present application is shown;

[0034] Figure 3 A cross-sectional schematic diagram of a bottom silicon after one etching provided by an embodiment of the present application is shown;

[0035] Figure 4 A cross-sectional schematic diagram of a bottom silicon after secondary etching provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0037] In this embodiment, a method for manufacturing a MEMS device for improving surface flatness is provided. Figure 1 As shown, the method includes:

[0038] Step 101, obtain a basic SOI wafer, and deposit a metal bottom electrode, a piezoelectric material and a metal top electrode on the SOI wafer in sequence to obtain a substrate material, wherein the basic SOI wafer includes bottom silicon oxide, bottom silicon, buried oxide layer silicon oxide, top silicon and top silicon oxide from bottom to top.

[0039] Step 102, etching the metal top electrode by ion beam etching to achieve patterning of the metal top electrode, etching the piezoelectric material by wet etching to achieve patterning of the piezoelectric material, and etching the metal bottom electrode by ion beam etching to achieve patterning of the metal bottom electrode.

[0040] Step 103, growing an insulating protective layer on the patterned substrate material, etching the insulating protective layer by inductively coupled plasma etching, and continuing to deposit a metal wiring layer, etching the metal wiring layer by ion beam etching or wet etching.

[0041] Step 104, etching the top silicon oxide by reactive ion etching, etching the top silicon by deep reactive ion etching, etching the buried oxide layer silicon oxide by reactive ion etching, and etching the bottom silicon oxide by reactive ion etching.

[0042] Step 105 , performing deep reactive ion etching twice on the bottom silicon to release the mirror structure to complete the manufacture of the MEMS device.

[0043] In this embodiment, first, a base SOI wafer is obtained and multiple layers of materials are deposited, wherein the base SOI wafer includes bottom silicon oxide (as an insulating layer), bottom silicon (support layer), buried oxide silicon oxide (used to isolate the bottom silicon from the top silicon), top silicon (a main material layer for subsequent processing) and top silicon oxide (possibly used for protection or as an etching stop layer). A metal bottom electrode, a piezoelectric material and a metal top electrode are sequentially deposited on the top silicon to form a substrate material, such as Figure 2 As shown, these material layers will constitute the functional part of the MEMS device, in which the piezoelectric material can be used to achieve some form of mechanical-electrical conversion. Secondly, the electrodes and piezoelectric materials are patterned. Specifically, the metal top electrode is etched by ion beam, the piezoelectric material is wet etched, and the metal bottom electrode is etched again by ion beam to achieve precise patterning of these layers. This step is the key to making electrodes and piezoelectric structures with specific shapes and sizes. Next, an insulating protective layer is grown and a metal wiring layer is made. Among them, an insulating protective layer is grown on the patterned substrate material to protect the structure below and serve as a support for the subsequent metal wiring layer. The metal wiring layer is deposited on the insulating protective layer and patterned by ion beam etching or wet etching to form wires connecting various electrodes and possible other electronic components. Further, the top multilayer material is etched. Specifically, reactive ion etching (RIE) and deep reactive ion etching (DRIE) techniques are used to etch the top silicon oxide, top silicon, buried oxide layer silicon oxide and bottom silicon oxide in sequence. This step is to remove unnecessary materials and prepare for the subsequent release of the mirror structure. Finally, the bottom silicon is subjected to two deep reactive ion etchings to completely remove the portion below the bottom silicon, thereby releasing the mirror structure. The mirror structure usually includes the top silicon layer and the electrodes and piezoelectric material layers on it, which can move or vibrate freely after being released.

[0044] In an embodiment of the present application, the bottom silicon is subjected to two deep reactive ion etchings, including: a first deep reactive ion etching is performed after coating the bottom silicon position corresponding to the support on the back side of the mirror with a preset pattern, wherein the etching thickness of the first deep reactive ion etching is 10um-30um; and a second deep reactive ion etching is performed on the entire micromirror back cavity of the bottom silicon after the first etching, wherein the etching thickness of the second deep reactive ion etching is 100um-500um.

[0045] In the above embodiment, first, a layer of photoresist is coated according to a preset pattern at the bottom silicon position corresponding to the support on the back side of the mirror, and photolithography and development are performed to form the desired etching pattern. This pattern defines which areas of the bottom silicon will be retained to support the mirror structure and which areas will be etched away to release the mirror. Subsequently, the first deep reactive ion etching is performed. The purpose of this etching is to remove part of the bottom silicon to form a preliminary support structure and the outline of the release cavity. The etching thickness is usually between 10um and 30um, depending on the size of the mirror structure, the strength of the support structure and the required release cavity depth. After the first etching, if Figure 3 As shown in Figure 1, a series of raised support structures and preliminary release cavities surrounding them will be formed on the bottom silicon. These support structures will be used to support the mirror surface to prevent it from collapsing or deforming after release. After the first etching is completed, the second deep reactive ion etching is performed on the entire micromirror back cavity area, as shown in Figure 1. Figure 4 As shown, this etching is wider, aiming to further deepen the release cavity and ensure that the mirror structure can be fully released and move freely. The thickness of the second etching is usually between 100um and 500um, depending on the design requirements of the MEMS device and the expected application scenarios. A deeper release cavity can provide better mechanical properties and more stable mirror movement. After the second etching, the release cavity on the bottom silicon will reach the required depth, and the mirror structure will be fully released and suspended in the release cavity. At this point, the mirror can freely vibrate or deflect according to the drive of the piezoelectric material, thereby realizing the specific functions of the MEMS device. By performing two deep reactive ion etchings on the bottom silicon, the depth and shape of the release cavity can be precisely controlled to ensure that the mirror structure can be stably released and move freely. This manufacturing method is of great significance for improving the performance and reliability of MEMS devices.

[0046] By applying the technical solution of this embodiment, a basic SOI wafer consisting of bottom silicon oxide, bottom silicon, buried oxide layer silicon oxide, top silicon and top silicon oxide is obtained; a metal bottom electrode, a piezoelectric material and a metal top electrode are sequentially deposited on the top silicon to form a substrate material; the metal top electrode is etched by ion beam etching to achieve its patterning; the piezoelectric material is etched by wet etching to achieve its patterning; the metal bottom electrode is etched again by ion beam etching to complete its patterning; an insulating protective layer is grown on the patterned substrate material; and an inductively coupled plasma etching is performed. The insulating protection layer is etched by etching, and a metal wiring layer is deposited; the metal wiring layer is patterned by ion beam etching or wet etching; the top silicon oxide is etched by reactive ion etching, the top silicon is etched by deep reactive ion etching, and the buried oxide layer silicon oxide is etched by reactive ion etching; the bottom silicon oxide is also subjected to reactive ion etching; glue is applied to the bottom silicon position corresponding to the support on the back side of the mirror, and a first deep reactive ion etching is performed, and a second deep reactive ion etching is performed on the entire micromirror back cavity of the bottom silicon after the first etching to release the mirror structure. The embodiment of the present application can accurately control the patterning process of electrodes and piezoelectric materials through ion beam etching and wet etching technology, reduce the roughness and unevenness of the material edge, and the growth and patterning process of the insulating protective layer helps to protect the underlying structural layer, reduce the pollution and damage that may be introduced in the subsequent process, thereby maintaining the flatness of the surface. Reactive ion etching and deep reactive ion etching technology can achieve high-precision etching of multilayer materials, control the etching depth and shape, reduce lateral erosion and bottom bulges during the etching process, and improve the flatness of the device surface. By designing and accurately etching the support structure on the bottom silicon, it can be ensured that the mirror structure can be stably suspended in the release cavity after release, avoiding the problem of surface unevenness caused by uneven support. In summary, the technical solution effectively improves the surface flatness of MEMS devices through measures such as precise patterning control, high-quality insulating protective layer, fine etching of multilayer materials, optimized design of support structure, and fine adjustment of process parameters.

[0047] In an embodiment of the present application, optionally, the thickness of the metal top electrode is 50nm-200nm, the material of the metal top electrode is one of Pt, Au, Cu, and Ti, the thickness of the piezoelectric material is 1um-5um, the piezoelectric material is one of lead zirconate titanate, aluminum nitride, zinc oxide, and lithium nickelate, and the thickness of the metal bottom electrode is 50nm-200nm, and the material of the metal bottom electrode is one of Pt, Au, Cu, and Ti.

[0048] In an embodiment of the present application, optionally, the piezoelectric material is etched by wet etching, including: at least a buffered hydrofluoric acid etching solution and a buffered etching solution are mixed to obtain an etching solution, and the piezoelectric material is etched by wet etching based on the etching solution. Wherein, the piezoelectric material is wet-etched to achieve the patterning of the piezoelectric layer, and its corrosion environment is mainly various acidic solutions, mainly mixed solutions such as buffered hydrofluoric acid etching solution (Buffered HF, BHF) and buffered etching solution (Buffered Oxide Etch, BOE). BHF and BOE are both composed of different ratios of NH4F (ammonium fluoride) and HF (hydrofluoric acid), and can be further diluted with HCl (hydrochloric acid), HNO3 (nitric acid) and an appropriate amount of water to form a pre-etching solution, a main etching solution, a buffered etching solution and other etching solutions, and the wet etching of PZT is completed through a multi-pass wet etching process. The thickness of the etched PZT can be 1-5um.

[0049] In an embodiment of the present application, optionally, an insulating protective layer is grown on the patterned substrate material, including: growing silicon nitride as an insulating protective layer on the patterned substrate material by plasma enhanced chemical vapor deposition (PECVD), wherein the gas source for growing silicon nitride is SiH4 and NH3, the growth temperature is 200°C-400°C, and the thickness of the insulating protective layer is 300nm-500nm. Among them, PECVD can produce silicon nitride films with lower compressive stress and the reaction temperature is lower, so PECVD is used to grow silicon nitride as an insulating layer and a protective layer. The gas source for growing silicon nitride is SiH4+NH3, and the growth temperature is approximately 200°C-400°C. The thickness of the grown insulating layer can be 300nm-500nm.

[0050] In an embodiment of the present application, optionally, the insulating protective layer is etched using inductively coupled plasma etching, including: selecting CF4 and O2, or selecting CHF3, or selecting C2F6, or selecting SF6 and He as gas sources, and etching the insulating protective layer using inductively coupled plasma etching.

[0051] In an embodiment of the present application, optionally, continuing to deposit a metal wiring layer includes: using one of Ag, Au, Cu, and Pt as a metal material, and depositing the metal wiring layer by magnetron sputtering, wherein the thickness of the metal wiring layer is 100nm-300nm.

[0052] In the embodiment of the present application, optionally, the etching thickness of the top silicon oxide and the buried oxide layer silicon oxide are both 1 um, and the etching thickness of the top silicon is 5 um-50 um.

[0053] In an embodiment of the present application, optionally, the bottom silicon oxide is etched using reactive ion etching, including: selecting CHF3 and SF6, or selecting C2F6 as etching source gas, and etching the bottom silicon oxide using counter ion etching, with an etching thickness of 1 um.

[0054] Furthermore, an embodiment of the present application also provides a MEMS device, which is manufactured by the above-mentioned MEMS device manufacturing method for improving surface flatness.

[0055] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for manufacturing a MEMS device for improving surface flatness, characterized in that: The method comprises: Obtain a base SOI wafer, and sequentially deposit a metal bottom electrode, a piezoelectric material, and a metal top electrode on the SOI wafer to obtain a substrate material, wherein the base SOI wafer sequentially comprises bottom silicon oxide, bottom silicon, buried oxide layer silicon oxide, top silicon, and top silicon oxide from bottom to top; Etching the metal top electrode by ion beam etching to achieve patterning of the metal top electrode, etching the piezoelectric material by wet etching to achieve patterning of the piezoelectric material, and etching the metal bottom electrode by ion beam etching to achieve patterning of the metal bottom electrode; Growing an insulating protective layer on the patterned substrate material, etching the insulating protective layer by inductively coupled plasma etching, and continuing to deposit a metal wiring layer, etching the metal wiring layer by ion beam etching or wet etching; Etching the top silicon oxide by reactive ion etching, etching the top silicon by deep reactive ion etching, etching the buried oxide layer silicon oxide by reactive ion etching, and etching the bottom silicon oxide by reactive ion etching; The bottom silicon is subjected to two deep reactive ion etchings to release the mirror structure, so as to complete the manufacture of the MEMS device.

2. The method according to claim 1, characterized in that The bottom silicon is subjected to two deep reactive ion etchings, including: After applying a preset pattern of glue at the bottom silicon position corresponding to the support on the back of the mirror, a first deep reactive ion etching is performed, wherein the etching thickness of the first deep reactive ion etching is 10um-30um; The entire micromirror back cavity of the bottom silicon after the first etching is subjected to a second deep reactive ion etching, wherein the etching thickness of the second deep reactive ion etching is 100um-500um.

3. The method according to claim 2, characterized in that The thickness of the metal top electrode is 50nm-200nm, and the material of the metal top electrode is one of Pt, Au, Cu, and Ti. The thickness of the piezoelectric material is 1um-5um, and the piezoelectric material is one of lead zirconate titanate, aluminum nitride, zinc oxide, and lithium nickelate. The thickness of the metal bottom electrode is 50nm-200nm, and the material of the metal bottom electrode is one of Pt, Au, Cu, and Ti.

4. The method according to claim 2, characterized in that: Etching the piezoelectric material by wet etching, comprising: At least a buffered hydrofluoric acid etching solution and a buffered etching solution are mixed to obtain an etching solution, and the piezoelectric material is etched by wet etching based on the etching solution.

5. The method according to claim 2, characterized in that: Growing an insulating protective layer on the patterned substrate material, including: Silicon nitride is grown on the patterned substrate material as an insulating protective layer by plasma enhanced chemical vapor deposition, wherein the gas source for growing silicon nitride is SiH4 and NH3, the growth temperature is 200°C-400°C, and the thickness of the insulating protective layer is 300nm-500nm.

6. The method according to claim 5, characterized in that Etching the insulating protective layer by inductively coupled plasma etching, comprising: CF4 and O2, or CHF3, or C2F6, or SF6 and He are selected as gas sources, and the insulating protection layer is etched by inductively coupled plasma etching.

7. The method according to claim 2, characterized in that Continue to deposit metal wiring layers, including: One of Ag, Au, Cu and Pt is used as the metal material, and a metal wiring layer is deposited by magnetron sputtering. The thickness of the metal wiring layer is 100nm-300nm.

8. The method according to claim 2, characterized in that: The etching thickness of the top silicon oxide and the buried oxide layer silicon oxide are both 1 um, and the etching thickness of the top silicon is 5 um-50 um.

9. The method according to claim 2, characterized in that: Etching the bottom silicon oxide by reactive ion etching, comprising: CHF3 and SF6, or C2F6, are selected as etching source gases, and the bottom silicon oxide is etched by reactive ion etching to a thickness of 1 um.

10. A MEMS device, characterized in that: The device is manufactured by the method for manufacturing a MEMS device for improving surface flatness according to any one of claims 1 to 9.

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