Memory particle routing method

Abstract

The invention relates to the technical field of memory particle chips, in particular to a memory particle routing method, which comprises the following steps of: S1, applying a via hole at a routing starting position of a memory controller, setting a stub length L of the via hole, and establishing a correlation between the stub length L of the via hole and a signal wavelength lambda of a corresponding resonant frequency, so that L is equal to 1 / 4 * lambda, when 1 / 4 wavelength is equal to the length of the stub, the energy of the sine wave can be offset due to 180-degree phase difference when the sine wave passes through the stub, and a low-pass filtering effect is formed; s2, calculating the routing length Ls of the memory particle branches to ensure that the wavelength of sine waves filtered by the stub effect is greater than or equal to 4 * Ls, namely L is greater than or equal to Ls; s3, calculating the maximum value of the stub length L of the via hole; and S4, the length L range of the via hole stub is controlled. The method has the advantages that the bandwidth of the signal at the branch point of the memory grain address control routing is reduced, so that signal reflection is reduced, and the integrity of the signal is enhanced.

Description

Technical Field

[0001] The invention relates to the technical field of memory particle chips, in particular to a memory particle routing method. Background Art

[0002] Memory chip, as a universal form of dynamic random access memory (DRAM), has played a key role in many fields, including personal computers, servers, communication equipment and embedded systems. DDR memory chips, that is, double data rate memory, are famous for their high-speed synchronous transmission capabilities. With the advancement of technology, DDR memory has developed to the fifth generation, and its data transmission rate has been significantly improved. The single data line transmission rate of DDR5 can reach 6.4Gbps, and the address line rate is 3.2Gbps.

[0003] However, as the speed increases, signal integrity issues such as signal loss, reflection, and crosstalk become more prominent. In order to ensure the stable operation of memory chips, the routing design must be carefully optimized for signal integrity.

[0004] See also Figure 1 , the address control line of the memory chip adopts a one-to-many topology, that is, the address control line of one controller is connected to multiple loads. This structure is prone to impedance discontinuity at the branch point, resulting in signal reflection, especially at the first memory chip branch. In order to reduce this reflection and improve signal integrity, the routing of the address control line must be optimized to enhance the stability of the system. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a memory chip routing method to reduce signal reflection and optimize the routing design of address control lines, thereby enhancing the stability of the system.

[0006] In order to achieve the above purpose, a memory particle routing method is designed, and the method steps are as follows: S1. A via is added at the starting position of the memory controller routing, and the stub length L of the via is set, and the relationship between the stub length L of the via and the signal wavelength λ of the corresponding resonant frequency is established to satisfy L=1 / 4*λ, that is, when 1 / 4 wavelength is equal to the stub length, the energy of the sine wave will be offset due to the phase difference of 180 degrees when passing through the stub, forming a low-pass filtering effect; S2. The routing length Ls of the memory particle branch is calculated to ensure that the wavelength of the sine wave filtered by the stub effect is greater than or equal to 4*Ls, that is, L≥Ls; S3. The maximum value of the stub length L of the via is calculated to satisfy L≤c / (√ε*8*datarate), where c is the speed of light, ε is the node constant of the PCB medium, and datarate is the transmission data rate of the signal; S4. The stub length L of the via is controlled to be in the range of Ls≤L≤c / (√ε*8*datarate).

[0007] The memory particle routing method provided by the present invention also has other technical features, wherein the via is an electrical structure connecting two different routing layers.

[0008] The memory particle routing method provided by the present invention also has other technical features, wherein step S2 is specifically as follows: by confirming the sinusoidal wave frequency corresponding to 4*Ls times the wavelength and the frequency below, the signal corresponding to the routing length Ls is made close to the DC voltage, thereby reducing the reflection or the reflection amplitude is extremely small, ensuring that the filtered sinusoidal wave wavelength is greater than or equal to 4*Ls, so as to eliminate or reduce signal reflection, thereby improving signal integrity and enhancing system stability.

[0009] The memory particle routing method provided by the present invention has other technical features, wherein the step S3 is specifically as follows: the larger the residual length L of the via hole, the lower the corresponding filtering frequency, that is, the smaller the bandwidth of the signal, and the bandwidth of the signal is close to 0.5 / Rt, where Rt is the rise time of the signal. A smaller bandwidth will cause the rise time to become longer, which will affect the timing of the address control signal. The rise time of the address control line needs to be less than or equal to 1 / 4*UI, where UI is the minimum time interval for signal switching, UI=1 / datarate, where datarate is the transmission data rate of the signal, in bps, and the minimum bandwidth for stable operation of the system is 2*datarate, and the corresponding minimum bandwidth wavelength is obtained: λ=c / (√ε*2*datarate), where c is the speed of light, and ε is the node constant of the PCB medium. According to step S1, L≤c / (√ε*8*datarate).

[0010] Compared with the prior art, the present invention has the following advantages: By using the low-pass filtering effect produced by the via stubs, the bandwidth of the signal at the branch point of the memory chip address control routing can be effectively reduced, thereby reducing signal reflection and enhancing signal integrity. By accurately designing the length of the stubs, we can determine a length range within which reflections can be effectively reduced while meeting the minimum bandwidth requirements for stable system operation. In addition, this design method is also highly feasible in actual operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 , is an address control wiring diagram of memory particles in the prior art; Figure 2 , is a schematic diagram of the via structure of the present invention; Figure 3 , is the address control wiring diagram of the memory particle of the present invention; In the figure: 1 via stump L, 2 memory controller, 3 memory particles, 4 memory particle branch length Ls, 5 resistor R1, 6 reference voltage Vtt, 7 conductive path trace, 8 via. DETAILED DESCRIPTION

[0012] In order to make the purpose, principle and structure of the present invention more clear, it is further described below in conjunction with the drawings and specific embodiments.

[0013] See also Figure 2 , 3 The present invention provides a memory chip routing method, the main technical solution idea is: Determine the maximum bandwidth of the signal required to reduce reflections and the minimum bandwidth allowed for normal operation of the system. Determine the appropriate length range of the via stub 1 based on the above bandwidth requirements, and use the stub effect to form a low-pass filter to ensure normal operation of the system while reducing reflections. Specifically, the specific solution of the present invention is: The current topology of the memory chip address control line routing has multiple loads, such as Figure 1 As shown, at each branch, due to impedance discontinuity, a reflection signal will be generated, affecting the integrity of the signal. In the early DDR1 / 2 / 3 era, due to the low speed and chip process problems, the bandwidth of the output signal of the memory controller 2 was low, and the reflection signal was relatively small, and the impact on the signal was relatively small. With the increase of DDR4 / 5 speed and the improvement of chip process, the bandwidth of the signal is getting higher and higher, and the reflection is getting larger and larger, which will deteriorate the signal received by the memory chip 3 at the branch, and in serious cases, the memory chip 3 may not work normally.

[0014] The method of reducing signal bandwidth is usually to increase the length of the trace and add parallel capacitance at the load to form a low-pass filter effect to filter out high-frequency signals. However, for more than 20 address control lines, the trace density is very dense. It is difficult to increase the length by winding or increase the capacitance of each trace on the circuit board. Considering that the stub effect of the via is similar to the effect of a low-pass filter, such as Figure 2 As shown, a via is an electrical structure that connects two different routing layers and is very common during routing. If the length of the via stub 1 can be designed and adjusted to meet the filtering effect of a specific frequency, the purpose of reducing the signal bandwidth can be achieved.

[0015] First, drill a hole at the location where the memory controller 2 wiring comes out, such as Figure 3 As shown, since the length L of the via stump 1 and the signal wavelength λ of the corresponding resonant frequency are as shown in Formula 1, that is, the energy of a sine wave with a wavelength equal to the length 1 of the via stump L will be offset due to the phase difference of 180 degrees when passing through the stump, thereby forming a low-pass filtering effect.

[0016] L=1 / 4*λ (Formula 1).

[0017] Then confirm the routing length Ls 4 of the memory chip branch, such as Figure 1 As shown in the figure, the sine wave frequency corresponding to 4*Ls times wavelength and the frequency below are approximately DC voltage for the trace of Ls length 4, there is no reflection effect or the reflection amplitude is very small, and the frequency of the sine wave is the maximum bandwidth corresponding to reducing reflection. Therefore, as long as the sine wave wavelength filtered by the stub effect is greater than or equal to 4*Ls, that is, L≥Ls, the reflection can be eliminated or reduced.

[0018] Of course, the larger the L value is, the better it is. If it is too large, the corresponding filtering frequency will be lower, that is, the bandwidth of the signal will be smaller. The bandwidth of the signal is approximately equal to 0.5 / Rt, where Rt is the rise time of the signal. A smaller bandwidth will cause the rise time to become longer, which will affect the timing of the address control signal and may also cause the system to work unstable. Therefore, the rise time of the address control line generally needs to be less than or equal to 1 / 4*UI, where UI is the minimum time interval for signal switching, as shown in Formula 2: UI=1 / datarate (formula 2); Where datarate is the transmission data rate of the signal, in bps.

[0019] From the previous step, we can conclude that the minimum bandwidth for stable operation of the system is 2*datarate. According to formula 3, we can derive the corresponding minimum bandwidth wavelength as: λ=c / (√ε*2*datarate) (Formula 3); Where c is the speed of light and ε is the nodal constant of the PCB medium.

[0020] According to formula 1, we can conclude that L≤c / (√ε*8*datarate).

[0021] Based on the above, it can be concluded that the length L of the via stub 1 of the address control line needs to be controlled within Ls≤L≤c / (√ε*8*datarate). Assuming that the data rate of the address control line of the memory particle is 3.2Gbps, the dielectric constant ε of the PCB medium is 4, and the length Ls 4 at the particle branch is 2.5mm, then as long as the length L of the via stub 1 of the routing is within the range of 2.5mm≤L≤5.86mm, this can not only reduce the impact of reflection on signal integrity, but also ensure the stability of the system.

[0022] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes according to the technical solutions and novel concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A memory chip routing method, characterized in that The method steps are as follows: S1. Add vias at the starting position of the memory controller routing, set the stub length L of the vias, and establish the relationship between the stub length L of the vias and the signal wavelength λ of the corresponding resonant frequency, so that L=1 / 4*λ is satisfied. That is, when 1 / 4 wavelength is equal to the stub length, the energy of the sine wave will be offset by the phase difference of 180 degrees when passing through the stub, forming a low-pass filtering effect; S2. Calculate the routing length Ls of the memory chip branch to ensure that the wavelength of the sine wave filtered by the stub effect is greater than or equal to 4*Ls, that is, L≥Ls; S3. Calculate the maximum length L of the via stub, satisfying L≤c / (√ε*8*datarate), where c is the speed of light, ε is the node constant of the PCB medium, and datarate is the transmission data rate of the signal; S4. Control the length L of the via stump to be within the range of Ls≤L≤c / (√ε*8*datarate).

2. A memory chip routing method as claimed in claim 1, characterized in that The via is an electrical structure that connects two different routing layers.

3. A memory chip routing method as claimed in claim 1, characterized in that The step S2 is specifically as follows: by confirming the sine wave frequency corresponding to 4*Ls times the wavelength and the frequency below, the signal corresponding to the wiring length Ls is close to the DC voltage, thereby reducing the reflection or the reflection amplitude is extremely small, ensuring that the filtered sine wave wavelength is greater than or equal to 4*Ls, so as to eliminate or reduce signal reflection, thereby improving signal integrity and enhancing system stability.

4. A memory chip routing method as claimed in claim 1, characterized in that The step S3 is specifically as follows: the larger the length L of the via stump, the lower the corresponding filtering frequency, that is, the smaller the bandwidth of the signal, and the bandwidth of the signal is close to 0.5 / Rt, where Rt is the rise time of the signal. A smaller bandwidth will cause the rise time to become longer, which will affect the timing of the address control signal. The rise time of the address control line needs to be less than or equal to 1 / 4*UI, where UI is the minimum time interval for signal switching, UI=1 / datarate, where datarate is the transmission data rate of the signal, in bps, and the minimum bandwidth for stable operation of the system is 2*datarate. The corresponding minimum bandwidth wavelength is: λ=c / (√ε*2*datarate), where c is the speed of light, and ε is the node constant of the PCB medium. According to step S1, L≤c / (√ε*8*datarate).

Images