Driving circuit, display panel and display device

Abstract

The invention discloses a driving circuit, a display panel and a display device, and belongs to the technical field of liquid crystal display, and the driving circuit comprises a driving module which receives a first control signal to output a first driving signal; a common voltage line transmitting a common voltage; the first control module is connected with the driving module, the first control module is provided with a first output end and a first input end, and the first input end is connected with a common voltage line; in response to the first driving signal output by the driving module, the first control module conducts the first output end and the first input end after being conducted, so that the potential output by the first output end is equal to the potential of the common voltage. According to the driving circuit provided by the invention, the first driving signal is sent to the first control module through the driving module so as to connect the first output end of the first control module with the common voltage line, so that the voltage difference between the voltage output by the first output end and the common voltage is reduced, and the phenomenon that the picture of the display panel flashes white is improved; and the display effect of the display panel is further improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of liquid crystal display technology, and in particular to a driving circuit, a display panel, and a display device. Background Art

[0002] Liquid crystal display is a mainstream display device, widely used in various electronic devices, including computer monitors, televisions, smart phones, tablet computers, etc. It has become an indispensable part of modern society with its high-quality image display effect and convenient user experience. However, when the LCD monitor is turned on, the voltage input to the monitor is in a floating state, which causes the screen of the LCD monitor to flash white. Summary of the invention

[0003] The embodiment of the present application aims to provide a driving circuit to solve the technical problem in the prior art that a liquid crystal display will have a white screen flashing when it is powered on. Another embodiment of the present application aims to provide a display panel to solve the technical problem in the prior art that a liquid crystal display will have a white screen flashing when it is powered on. Another embodiment of the present application aims to provide a display device to solve the technical problem in the prior art that a liquid crystal display will have a white screen flashing when it is powered on.

[0004] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0005] In a first aspect, a driving circuit is provided, comprising:

[0006] A driving module, wherein the driving module is configured to receive a first control signal to output a first driving signal;

[0007] a common voltage line, the common voltage line being configured to transmit a common voltage;

[0008] a first control module, the first control module having a first control terminal, a first output terminal and a first input terminal, the first control terminal being connected to the driving module, the first input terminal being connected to the common voltage line, the first output terminal being connected to the display panel, and the first output terminal being configured to input a display signal into the display panel;

[0009] In response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal, so that the potential output by the first output terminal is equal to the potential of the common voltage.

[0010] In combination with the first aspect, the method further includes a second control module, the second control module is connected between the driving module and the first control module, and the second control module is configured to receive the first driving signal to send a second control signal to the first control module;

[0011] The second control signal is configured to turn on the first control module.

[0012] In combination with the first aspect, the second control module has a second control end, a second input end, and a second output end;

[0013] The first control terminal is connected to the second output terminal, the second control terminal is connected to the driving module, the second input terminal is connected to a third control signal line, and the third control signal line is configured to transmit an AVDD voltage.

[0014] In combination with the first aspect, the first control module has multiple first control modules, and the first input terminals and the first output terminals of the multiple first control modules are cascaded to each other to form a cascade logic circuit, and the first control terminals of the multiple first control modules are commonly connected to the second output terminal.

[0015] In combination with the first aspect, the driving module includes a first driver, the first driver having a first driving input terminal, a second driving input terminal and a first driving output terminal, the first driving output terminal is connected to the second control module, the second driving input terminal is grounded, and the first driving input terminal is configured to receive a second driving signal to output the first driving signal.

[0016] In combination with the first aspect, the driving module also includes a second driver, the second driver having a third driving input terminal, a fourth driving input terminal and a second driving output terminal, the third driving input terminal is connected to the working voltage line, the second driving output terminal is connected to the first driving input terminal, and the fourth driving input terminal is configured to receive a third driving signal to output the second driving signal.

[0017] In combination with the first aspect, the driving module also includes a third driver, the third driver having a fifth driving input terminal, a sixth driving input terminal and a third driving output terminal, the fifth driving input terminal is connected to the working voltage line, the third driving output terminal is connected to the fourth driving input terminal, and the sixth driving input terminal is configured to receive the first control signal to output the third driving signal.

[0018] In combination with the first aspect, the first control signal includes a clock signal.

[0019] In a second aspect, a display panel is provided, which is driven based on a driving circuit, and includes:

[0020] substrate;

[0021] a liquid crystal layer connected to the substrate;

[0022] A signal connection terminal, the signal connection terminal being connected to the substrate to input a display signal into the liquid crystal layer;

[0023] Among them, the driving circuit has a first output terminal and a first input terminal, the signal connection terminal is connected to the first output terminal, the first output terminal is connected to a common voltage line through the first input terminal, the common voltage line is configured to transmit a common voltage, and after the first output terminal is connected to the first input terminal, the potential output by the first output terminal is equal to the potential of the common voltage.

[0024] In a third aspect, a display device is provided, comprising:

[0025] A driving circuit as described in any one of the first aspects; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit through a common voltage line; or

[0026] A display panel as described in the second aspect; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, the common voltage is transmitted to a driving circuit through a common voltage line, and the display panel is connected to the driving circuit to receive a display signal.

[0027] One of the above technical solutions has the following advantages or beneficial effects:

[0028] The embodiment of the present application provides a driving circuit, including: a driving circuit, including: a driving module, the driving module is configured to receive a first control signal to output a first driving signal; a common voltage line, the common voltage line is configured to transmit a common voltage; a first control module, the first control module has a first control terminal, a first output terminal and a first input terminal, the first control terminal is connected to the driving module, the first input terminal is connected to the common voltage line, the first output terminal is connected to the display panel, and the first output terminal is configured to input a display signal to the display panel; wherein, in response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal so that the potential output by the first output terminal is equal to the potential of the common voltage. The driving circuit provided in the present application sends a first driving signal to the first control module through the driving module to realize connecting the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal and the common voltage, thereby improving the white flickering phenomenon of the screen of the display device, and further improving the display effect of the display device.

[0029] The embodiment of the present application provides a display panel, which is driven by a driving circuit and includes: a substrate; a liquid crystal layer, which is connected to the substrate; a signal connection terminal, which is connected to the substrate to input a display signal into the liquid crystal layer; wherein the driving circuit has a first output terminal and a first input terminal, the signal connection terminal is connected to the first output terminal, the first output terminal is connected to a common voltage line through the first input terminal, the common voltage line is configured to transmit a common voltage, and after the first output terminal is connected to the first input terminal, the potential output by the first output terminal is equal to the potential of the common voltage. The display panel provided by the present application, driven by the driving circuit, can reduce the voltage difference between the voltage input into the display panel and the common voltage, thereby improving the white flickering phenomenon of the display panel and further improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0031] Figure 1 A schematic diagram of module connections of a drive circuit provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the connection structure of the driving circuit provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the structure of a pixel electrode provided in some embodiments of the present application;

[0034] Figure 4 A schematic diagram of signal timing provided for some embodiments of the present application;

[0035] Figure 5 A schematic diagram of the connection between the display panel and the driving circuit provided in the embodiment of the present application;

[0036] Figure 6 A schematic diagram of a display device provided in an embodiment of the present application.

[0037] The reference numerals are as follows:

[0038] 100 - substrate, 101 - signal connection end, 200 - liquid crystal layer, 300 - driving circuit, 301 - first output end, 302 - first input end, 400 - voltage signal line. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. In the description of the present application, it is necessary to understand that the orientation or position relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0040] In some embodiments, the relevant technical personnel of the present application noticed that in an active matrix LCD (Liquid Crystal Display), on the same horizontal scan line, the gates of all TFTs (Thin-Film Transistors) are connected together, and the applied voltage is linked. Due to the existence of parasitic capacitance Cgs between the data line and the gate line (such as Figure 3 As shown in Figure 2, the coupling effect of the parasitic capacitance Cgs will cause the gate line to be coupled and raised by the data line when the LCD is powered on. When the voltage coupled to the gate line is greater than the threshold voltage Vgs of the TFT, the TFT will be turned on and the data line will leak to the pixel electrode. At this time, since the output channel is still in a floating state, that is, the voltage output by the output channel is uncertain, there is a certain voltage difference with the common voltage Vcom (such as Figure 4 As a result, the entire screen will flash white when the LCD is powered on.

[0041] To solve the above problem, the present application proposes to short-circuit all output channels input to the LCD surface when the LCD is powered on, thereby reducing the voltage difference between the voltage output by the output channel and the common voltage Vcom when the LCD is powered on, thereby improving the white flashing phenomenon of the startup screen, and the short-circuit state is released after the timing controller normally sends the data signal to the driving circuit.

[0042] The specific implementation methods of the present application are described below by way of examples:

[0043] like Figure 1 and Figure 2 As shown, the embodiment of the present application provides a driving circuit, including: a driving module, the driving module is configured to receive a first control signal to output a first driving signal; a common voltage line, the common voltage line is configured to transmit a common voltage Vcom; a first control module, the first control module has a first control terminal, a first output terminal and a first input terminal, the first control terminal is connected to the driving module, the first input terminal is connected to the common voltage line, the first output terminal is connected to the display panel, and the first output terminal is configured to input a display signal to the display panel; wherein, in response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal, so that the potential output by the first output terminal is equal to the potential of the common voltage; wherein the first output terminal is configured to input the display signal to the display panel. Specifically, the first driving signal output by the driving module is used to control the conduction state of the first input terminal and the first output terminal on the first driving module, so that when the LCD is powered on, the voltage output by the first output terminal and the common voltage Vcom are at the same potential, or the voltage difference between the two is reduced, so that the voltage output by the first output terminal can be unified, thereby improving the white flashing phenomenon of the LCD startup screen and improving the display effect of the LCD.

[0044] like Figure 1 and Figure 2 As shown, in an embodiment of the present application, a second control module is also included, the second control module is connected between the driving module and the first control module, the second control module is configured to receive the first driving signal to send a second control signal to the first control module; the second control signal is configured to turn on the first control module. Specifically, the conduction of the first control module is controlled by controlling the second control signal output by the second control module. At this time, the first input terminal is turned on with the first output terminal, and the voltage output by the first output terminal is the same as the potential of the common voltage Vcom, thereby improving the white flashing phenomenon of the LCD startup screen. When the second control module outputs a signal other than the second control signal, the first control module is cut off, that is, the connection between the first input terminal and the first output terminal is disconnected, and the first output terminal outputs a normal video signal to the LCD, thereby realizing the display of a video or image screen.

[0045] like Figure 2 As shown, in the embodiment of the present application, the second control module has a second control terminal, a second input terminal and a second output terminal; wherein the first control terminal is connected to the second output terminal, that is, Figure 2The first control module is connected to the P point in the circuit, the second control terminal is connected to the driving module, the second input terminal is connected to the third control signal line, and the third control signal line is configured to transmit the third control signal AVDD. Specifically, the first control module includes a P-type MOS tube Ts, the gate of the P-type MOS tube Ts is the first control terminal, the source is the first input terminal, and the drain is the first output terminal. The third control signal AVDD usually refers to an analog power supply voltage (Analog VDD), which is used to supply the power supply voltage of the analog circuit. When the first control module is a P-type MOS tube Ts, the third control signal AVDD is usually a high-level voltage. Therefore, when the second control module is turned on, the third control signal AVDD pulls up the potential at the gate of the P-type MOS tube Ts, so that the source and drain of the P-type MOS tube Ts can be turned on, that is, the voltage of the drain is equal to the potential of the common voltage Vcom connected to the source, thereby improving the display effect of the picture when the LCD is powered on.

[0046] In some embodiments, the first control module may also include an N-type MOS tube. In this case, the third control signal AVDD may be a low-level voltage. Therefore, when the second control module is turned on, the third control signal AVDD pulls down the potential at the gate of the N-type MOS tube, thereby enabling the source and drain of the N-type MOS tube to be turned on, i.e., the voltage of the drain is equal to the potential of the common voltage Vcom connected to the source, thereby improving the display effect of the picture when the LCD is powered on.

[0047] like Figure 2 As shown, in an embodiment of the present application, the first control module has multiple, the first input terminals and the first output terminals of the multiple first control modules are cascaded to each other to form a cascade logic circuit, and the first control terminals of the multiple first control modules are commonly connected to the second output terminal. Specifically, the first control module includes multiple MOS tubes, the source and drain of adjacent MOS tubes are connected in sequence, and the gates of all MOS tubes are commonly connected to form a first control terminal to form a cascade logic circuit. The first output terminal still receives the second control signal output by the second control module. Under the drive of the second control signal, all MOS tubes are fully turned on, so that the source and drain of all MOS tubes are connected to the common voltage line. Therefore, at this time, the potential of the output voltage of the first output terminal is equal to the potential of the common voltage Vcom, or the error is less than the threshold voltage Vgs of the TFT. Therefore, the cascade logic circuit can improve the white screen flashing phenomenon of the LCD when it is powered on, and improve the display effect of the LCD. It can be understood that the first control module may include multiple N-type MOS tubes or multiple P-type MOS tubes Ts. When the first control module is a cascade of multiple P-type MOS tubes Ts, the second control signal AVDD is a high-level signal; when the first control module is a cascade of multiple N-type MOS tubes, the second control signal AVDD is a low-level signal.

[0048] like Figure 2As shown, in the embodiment of the present application, the second control module includes an N-type MOS tube Tm, the gate of the N-type MOS tube Tm is the first control terminal, the source is the first input terminal, and the drain is the first output terminal. When the second control module is the N-type MOS tube Tm, the first drive signal is usually a low-level voltage. Therefore, when the drive module outputs the first drive signal, the first drive signal pulls down the potential at the gate of the N-type MOS tube Tm, so that the source and drain of the N-type MOS tube Tm can be turned on, that is, the third control signal AVDD in the third control signal line connected to the source can be transmitted to the first control terminal of the first control module, so that the first input terminal and the first output terminal of the first control module are turned on, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the picture when the LCD is powered on.

[0049] like Figure 1 and Figure 2 As shown, in the embodiment of the present application, the driving module includes a first driver F1, the first driver F1 has a first driving input terminal S, a second driving input terminal R and a first driving output terminal Q3, the first driving output terminal Q3 is connected to the second control module, the second driving input terminal R is grounded, and the first driving input terminal S is configured to receive a second driving signal to output a first driving signal. Specifically, the first driver F1 determines the first driving signal output by the first driving output terminal Q3 by the relationship between the second driving signal input by the first input terminal S and the ground signal. In the embodiment of the present application, the level of the output first driving signal can be determined by the level of the second driving signal. When the second driving signal changes from 0 to 1, the first driving input terminal S and the second driving input terminal R are grounded, and the first driving signal output by the first driving output terminal Q3 is a high level. At this time, the second control module, that is, the N-type MOS tube is turned on under the drive of the first driving signal, and further makes the third control signal AVDD turn on the first input terminal and the first output terminal of the first control module, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the screen when the LCD is powered on. When the second drive signal changes from 1 to 0, the first drive input terminal S and the second drive input terminal R are grounded, and the first drive signal output by the first drive output terminal Q3 is at a low level. At this time, the second control module is cut off, and the first control module is also cut off, that is, the first input terminal and the first output terminal of the first control module are not connected. At this time, the first output terminal can output a normal video signal to the LCD, thereby realizing the display of video or image screen.

[0050] In some embodiments, the first driver F1 includes an RS flip-flop. The RS flip-flop is a basic digital circuit component. The RS flip-flop can be used to store a bit of data (such as 0 or 1). By setting or resetting the input signal, the corresponding state (such as 0 or 1) can be maintained at the output of the flip-flop; or, the RS flip-flop can memorize the previous state and maintain the current output state when there is no input. Therefore, the RS flip-flop can be designed through the above functions to control the level of the output signal at the output end according to the signal relationship between the two input ends. Generally speaking, the high level is 1 and the low level is 0. The characteristic equation of the RS flip-flop is: Q n+1 =R'Q n +SQ' n , where R' represents the reset signal, S represents the set signal, and Q n+1 is the output state of the flip-flop, Q n It is the current state of the trigger. The initial state of the trigger is 0.

[0051] It should be known that in addition to the above functions, the RS trigger also has the following main functions, such as timing control, data synchronization and logic operation; because the RS trigger has two control input terminals, these inputs can be used to control the working state of the trigger. By changing the combination of the two input terminal signals, various timing control functions such as state transfer, clock synchronization, data latching, etc. can be realized. The RS trigger can also be used to synchronize the input data and the trigger clock signal to ensure that the input signal is stable and correctly transmitted to the output terminal at a specific clock edge. This synchronization capability is crucial for the stability and correctness of data in the timing circuit. The RS trigger can also be used in combinational logic circuits. By connecting the input signal and the output signal through a logic gate, different logic functions such as AND gates, OR gates, NOT gates, etc. can be realized. Therefore, in some embodiments, the function of the above-mentioned RS trigger can be used to control the level of the signal at the output terminal according to the relationship between the second drive signal and the ground signal.

[0052] like Figure 1 and Figure 2As shown, in the embodiment of the present application, the driving module also includes a second driver F2, the second driver F2 has a third driving input terminal T2, a fourth driving input terminal CLK2 and a second driving output terminal Q2, the third driving input terminal T2 is connected to the working voltage line, the second driving output terminal Q2 is connected to the first driving input terminal S, and the fourth driving input terminal CLK2 is configured to receive a third driving signal to output a second driving signal. Specifically, the second driver F2 determines the second driving signal output by the second driving output terminal Q2 through the relationship between the third driving signal input by the fourth driving input terminal CLK2 and the working voltage VDD input by the third driving input terminal T2. In the embodiment of the present application, the level of the output second driving signal can be determined by the level of the third driving signal. When the fourth driving input terminal CLK2 receives the third driving signal and changes from 0 to 1, the third driving input terminal T2 and the fourth driving input terminal CLK2 are connected to the working voltage VDD, and the output second driving signal is a high level. When the fourth driving input terminal CLK2 receives the third driving signal changing from 1 to 0, the third driving input terminal T2 and the fourth driving input terminal CLK2 are connected to the working voltage VDD, the second driver F2 is latched to maintain the original state, and the output maintains the original high level.

[0053] like Figure 1 and Figure 2As shown, in the embodiment of the present application, the driving module includes a third driver F3, the third driver F3 has a fifth driving input terminal T1, a sixth driving input terminal CLK1 and a third driving output terminal Q1, the fifth driving input terminal T1 is connected to the working voltage line, the third driving output terminal Q1 is connected to the fourth driving input terminal CLK2, and the sixth driving input terminal CLK1 is configured to receive a first control signal to output a third driving signal. Specifically, the third driver F3 determines the third driving signal output by the third driving output terminal Q1 through the relationship between the first driving signal input by the sixth driving input terminal CLK1 and the working voltage VDD input by the fifth driving input terminal T1. In the embodiment of the present application, the level of the output third driving signal can be determined by the level change of the first control signal. When the first control signal changes from 0 to 1, the fifth driving input terminal T1 and the sixth driving input terminal CLK1 are connected to the working voltage VDD, and the output third driving signal is at a high level. At this time, the second control module is turned off, and the first control module is also turned off, that is, the first input terminal and the first output terminal of the first control module are not turned on, and the first output terminal can output a normal video signal to the LCD, thereby realizing the display of the video or image screen. When the first control signal changes from 0 to 1 again, the fifth drive input terminal T1 and the sixth drive input terminal CLK1 are connected to the working voltage VDD, and the output third drive signal is low level. At this time, the second control module, that is, the N-type MOS tube is turned on under the drive of the first drive signal, and further makes the third control signal AVDD turn on the first input terminal and the first output terminal of the first control module, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the screen when the LCD is powered on.

[0054] In some embodiments, the second driver F2 and the third driver F3 include a T flip-flop, which is a commonly used type of flip-flop, consisting of two cross-coupled latches. The T flip-flop is used in a timing control circuit to control the state change of the output signal through a continuous pulse signal at its input end. When the pulse signal at the input end is at a high level, the output will be inverted at each rising edge of the clock pulse to achieve control of the timing logic.

[0055] In the embodiment of the present application, when the first driver F1 is an RS trigger, the second driver F2 and the third driver F3 are both T triggers (the third driver F3 is a T1 trigger, and the second driver F2 is a T2 trigger). The characteristic equation of the T trigger is: Q n+1 =T⊕Q n , where Q n+1 is the output state of the T flip-flop, Q nis the current state of the trigger, and T is the input signal. When the input signal T=0, the trigger keeps the current state unchanged; when the input signal T=1, the trigger state flips. When the sixth drive input terminal CLK1 of the third driver F3 inputs the first TP signal, the T1 trigger flips, and the third drive signal output by the third drive output terminal Q1 is 1, that is, the signal received by the fourth drive input terminal CLK2 is 1, then the T2 trigger flips, and the second drive signal output by the second drive output terminal Q2 is 1, that is, the signal received by the first drive input terminal S is 1. At this time, the characteristic equation of the RS trigger is: Q n+1 =R'Q n +SQ' n =Q' n , the first driving signal output by the first driving output terminal Q3 is 1, the N-type MOS tube Tm is turned on at a high level, and the potential at point p is at a high level. At this time, the source and drain of the P-type MOS tube Ts can be turned on, that is, the voltage of the drain is equal to the potential of the common voltage Vcom connected to the source.

[0056] When the sixth drive input terminal CLK1 of the third driver F3 inputs the second TP signal, the T1 trigger flips over, the third drive signal output by the third drive output terminal Q1 is 0, that is, the signal received by the fourth drive input terminal CLK2 is 0, the T2 trigger remains, and the second drive signal output by the second drive output terminal Q2 is 1, that is, the signal received by the first drive input terminal S is 1. At this time, the characteristic equation of the RS trigger is: Q n+1 =Q' n , the first driving signal outputted by the first driving output terminal Q3 is 0, the N-type MOS tube Tm is turned off at a low level, and the potential of the point p is at a low level. At this time, the source and drain of the P-type MOS tube Ts can be disconnected, that is, the voltage of the drain is not equal to the potential of the common voltage Vcom connected to the source. At the same time, the output channel outputs a given display voltage signal.

[0057] It should be known that in addition to the above functions, the T flip-flop also has the following main functions: frequency division, data storage, and timing transmission; specifically, the T flip-flop can be used as a frequency divider or divider to reduce the frequency of the clock signal to the required frequency. By providing an appropriate clock signal at the input of the T flip-flop and setting appropriate logical conditions, the flip-flop output can generate a corresponding frequency division signal. The T flip-flop can also be used in data storage applications to temporarily store the input data and keep it unchanged until the next clock pulse arrives. When the clock signal edge jumps (such as the rising edge or the falling edge), the T flip-flop latches the input data and outputs the latched data at the edge of the clock pulse. Accordingly, the T flip-flop can be used in the timing transmission circuit to transmit the data to the next stage according to the edge of the clock signal. When the clock signal arrives, the input data will be transmitted according to the state of the T flip-flop, and output to the next stage at the clock edge to achieve the timing transmission of the data.

[0058] Therefore, according to the level of the first control signal, the on and off states of the second control module and the third control module can be controlled respectively. When the first control signal is at a high level, the second control module is turned on under the drive of the first drive signal, and further causes the third control signal AVDD to turn on the first input terminal and the first output terminal of the first control module, so that the voltage output by the first output terminal is equal to the potential of the common voltage Vcom, thereby improving the display effect of the screen when the LCD is powered on. When the first drive signal is at a low level, the second control module and the first control module are both turned off, and at this time, the first output terminal can output a normal video signal to the LCD, thereby realizing the display of a video or image screen.

[0059] like Figure 2 As shown, in the embodiment of the present application, the first control signal includes a clock signal TP. Specifically, the clock signal TP is usually generated by a clock generator provided in the circuit, and the clock generator is usually composed of a crystal oscillator or an oscillation circuit, which can generate a square wave signal with a fixed frequency. By using the clock signal TP as the first control signal, the introduction of the signal can be reduced.

[0060] In some embodiments, the clock signal TP mainly has the functions of synchronous refresh, control scanning and driving, rhythm control and power consumption reduction in the liquid crystal display circuit. The liquid crystal display is usually composed of many pixels, and each pixel needs to be refreshed regularly to maintain the stability of the displayed image. The clock signal TP is used to synchronize the scanning and refreshing operations in the liquid crystal display circuit to ensure that the state of the pixel is updated in the correct time sequence, thereby generating a stable image. And the pixels of the liquid crystal display are usually arranged in a matrix structure of rows and columns. The clock signal TP is used to control the scanning circuit and the driving circuit, select and activate each row of pixels in a predetermined order, and apply the correct voltage and signal to each pixel, so as to realize the display of the image. Accordingly, the clock signal TP also provides a unified clock rhythm between various parts in the display system. Different signals and operations need to be processed and executed within the correct time interval to ensure accurate display results. The clock signal TP can be used as a time reference to coordinate the work of various parts to ensure the normal operation of the entire display system. The clock signal TP can also be used to control the activation time and duration of the pixel, as well as the working time of the driving circuit, to minimize power consumption.

[0061] like Figure 5 As shown, the embodiment of the present application also provides a display panel, which is driven based on a driving circuit 300 and includes: a substrate 100; a liquid crystal layer 200, which is connected to the substrate 100; a signal connection terminal 101, which is connected to the substrate 100 to input a display signal into the liquid crystal layer 200; wherein the driving circuit has a first output terminal and a first input terminal, the signal connection terminal 101 is connected to the first output terminal 301 in the driving circuit 300, the first output terminal 301 is connected to a common voltage line 400 through a first input terminal 302, the common voltage line 400 is configured to transmit a common voltage, and after the first output terminal 301 is connected to the first input terminal 302, the potential output by the first output terminal 301 is equal to the potential of the common voltage. Specifically, the driving circuit sends a first driving signal to the first control module through the driving module to connect the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal (i.e., the voltage input into the display panel) and the common voltage, thereby improving the white flashing phenomenon of the display panel and further improving the display effect of the display panel.

[0062] like Figure 6As shown, the embodiment of the present application also provides a display device, including: a driving circuit and a power integrated circuit as provided in any of the above embodiments, the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit through a common voltage line; or a display panel and a power integrated circuit as provided in the above embodiments, the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit through a common voltage line, and the display panel is connected to the driving circuit to receive a display signal. Specifically, the driving circuit sends a first driving signal to the first control module through the driving module to connect the first output terminal of the first control module to the common voltage line, thereby reducing the voltage difference between the voltage output by the first output terminal (i.e., the voltage input into the display panel) and the common voltage, thereby improving the white flickering phenomenon of the display device and further improving the display effect of the display device.

[0063] The above is a detailed introduction to a driving circuit, a display panel and a display device provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driving circuit, characterized in that: include: A driving module, wherein the driving module is configured to receive a first control signal to output a first driving signal; a common voltage line, the common voltage line being configured to transmit a common voltage; a first control module, the first control module having a first control terminal, a first output terminal and a first input terminal, the first control terminal being connected to the driving module, the first input terminal being connected to the common voltage line, the first output terminal being connected to the display panel, and the first output terminal being configured to input a display signal into the display panel; In response to the driving module outputting the first driving signal, the first output terminal is connected to the first input terminal, so that the potential output by the first output terminal is equal to the potential of the common voltage.

2. The driving circuit according to claim 1, characterized in that: Also includes a second control module, the second control module is connected between the driving module and the first control module, the second control module is configured to receive the first driving signal to send a second control signal to the first control module; The second control signal is configured to turn on the first control module.

3. The driving circuit according to claim 2, characterized in that: The second control module has a second control end, a second input end and a second output end; The first control terminal is connected to the second output terminal, the second control terminal is connected to the driving module, the second input terminal is connected to a third control signal line, and the third control signal line is configured to transmit an AVDD voltage.

4. The driving circuit according to claim 3, characterized in that: The first control modules include a plurality of first control modules, the first input terminals and the first output terminals of the plurality of first control modules are cascade-connected to each other to form a cascade logic circuit, and the first control terminals of the plurality of first control modules are commonly connected to the second output terminal.

5. The driving circuit according to claim 2, characterized in that: The driving module includes a first driver, the first driver has a first driving input terminal, a second driving input terminal and a first driving output terminal, the first driving output terminal is connected to the second control module, the second driving input terminal is grounded, and the first driving input terminal is configured to receive a second driving signal to output the first driving signal.

6. The driving circuit according to claim 5, characterized in that: The driving module also includes a second driver, which has a third driving input terminal, a fourth driving input terminal and a second driving output terminal, the third driving input terminal is connected to the working voltage line, the second driving output terminal is connected to the first driving input terminal, and the fourth driving input terminal is configured to receive a third driving signal to output the second driving signal.

7. The driving circuit according to claim 6, characterized in that: The driving module also includes a third driver, which has a fifth driving input terminal, a sixth driving input terminal and a third driving output terminal, the fifth driving input terminal is connected to the working voltage line, the third driving output terminal is connected to the fourth driving input terminal, and the sixth driving input terminal is configured to receive the first control signal to output the third driving signal.

8. The driving circuit according to claim 1, characterized in that: The first control signal includes a clock signal.

9. A display panel driven by a driving circuit, characterized in that: include: substrate; a liquid crystal layer connected to the substrate; A signal connection terminal, the signal connection terminal being connected to the substrate to input a display signal into the liquid crystal layer; Among them, the driving circuit has a first output terminal and a first input terminal, the signal connection terminal is connected to the first output terminal, the first output terminal is connected to a common voltage line through the first input terminal, the common voltage line is configured to transmit a common voltage, and after the first output terminal is connected to the first input terminal, the potential output by the first output terminal is equal to the potential of the common voltage.

10. A display device, characterized in that: include: A driving circuit according to any one of claims 1 to 8; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, and the common voltage is transmitted to the driving circuit through a common voltage line; or A display panel as claimed in claim 9; and a power integrated circuit, wherein the power integrated circuit is configured to generate a common voltage, the common voltage is transmitted to a driving circuit through a common voltage line, and the display panel is connected to the driving circuit to receive a display signal.

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