Memory device and operating method thereof

Abstract

A memory device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first word line and a plurality of second memory cells coupled to a second word line, the first word line and the second word line being adjacent to each other; and a memory controller configured to control the nonvolatile memory device. The memory controller is further configured to encode data to be programmed into a plurality of second memory cells based on a program state of each of the plurality of first memory cells, and encode data to be programmed into a second word line, a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0088659 filed in the Korean Intellectual Property Office on July 7, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to memory devices, and more particularly, to memory devices and methods of operating the same. Background Art

[0003] Semiconductor memory devices can be divided into volatile memory devices and non-volatile memory devices. Flash memory devices can be a representative example of non-volatile memory devices. In the case where a flash memory device stores multi-bit data in a single memory cell, it may be necessary to maintain an appropriate threshold voltage distribution to ensure data reliability. However, as the integration of memory increases, the threshold voltage distribution of a memory cell may change due to word line interference of adjacent memory cells. Summary of the invention

[0004] One or more example embodiments of the present disclosure provide a memory device and an operating method thereof, which may encode data to be programmed in a target word line in consideration of program states of adjacent word lines to improve reliability of the data.

[0005] According to one aspect of the present disclosure, a storage device includes: a nonvolatile memory device including a plurality of first memory cells coupled to a first word line and a plurality of second memory cells coupled to a second word line, the first word line and the second word line being adjacent to each other; and a storage controller configured to control the nonvolatile memory device. The storage controller is also configured to: encode data to be programmed into the plurality of second memory cells based on a programming state of each of the plurality of first memory cells, the programming state including a first state and a second state; and encode the data to be programmed into the second word line so that the first part of the data to be written into the first part of the plurality of second memory cells satisfies a first condition, and the second part of the data to be written into the second part of the plurality of second memory cells satisfies a second condition, the first part of the plurality of second memory cells is adjacent to the first part of the plurality of first memory cells in the first state, and the second part of the plurality of second memory cells is adjacent to the second part of the plurality of first memory cells in the second state.

[0006] According to one aspect of the present disclosure, a method for operating a storage device includes: checking whether a programming state of each of a plurality of first storage cells connected to a first word line is at least one of a first state and a second state, and encoding data to be programmed into a plurality of second storage cells connected to a second word line based on the programming state of each of the plurality of first storage cells. The first word line and the second word line are adjacent to each other. Encoding the data to be programmed into the plurality of second storage cells includes: encoding the data to be programmed into the second word line so that a first portion of the data to be written into a first portion of the plurality of second storage cells satisfies a first condition, and so that a second portion of the data to be written into a second portion of the plurality of second storage cells satisfies a second condition.

[0007] According to one aspect of the present disclosure, a method for operating a storage device includes: classifying a programming state of each of a plurality of first storage cells connected to a first word line into a plurality of states, encoding data to be programmed into a plurality of second storage cells connected to a second word line based on the programming state of each of the plurality of first storage cells, and programming the encoded programming data into the plurality of second storage cells. Encoding the data to be programmed into the plurality of second storage cells includes: encoding the data to be programmed into the plurality of second storage cells so that a first portion of the data to be written into a first portion of the plurality of second storage cells adjacent to a first storage cell in a first state among the plurality of states satisfies a first condition, and so that a second portion of the data to be written into a second portion of the plurality of second storage cells adjacent to a first storage cell in a second state among the plurality of states satisfies a second condition.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description which follows, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a storage system according to an example embodiment;

[0011] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A block diagram of a non-volatile memory device is shown;

[0012] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A circuit diagram of a memory block of a memory cell array shown;

[0013] Figure 4 is a diagram showing the eighth string selection line from Figure 3 A circuit diagram of a cell string selected from among the cell strings of the memory block shown;

[0014] Figure 5 is a diagram showing an example of threshold voltage distribution depending on a program state of a memory cell according to an embodiment;

[0015] Figure 6 is a flow chart illustrating a method of operating a storage controller according to an example embodiment;

[0016] Fig. 7A and Figure 7B is a diagram showing a method according to an embodiment of the present invention. Figure 6 FIG. 1 is a diagram showing an example of operations S110 to S130;

[0017] Fig. 8A and Figure 8B is a diagram showing a method according to an embodiment of the present invention. Figure 6 FIG. 1 is a diagram showing an example of operations S110 to S130;

[0018] Fig. 9 is a block diagram illustrating a configuration of a storage controller according to an example embodiment;

[0019] Fig.10 is a diagram showing a method according to an embodiment of the present invention. Fig. 9 The block diagram of the shaping encoder shown;

[0020] Fig.11A is a diagram showing a portion of data programmed in an n-th word line as a neighboring word line in a TLC cell and a programming state corresponding thereto according to an embodiment;

[0021] Fig. 11B is a diagram showing a method according to an embodiment of the present invention. Fig.11A A diagram of programming mode information for each adjacent cell shown in;

[0022] Fig. 11C is a diagram showing a portion of user data to be programmed to an n+1th word line as a program target word line and a program state corresponding thereto according to an embodiment;

[0023] FIG. 12A to FIG. 12C is a diagram showing encoding of data of a first logical page to be programmed to Fig. 11C one of the plurality of data in the n+1th word line shown;

[0024] Fig.13A and Fig. 13Bis a diagram showing encoding of data of a second logical page to be programmed to Fig. 11C one of the plurality of data in the n+1th word line shown;

[0025] FIG. 14A to FIG. 14C is a diagram showing encoding of data of a third logical page to be programmed to Fig. 11C one of the plurality of data in the n+1th word line shown; and

[0026] Fig.15 is a diagram illustrating an example of the operation of a state shaping circuit according to an example embodiment. DETAILED DESCRIPTION

[0027] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, it will be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and structures have been omitted for the purpose of clarity and conciseness.

[0028] In the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that the singular form of the noun corresponding to the project may include one or more things, unless the relevant context clearly indicates otherwise. As used herein, each phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" may include any possible combination of the items listed together in a corresponding phrase. As used herein, terms such as "1st" and "2nd" or "first" and "second" may be used to simply distinguish the corresponding component from other components, and do not limit the component in other aspects (e.g., importance or order). It should be understood that if the term "operably" or "communicatively" is used to mention that an element (e.g., a first element) is "coupled", "coupled to" another element, "connected" or "connected to" another element with another element using or without the term "operably" or "communicatively", it means that the element can be directly (e.g., wired), wirelessly or via a third element coupled to the other element.

[0029] References throughout this disclosure to "one embodiment," "an embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in conjunction with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language throughout this disclosure may (but do not necessarily) all refer to the same embodiment.

[0030] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged. In addition, some blocks can be combined or omitted. The attached claims present the elements of each block in an example order and are not meant to be limited to the specific order or hierarchy presented.

[0031] The embodiments of the present invention may be described and illustrated in accordance with the blocks shown in the figure, which perform one or more functions described. These blocks may be referred to herein as units or modules, etc., or as names such as devices, logic, circuits, controllers (e.g., storage controllers), counters, comparators, generators, converters, etc., and may be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0032] Hereinafter, example embodiments are described with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram illustrating a storage system 10 according to an example embodiment.

[0034] refer to Figure 1 , a storage system 10 according to example embodiments may include a host 1500 and a storage device 1000 .

[0035] The host 1500 may write data in the memory device 1000 and / or read data stored in the memory device 1000. To this end, the host 1500 may transmit a command CMD, an address ADDR, and user data DATA to the memory device 1000.

[0036] The memory device 1000 may be provided as a data storage device of the host 1500. The memory device 1000 may include a memory controller 1100 and a nonvolatile memory device 1200.

[0037] The memory controller 1100 may control the overall operation of the memory device 1000. For example, the memory controller 1100 may control the nonvolatile memory device 1200 to perform a program operation, a read operation, etc. based on a command CMD, an address ADDR, and user data DATA received from the host 1500.

[0038] The non-volatile memory device 1200 may be and / or may include, but is not limited to, a flash memory, a magnetic random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FeRAM), a resistive RAM (ReRAM), etc. However, the present disclosure is not limited thereto in this regard. That is, reference Figure 1 The NAND flash memory devices described are merely examples, and other examples are possible.

[0039] The nonvolatile memory device 1200 may include a memory cell array 1210. The memory cell array 1210 may include a plurality of memory blocks. Figure 1 , for ease of description, a single memory block BLK1 is shown. However, it should be understood that the memory cell array 1210 may include additional memory blocks.

[0040] The memory block BLK1 may include a plurality of memory cells connected to each of a plurality of word lines (e.g., a first word line WL1 to an nth word line WLn, and an n+1th word line WLn+1, where n is a positive integer greater than zero (0)). During a programming operation, user data DATA may be stored in the plurality of memory cells connected to each of the plurality of word lines. In an example embodiment, a programming operation may be sequentially performed from the first word line WL1 to the n+1th word line WLn+1. However, this is merely exemplary, and the direction in which the programming operation is performed may vary according to an example embodiment.

[0041] In example embodiments, during a program operation, the memory controller 1100 may encode user data DATA provided from the host 1500 to have different data conditions according to program states of adjacent word lines. The encoded data EN_DATA may be transmitted to the nonvolatile memory device 1200 and then programmed into a plurality of memory cells.

[0042] In example embodiments, during a read operation, the memory controller 1100 may read the encoded data EN_DATA from the nonvolatile memory device 1200. The memory controller 1100 may decode the encoded data EN_DATA into original user data DATA and may transmit the decoded data to the host 1500.

[0043] In an embodiment, the memory controller 1100 may include a state shaping circuit 1150. The state shaping circuit 1150 may include a shaping encoder 1151 and a shaping decoder 1153.

[0044] For ease of description, the Figure 1 An example is provided in which a programming operation is sequentially performed from the first word line WL1 to the n+1th word line WLn+1 in the memory block BLK1. In addition, an example is provided in which the first word line WL1 to the nth word line WLn are in a programmed state and a programming operation is to be performed on the n+1th word line WLn+1. In addition, an example is provided in which the n+1th word line WLn+1 is a target word line.

[0045] In an embodiment, the shaping encoder 1151 can encode data to be programmed into a memory cell (hereinafter referred to as a "target cell") connected to the n+1th word line WLn+1 (e.g., the target word line) based on the programming state of a memory cell (hereinafter referred to as a "neighboring cell") connected to the nth word line WLn adjacent to the target word line.

[0046] In example embodiments, the shaping encoder 1151 may encode data to be programmed into the target cell based on a programming state of a neighboring cell corresponding to each target cell.

[0047] For example, the shaping encoder 1151 may determine whether the programming state of each adjacent cell is the first state P_L or the second state P_H. The first state P_L may include at least one programming state corresponding to a relatively low threshold voltage among the programming states of the memory cell. The second state P_H may include at least one programming state corresponding to a relatively high threshold voltage among the programming states of the memory cell.

[0048] The shaping encoder 1151 can encode data to be programmed into the target cell so that data satisfying a first data condition can be programmed into the target cell corresponding to the adjacent cell in the first state P_L, and data satisfying a second data condition can be programmed into the target cell corresponding to the adjacent cell in the second state P_H.

[0049] The first data condition may be a data condition that data to be programmed into a target cell corresponding to an adjacent cell in the first state P_L has a programming pattern that excludes the first shaping target pattern. The second data condition may be a data condition that data to be programmed into a target cell corresponding to an adjacent cell in the second state P_H has a programming pattern that excludes the second shaping target pattern. The first data condition may be referred to as a "first condition" and the second data condition may be referred to as a "second condition".

[0050] For example, the first shaping target mode may be a programming state corresponding to the highest (e.g., maximum) threshold voltage among the programming states of the memory cell. The second shaping target mode may be a programming state corresponding to the lowest (e.g., minimum) threshold voltage among the programming states of the memory cell. However, the present disclosure is not limited thereto in this regard, and the first shaping target mode and the second shaping target mode may be set to vary according to example embodiments. For example, the first shaping target mode may be a programming state corresponding to the next highest threshold voltage among the programming states of the memory cell, and the second shaping target mode may be a programming state corresponding to the next lowest threshold voltage among the programming states of the memory cell.

[0051] According to example embodiments, the shaping encoder 1151 may transmit encoding related information used in generating the encoding data EN_DATA to the nonvolatile memory device 1200 .

[0052] The shaping decoder 1153 may receive the encoded data EN_DATA from the nonvolatile memory device 1200. The shaping decoder 1153 may decode the original user data DATA from the encoded data EN_DATA using the encoding related information.

[0053] As described above, the memory device 1000 according to the example embodiment can encode the data to be programmed into the target word line to have different data conditions according to the programming state of the adjacent word line. For example, the memory device 1000 can encode the data to be programmed into the target cell so that the data satisfying the first data condition can be programmed into the target cell corresponding to the adjacent cell in the first state P_L, and the data satisfying the second data condition can be programmed into the target cell corresponding to the adjacent cell in the second state P_H. Therefore, the interference between the word lines can be reduced during the programming operation, thereby improving the reliability of the data.

[0054] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 FIG. 1 is a block diagram of a nonvolatile memory device 1200. Figure 2 , the nonvolatile memory device 1200 may include a memory cell array 1210 , an address decoder 1220 , a page buffer circuit 1230 , a data input / output (I / O) circuit 1240 , a voltage generator 1250 , and control logic 1260 .

[0055] The memory cell array 1210 may include a plurality of memory blocks (e.g., a first memory block BLK1, a second memory block BLK2 to an nth memory block BLKn). Each memory block may include a plurality of memory cells connected to a plurality of word lines. In an embodiment, the memory cells connected to the same word line may constitute a single physical page. When multi-bit data is stored in each memory cell, each word line may include a plurality of logical pages.

[0056] Each memory block (e.g., BLK1) can be connected to a string selection line SSL, multiple word lines (e.g., a first word line WL1 to an n-1th word line WLn-1, an nth word line WLn, and an n+1th word line WLn+1 to an mth word line WLm, where m is a positive integer greater than n), and a ground selection line GSL.

[0057] The address decoder 1220 may be connected to the memory cell array 1210 through the selection lines SSL and GSL and the plurality of word lines WL1 to WLm. The address decoder 1220 may select a word line during a programming and / or reading operation. The address decoder 1220 may receive a word line voltage from the voltage generator 1250 and may provide a programming voltage and / or a reading voltage to the selected word line.

[0058] The page buffer circuit 1230 may be connected to the memory cell array 1210 through bit lines (e.g., first bit line BL1, second bit line BL2 to z-th bit line BLz, where z is a positive integer greater than zero (0)). The page buffer circuit 1230 may temporarily store data to be stored in the memory cell array 1210 and / or data read from the memory cell array 1210.

[0059] The I / O circuit 1240 may be internally connected to the page buffer circuit 1230 through a data line, and may be externally connected to a memory controller (eg, Figure 1 storage controller 1100).

[0060] In an example embodiment, the I / O circuit 1240 may receive encoding data EN_DATA from the memory controller 1100 during a program operation. In this example, the I / O circuit 1240 may also receive encoding related information used when generating the encoding data EN_DATA. Alternatively or additionally, the I / O circuit 1240 may provide the encoding data EN_DATA read from the memory cell array 1210 to the memory controller 1100 during a read operation. In this example, the I / O circuit 1240 may also provide the encoding related information read from the memory cell array 1210 to the memory controller 1100. The encoding related information may be information about an encoding code used when generating the encoding data EN_DATA.

[0061] The voltage generator 1250 may generate a word line voltage required for reading and / or writing data and a voltage to be supplied to a body in which a memory cell is formed under the control of the control logic 1260. The voltage generator 1250 may generate a selection line voltage supplied to the selection lines SSL and GSL during a read operation and / or a program operation.

[0062] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 2 The circuit diagram of the memory block BLK1 of the memory cell array is shown. Figure 3 , the memory block BLK1 may include 11th to 8zth cell strings STR11 to STR8z located between the first to zth bit lines BL1 to BLz and the common source line CSL. In example embodiments, the 11th to 8zth cell strings STR11 to STR8z may be formed in a direction perpendicular to the substrate (eg, z direction).

[0063] Each cell string may include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST.

[0064] The string selection transistors SST may be connected to the first to eighth string selection lines SSL1 to SSL8, respectively. The ground selection transistors GST may be connected to the first to eighth ground selection lines GSL1 to GSL8, respectively. The string selection transistors SST may be connected to the first to z-th bit lines BL1 to BLz. The ground selection transistors GST may be connected to the common source line CSL.

[0065] The first word line WL1 may be disposed on the first to eighth ground selection lines GSL1 to GSL8. Memory cells MC disposed at the same height from the substrate may be connected to the first word line WL1. Similarly, memory cells disposed at the same height from the substrate may be connected to each of the second to eighth word lines WL2 to WL8.

[0066] Figure 4 is a diagram showing the eighth string selection line SSL8 from Figure 3 FIG. 1 is a circuit diagram of a selected cell string among the cell strings of the memory block BLK1 . Figure 5 1 is a diagram showing an example of threshold voltage distribution depending on a program state of a memory cell according to an embodiment. For ease of description, an example is provided in which the first to fourth word lines WL1 to WL4 are word lines that have completed a program operation, and the fifth word line WL5 is a target word line to perform a program operation.

[0067] refer to Figure 4, the 81st cell string STR81 to the 8zth cell string STR8z may be selected by the eighth string selection line SSL8. The 81st cell string STR81 to the 8zth cell string STR8z may be connected to the first bit line BL1 to the zth bit line BLz, respectively. Memory cells selected by a single string selection line and connected to a single word line may constitute a single physical page.

[0068] Multi-bit data may be stored in each memory cell. As used herein, multiple logical pages may correspond to a single word line. For example, when the number of bits stored in each memory cell is "a", a single word line may have "a" logical pages, where "a" is a positive integer greater than zero (0).

[0069] For example, each memory cell may be a triple-level cell (TLC) storing three (3) bits of data (e.g., a=3). In this example, a single word line may have three (3) logical pages. In addition, each memory cell storing three (3) bits of data may have a threshold voltage corresponding to an erase state E and one of seven (seven) programming states (e.g., a first programming state P1, a second programming state P2, a third programming state P3, a fourth programming state P4, a fifth programming state P5, a sixth programming state P6, a seventh programming state P7), as shown in FIG. Figure 5 shown.

[0070] In the case of TLC, after the program operation is completed, the memory cells connected to the fourth word line WL4 may have the following Figure 5 However, when a program operation is performed on the fifth word line WL5 (target word line), the threshold voltage distribution of memory cells connected to the fourth word line WL4 (adjacent word line) may be affected.

[0071] As used herein, a memory cell connected to the fourth word line WL4 may be referred to as a "victim cell," and a memory cell connected to the fifth word line WL5 may be referred to as an "aggressive cell." An aggressor cell may refer to a cell that has an influence on other cells, and a victim cell may refer to a cell that is affected by an aggressor cell. Due to lateral charge diffusion and word line (WL) interference caused by the physical influence of the aggressor cell, the threshold voltage of the victim cell may shift from the originally programmed threshold voltage.

[0072] This change in threshold voltage may be significant when the programmed state of the victim cell is a higher programmed state and the programmed state of the aggressor cell is a lower programmed state and / or when the programmed state of the victim cell is a lower programmed state and the programmed state of the adjacent aggressor cell is a higher programmed state.

[0073] The memory device 1000 according to the example embodiment may encode the data to be programmed into the fifth word line WL5 (target word line) based on the programming state of the fourth word line WL4 (neighboring word line) to prevent such a change in the threshold voltage of the victim cell. In this embodiment, the encoding operation may be performed to reduce the difference between the threshold voltages of the victim cell and the attacking cell.

[0074] For example, the memory device 1000 may assign the victim cell to the first state P_L and / or the second state P_H based on the programming state of the victim cell. The memory device 1000 may encode the data to be programmed into the attack cell so that the data satisfying the first data condition is programmed into the attack cell corresponding to the victim cell in the first state P_L, and the data satisfying the second data condition is programmed into the attack cell corresponding to the victim cell in the second state P_H. Therefore, the change in the threshold voltage of the victim cell can be reduced during the programming operation, thereby potentially improving the reliability of the data.

[0075] Figure 6 is a flowchart illustrating a method of operating the memory controller 1100 according to example embodiments. Fig. 7A and Figure 7B is a diagram showing a method according to an embodiment of the present invention. Figure 6 FIG. 1 is a diagram showing an example of operations S110 to S130 .

[0076] For ease of description, an example is provided in which a target word line is an n+1th word line WLn+1 and an adjacent word line is an nth word line WLn.

[0077] In operation S110 , the memory controller 1100 may check a program state of each adjacent cell connected to an n-th word line WLn (adjacent word line).

[0078] For example, Fig. 7A Memory cells (e.g., first memory cell MC1, second memory cell MC2, third memory cell MC3, fourth memory cell MC4, fifth memory cell MC5, sixth memory cell MC6, seventh memory cell MC7, and eighth memory cell MC8) corresponding to the first bit line BL1 to the eighth bit line BL8 among the memory cells connected to the nth word line WLn are shown. For example, the memory cells MC1 to MC8 may be three-level cells (TLC). In this example, the programming state of each memory cell may correspond to one of the erase state E and the first programming state P1 to the seventh programming state P7. For ease of description, an example is provided in which the first memory cell MC1 to the eighth memory cell MC8 connected to the nth word line WLn of the adjacent word line are programmed to states E, P1, P2, P3, P4, P5, P6, and P7, respectively.

[0079] In example embodiments, the memory controller 1100 may check a programming state of each of the memory cells MC1 to MC8 connected to the nth word line WLn, and may classify the programming state of each cell into a first state P_L and a second state P_H. The first state P_L may be a programming state corresponding to a low threshold voltage among programming states of the memory cell, and the second state P_H may be a programming state corresponding to a high threshold voltage among programming states of the memory cell.

[0080] In an exemplary embodiment, when the number of bits stored in the memory cell is "a", the erase state and states P1 to P2 a -1 -1 can each be the first state P_L, and state P2 a-1 To P2 a -1 can each be the second state P_H.

[0081] For example, Fig. 7A As shown, the memory controller 1100 may check the programming state of each memory cell, and may classify each of the states E, P1, P2, and P3 as a first state P_L, and may classify each of the states P4, P5, P6, and P7 as a second state P_H. In this example, the memory controller 1100 may generate programming mode information based on whether the programming state of each memory cell is the first state P_L and / or the second state P_H.

[0082] In operation S120 , the memory controller 1100 may determine a shaping target pattern of each target cell connected to an n+1th word line WLn+1 (eg, a target word line).

[0083] For example, the memory controller 1100 may determine that, among the target cells, the target cells corresponding to the neighboring cells having the first state P_L as the programming state have the first shaping target pattern. Alternatively or additionally, the memory controller 1100 may determine that, among the target cells, the target cells corresponding to the neighboring cells having the second state P_H as the programming state have the second shaping target pattern.

[0084] In an example embodiment, the first shaping target mode may be a programming state corresponding to the highest (e.g., maximum) threshold voltage among programming states of each memory cell, and the second shaping target mode may be a programming state corresponding to an erased state among programming states of the memory cell. However, this is merely exemplary, and example embodiments are not limited thereto. As another example, the first shaping target mode may be a programming state corresponding to a second highest threshold voltage, and the second shaping target mode may be a programming state corresponding to a second lowest threshold voltage. The first shaping target mode corresponding to the first state and the second shaping target mode corresponding to the second state may be predetermined when designing the memory device 1000. Alternatively or additionally, the first shaping target mode and the second shaping target mode may be updated by the memory controller 1100 based on the data environment and other characteristics of the host 1500.

[0085] For example, refer to Fig. 7A , the storage controller 1100 may determine the state P7 as the shaping target pattern of the target cells MC1, MC2, MC3, and MC4 corresponding to the neighboring cells having the first state P_L as the programming state. The storage controller 1100 may determine the erase state as the shaping target pattern of the target cells MC5, MC6, MC7, and MC8 corresponding to the neighboring cells having the second state P_H as the programming state. The storage controller 1100 may generate target pattern information based on the determined shaping target pattern.

[0086] In operation S130 , the memory controller 1100 may encode user data to be programmed into an n+1th word line WLn+1 (eg, a target word line).

[0087] For example, the memory controller 1100 may encode user data to be programmed into the n+1th word line WLn+1 based on the first data condition and the second data condition.

[0088] In an example embodiment, the memory controller 1100 may encode the user data to be programmed based on the state of the neighboring cells to satisfy the first data condition or the second data condition. For example, the data to be programmed into the target cell corresponding to the neighboring cell in the first state P_L may be encoded to satisfy the first data condition. The data to be programmed into the target cell corresponding to the neighboring cell in the second state P_H may be encoded to satisfy the second data condition.

[0089] The first data condition may be a data condition that prevents a target cell corresponding to an adjacent cell in the first state P_L from having a first shaped target pattern. The second data condition may be a data condition that prevents a target cell corresponding to an adjacent cell in the second state P_H from having a second shaped target pattern.

[0090] That is, Fig. 7A As shown in the example embodiment of , when the first shaping target mode is in state P7, the first data condition may be a data condition that causes the programming mode corresponding to the encoded data to have a programming mode other than state P7. For example, when the programming data corresponding to state P7 is "

[011] ", the first data condition may be a data condition that prevents the encoded data from being "

[011] ".

[0091] For example, when the second shaping target pattern is in the erased state E, the second data condition may be a data condition that prevents the programming pattern corresponding to the data after encoding from having the erased state E. For example, when the programming data corresponding to the erased state is "

[111] ", the second data condition may be a data condition that prevents the encoded data from being "

[111] ".

[0092] In an example embodiment, when the user data to be programmed into the target word line is encoded, the memory controller 1100 may use a plurality of code words. The memory controller 1100 may provide encoded data to which a code word that satisfies the first data condition and the second data condition to the greatest extent (e.g., maximally) among the plurality of code words is applied as an encoding result value. In an example embodiment, the plurality of code words may be polarity-encoded codes.

[0093] Figure 7B A program state corresponding to user data (eg, unencoded original data) to be programmed into the n+1th word line WLn+1 and a program state corresponding to encoded data after encoding are shown according to an embodiment.

[0094] Referring to the state of the data to be programmed into the n+1th word line WLn+1 corresponding to the unencoded original data, the data to be programmed into the target cell MC1 connected to the first bit line BL1 can have state P7, and the data to be programmed into the target cell MC5 connected to the fifth bit line BL5 can have state E.

[0095] Since the corresponding adjacent cell has the first state P_L, the data to be programmed into the target cell MC1 connected to the first bit line BL1 may be data corresponding to the first shaping target pattern. Therefore, the data to be programmed into the target cell MC1 may be encoded to satisfy the first data condition that does not have the first shaping target pattern (e.g., state P7).

[0096] Because the corresponding adjacent cell has the second state P_H, the data to be programmed into the target cell MC5 connected to the fifth bit line BL5 may be data corresponding to the second shaping target pattern. Therefore, the data to be programmed into the target cell MC5 may be encoded to satisfy the second data condition that does not have the second shaping target pattern (e.g., state E).

[0097] The data to be programmed into the target cells MC3 and MC6 connected to the third bit line BL3 and the sixth bit line BL6 may have states E and P7, respectively. However, the corresponding adjacent cells are in the first state P_L and the second state P_H, so that the programming mode of the data to be programmed into the target cells MC3 and MC6 connected to the third bit line BL3 and the sixth bit line BL6 may not be the shaping target mode.

[0098] As a result, referring to the programming states of the target cells corresponding to the encoded data after the encoding operation, the target cell MC1 connected to the first bit line BL1 may have a programming mode (e.g., P4) other than the first shaping target mode, and the target cell MC5 connected to the fifth bit line BL5 may have a programming mode (e.g., P2) other than the second shaping target mode, as shown in FIG. Figure 7B shown.

[0099] In example embodiments, target cells corresponding to neighboring cells having the first state P_L as a program state may not have the first shaping target pattern, and target cells corresponding to neighboring cells having the second state P_H as a program state may not have the second shaping target pattern.

[0100] Alternatively or additionally, the number of target cells having the first shaping target pattern among target cells corresponding to adjacent cells having the first state P_L as a programming state may be reduced, and the number of target cells having the second shaping target pattern among target cells corresponding to adjacent cells having the second state P_H as a programming state may be reduced. Thus, changes in threshold voltage distribution caused by word line disturbance and lateral charge loss may be reduced, thereby potentially leading to an improvement in data reliability.

[0101] For ease of description, Fig. 7A and Figure 7B , the neighboring cells are described as being classified into two states P_L and P_H, and the target cell is described as corresponding to one of the two shaping target modes. However, this is merely exemplary, and example embodiments are not limited thereto. As another example, the neighboring cells may be classified into three or more states, as described in reference to Fig. 8A As described.

[0102] Fig. 8A and Figure 8B is a diagram showing a method according to an embodiment of the present invention. Figure 6 FIG. 1 is a diagram showing an example of operations S110 to S130 . Fig. 8A and Figure 8B In many ways it can be Fig. 7A and Figure 7B The present invention is similar to and may include additional features not mentioned above. Therefore, for the sake of brevity, repeated descriptions may be omitted.

[0103] According to example embodiments, the memory controller 1100 may classify neighboring cells into one of three (3) states based on a programming state. For example, the memory controller 1100 may identify neighboring cells corresponding to a first state P_L and neighboring cells corresponding to a second state P_H based on the programming state of each neighboring cell. Alternatively or additionally, the memory controller 1100 may classify neighboring cells that do not correspond to the first state P_L and the second state P_H as cells corresponding to a third state P_M.

[0104] For example, Fig. 8A As shown, the first to third neighboring cells MC1 to MC3 having states E, P1, and P2, respectively, may be classified as the first state P_L. The seventh neighboring cells MC7 and the eighth neighboring cells MC8 having states P6 and P7, respectively, may be classified as the second state P_H. The fourth to sixth neighboring cells MC4 to MC6 having the remaining programming states may be classified as the third state P_M. Based on this, the memory controller 1100 may generate the following Fig. 8A Programming mode information is shown.

[0105] Continue to refer Fig. 8A , the target cells MC1 to MC3 corresponding to the neighboring cells MC1 to MC3 having the first state P_L as the programming state may have a first shaping target pattern (e.g., state P7). The target cells MC7 and MC8 corresponding to the neighboring cells MC7 and MC8 having the second state P_H as the programming state may have a second shaping target pattern (e.g., state E). The target cells MC4 to MC6 corresponding to the neighboring cells MC4 to MC6 having the third state P_M as the programming state may not have a shaping target pattern and / or may have a default value. Based on this, the storage controller 1100 may generate the following: Fig. 8A The shaping target mode information is shown.

[0106] In an embodiment, the data to be programmed into the target cell may be encoded so that the data to be programmed into the target cell corresponding to the neighboring cell in the first state P_L satisfies the first data condition, and the data to be programmed into the target cell corresponding to the neighboring cell in the second state P_H satisfies the second data condition. Alternatively or additionally, the data to be programmed into the target cell corresponding to the neighboring cell in the third state P_M may not be encoded.

[0107] refer to Figure 8B , the data to be programmed into the target cell MC1 connected to the first bit line BL1 may be encoded to satisfy the first data condition. For example, the data to be programmed into the target cell MC1 connected to the first bit line BL1 may be encoded from state P7 to state P4. The data to be programmed into the target cell MC5 connected to the fifth bit line BL5 may not be encoded. For example, in Fig. 7A and Figure 7B In the example, the data to be programmed into the target cell connected to the fifth bit line BL5 is encoded from state E to state P2, while in Fig. 8A and Figure 8B In the embodiment, data to be programmed into the target cell MC5 connected to the fifth bit line BL5 may be maintained in the state E.

[0108] According to the present embodiment, the storage controller 1100 may not set a shaping target mode and a data condition for a target cell corresponding to an adjacent cell having neither the first state P_L nor the second state P_H. That is, the change in the threshold voltage distribution of the adjacent cell having neither the first state nor the second state may be less than (e.g., less than) the change in the threshold voltage distribution of the adjacent cell having the first state and the second state, and therefore, it may not be necessary to set a shaping target mode and / or a data condition for such a target cell. Therefore, the storage controller 1100 may improve the efficiency of encoding by preventing at least a portion of the user data from being encoded.

[0109] Fig. 9 is a block diagram illustrating a configuration of a memory controller according to example embodiments. Fig. 9 The storage controller 1100_1 may include Figure 1 The storage controller 1100 and / or may be used in many ways with Figure 1 1 is similar to the storage controller 1100 of 1100_1 and may include additional features not mentioned above. Therefore, the same or similar components may be represented by the same and / or similar reference numerals, and repeated description of the storage controller 1100_1 may be omitted for the sake of brevity.

[0110] refer to Fig. 9, the storage controller 1100_1 may include a host interface (I / F) 1110, a non-volatile memory interface 1120, a central processing unit (CPU) 1130, an error correction code (ECC) circuit 1140, a state shaping circuit 1150A, a random access memory (RAM) 1160 and a read-only memory (ROM) 1170.

[0111] The host I / F 1110 may perform an interface between the storage device 1000 including the storage controller 1100_1 and the host 1500. The host I / F 1110 may communicate with the host 1500 using at least one protocol, such as but not limited to Universal Flash Storage (UFS), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Embedded MultiMediaCard (eMMC), Fibre Channel (FC), Advanced Technology Attachment (ATA), Integrated Drive Electronics (IDE), Universal Serial Bus (USB), Institute of Electrical and Electronics Engineers (IEEE) 1394 (FireWire), and the like.

[0112] The nonvolatile memory interface 1120 may perform an interface (eg, communicate through an interface) between the memory controller 1100_1 and the nonvolatile memory device 1200 .

[0113] The CPU 1130 may control the overall operation of the storage controller 1100_1. For example, in response to a request from the host 1500, the CPU 1130 may control the state shaping circuit 1150A, the nonvolatile memory interface 1120, etc. to program data into the nonvolatile memory device 1200 and / or read data stored in the nonvolatile memory device 1200.

[0114] The ECC circuit 1140 may perform error bit correction. For example, the ECC circuit 1140 may perform error detection and correction functions on read data read from the nonvolatile memory device 1200. In an embodiment, the ECC circuit 1140 may include an ECC encoder 1141 and an ECC decoder 1143.

[0115] The ECC encoder 1141 may generate parity bits for data to be programmed into the nonvolatile memory device 1200. In example embodiments, the ECC encoder 1141 may generate parity bits for the encoded data encoded by the state shaping circuit 1150A. The generated parity bits may be programmed into the nonvolatile memory device 1200 together with the encoded data.

[0116] When reading data from the nonvolatile memory device 1200, the ECC decoder 1143 may correct errors in the encoded data using parity bits read together with the encoded data. The error-corrected encoded data EN_DATA may be provided to the state shaping circuit 1150A.

[0117] The ECC encoder 1141 and the ECC decoder 1143 may perform error correction using coded modulation, such as, but not limited to, low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. However, the present disclosure is not limited thereto.

[0118] Continue to refer Fig. 9 , the state shaping circuit 1150A may include a shaping encoder 1151A and a shaping decoder 1153A.

[0119] The shaping encoder 1151A can encode the data to be programmed into the target word line based on the programming state of the adjacent word line. For example, the shaping encoder 1151A can encode the data to be programmed into the target word line based on whether the programming state of the adjacent word line is the first state P_L or the second state P_H. In this example, the data to be programmed into the target cell corresponding to the adjacent cell in the first state P_L can be encoded to meet the first data condition. The data to be programmed into the target cell corresponding to the adjacent cell in the second state P_H can be encoded to meet the second data condition.

[0120] In example embodiments, the first state P_L may be a programming state corresponding to a relatively low threshold voltage among programming states of each memory cell, and the second state P_H may be a programming state corresponding to a relatively high threshold voltage among programming states of each memory cell. In example embodiments, the first data condition may be a data condition that prevents data to be programmed into a target cell corresponding to an adjacent cell in the first state P_L from having a first shaping target pattern. The second data condition may be a data condition that prevents data to be programmed into a target cell corresponding to an adjacent cell in the second state P_H from having a second shaping target pattern. In example embodiments, the first shaping target pattern may be a programming state corresponding to a highest threshold voltage among programming states of the memory cell, and the second shaping target pattern may be a programming state corresponding to an erased state among programming states of the memory cell.

[0121] When encoding data to be programmed to a target word line, the shaping encoder 1151A may use a plurality of codewords. In an example embodiment, the shaping encoder 1151A may encode data using a polarity-encoded codeword.

[0122] In example embodiments, when the data to be programmed into the target word line includes data of a plurality of logical pages, the shaping encoder 1151A may perform temporary encoding on the data of the plurality of logical pages. The shaping encoder 1151A may perform encoding by sequentially applying a plurality of codewords to the temporary encoded data of each logical page.

[0123] The shaping encoder 1151A may select a codeword that satisfies the first data condition and the second data condition to the greatest extent (eg, maximally) for each data of each logical page. The data of each logical page to which the selected codeword is applied may be output as an encoding result value.

[0124] The encoded data output from the shaping encoder 1151A may be programmed together with encoding-related information into the nonvolatile memory device 1200. In example embodiments, the encoding-related information may be information related to a codeword selected for each logical page.

[0125] The shaping decoder 1153 may read the encoded data from the nonvolatile memory device 1200 and may decode the original data from the encoded data using the encoding related information.

[0126] The RAM 1160 may be a cache memory (eg, static RAM (SRAM)), a buffer memory (eg, dynamic RAM (DRAM)), and / or a drive memory. The RAM 1160 may store information required for the state shaping circuit 1150A to perform encoding.

[0127] The ROM 1170 may store driving firmware codes of the memory device 1000 and codes required for the operation of the memory controller 1100 .

[0128] In an embodiment, the storage controller 1100_1 may encode the data to be programmed into the target word line to have a data condition that varies according to the programming state of the adjacent word line. In addition, when the data to be programmed is data for multiple logical pages, the storage controller 1100_1 may temporarily encode the data of the multiple logical pages, and the codeword may be sequentially applied to the temporarily encoded data of the multiple logical pages. In this embodiment, a codeword that satisfies the first and second data conditions to the greatest extent (e.g., maximally) may be selected for each logical page. The storage controller 1100_1 may output the data of each logical page to which the selected codeword is applied as the encoding result value. Therefore, interference between word lines during the programming operation may be reduced, thereby improving the reliability of the data.

[0129] Fig.10 is a diagram showing a method according to an embodiment of the present invention. Fig. 9 The block diagram of the shaping encoder 1151A is shown in FIG. Fig.10 , the shaping encoder 1151A may include a temporary encoder 100 , a pattern checker 200 , a shaping position buffer 300 , a codeword selector 400 and an operator 500 .

[0130] For ease of description, Fig.10 , an example is provided in which the first to n-th word lines WL1 to WLn are sequentially programmed and the shaping encoder 1151A encodes user data to be programmed to the n+1-th word line WLn+1 (eg, a target word line).

[0131] The temporary encoder 100 may receive user data U_data_WLn+1 to be programmed into the n+1th word line WLn+1 (eg, a target word line) through a host interface. The temporary encoder 100 may generate temporary encoding data T_en_data through a temporary encoding operation.

[0132] In example embodiments, the temporary encoder 100 may apply a polar code generation matrix to the user data U_data_WLn+1 to generate temporary encoded data T_en_data.

[0133] The pattern checker 200 may receive data En_data_WLn programmed in an nth word line WLn (eg, an adjacent word line). The data programmed into the nth word line WLn may be data programmed after being encoded by the shaping encoder 115A in consideration of a programming state of the n-1th word line WLn-1.

[0134] The mode checker 200 may check the programming state of each adjacent cell connected to the nth word line WLn, and may classify each adjacent cell into one of a plurality of states. For example, the mode checker 200 may classify the adjacent cells into a first state P_L and a second state P_H based on the programming state. The first state P_L may include a programming state corresponding to a low threshold voltage among the programming states of the memory cell, and the second state P_H may include a programming state corresponding to a high threshold voltage among the programming states of the memory cell.

[0135] The mode checker 200 may generate program mode information P_inf based on classification information of the neighboring cells. The program mode information P_inf may include information on whether a program state of each neighboring cell connected to the nth word line WLn is a first state P_L or a second state P_H.

[0136] The shaping position buffer 300 may generate shaping position information S_1_inf based on the programming mode information P_inf. The shaping position information S_1_inf may include position information of the shaping target unit. Alternatively or additionally, the shaping position buffer 300 may update the shaping position information S_1_inf based on the encoding result value EN_data_WLn+1.

[0137] The codeword selector 400 may receive the temporary encoded data T_en_data from the temporary encoder 100. The codeword selector 400 may receive the shaping position information S_I_inf from the shaping position buffer 300.

[0138] The codeword selector 400 may select a codeword to be applied to the temporary encoding data T_en_data from a plurality of codewords based on the shaping position information S_I_inf, and may apply the selected codeword. For example, the codeword selector 400 may select a codeword so that the data to be programmed into the target cell corresponding to the adjacent cell in the first state P_L satisfies the first data condition, and the data to be programmed into the target cell corresponding to the adjacent cell in the second state P_H satisfies the second data condition. In an example embodiment, the codeword selector 400 may select and output a codeword S_codeword that satisfies the first data condition and the second data condition to the greatest extent.

[0139] The operator 500 may perform a first operation on the temporary encoding data T_en_data and the selected codeword S_codeword to generate an encoding result En_data_WLn+1. In an example embodiment, the first operation may be an XOR operation. However, the present disclosure is not limited thereto.

[0140] In example embodiments, when the user data U_data_WLn+1 to be programmed into the n+1th word line WLn+1 (e.g., the target word line) includes a plurality of logical page data, the encoding result may be sequentially generated for each logical page. For example, in the case of TLC, first to third encoded data corresponding to each of the first to third logical pages may be generated as the encoding result value.

[0141] In this embodiment, when the first encoded data is generated as a result value of the data of the first logical page, the first encoded data may be fed back to the shaping position buffer 300 .

[0142] The shaping position buffer 300 may update the shaping position information S_1_inf based on the first encoded data. The shaping position buffer 300 may update the shaping position information S_1_inf by excluding the position of the target unit satisfying the first data condition or the second data condition from the subsequent shaping target. The updated shaping position information S_1_inf may be provided to the codeword selector 400 and may be used in the encoding operation of the second logical page.

[0143] The codeword selector 400 may select a codeword that satisfies the first data condition and the second data condition to the greatest extent for the target cell indicated in the updated shaping position information S_1_inf. For example, the codeword selector 400 may exclude the target cell that has satisfied the first data condition and the second data condition by encoding the data of the first logical page from the shaping target. Therefore, the codeword selector 400 may select a codeword that satisfies the data condition of only a portion of the memory cells. As a result, when compared with a related memory device, programming state shaping may be performed relatively more efficiently and accurately.

[0144] In an embodiment, the shaping encoder 1151A may set a first data condition and a second data condition for each of a plurality of logical page data in consideration of a programming state of an adjacent word line, and may sequentially perform encoding so that each logical page satisfies the first and second data conditions. Alternatively or additionally, the shaping encoder 1151A may update position information of cells that may need to satisfy the first data condition and the second data condition when encoding the next logical page data in consideration of a result obtained by encoding previously performed on the logical page data. Therefore, when compared to a related storage device, an encoding operation may be performed relatively more efficiently.

[0145] In the following, reference FIG. 11A to FIG. 11C , FIG. 12A to FIG. 12C , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14C An example of the operation of the shaping encoder 1151A is described.

[0146] Fig.11A is a diagram illustrating a portion of data programmed in an n-th word line WLn (an adjacent word line) in a TLC cell and a program state corresponding thereto according to an embodiment.

[0147] In the case of a TLC cell, the data programmed into the nth word line WLn may include first to third logical page data. The first to third logical page data may be and / or may include data of a least significant bit (LSB) page, data of a center significant bit (CSB) page, and data of a most significant bit (MSB) page, respectively.

[0148] For example, Fig.11AAs shown, the first to eighth memory cells MC1 to MC8 connected to the nth word line WLn (e.g., adjacent word lines) may be programmed to states E, P7, P4, P1, P2, P6, P5, and P3, respectively. In this example, the data of the first to third logical pages LSB, CSB, and MSB corresponding to the nth word line WLn may be "[11000110]", "[10110010]", and "[11011000]", respectively.

[0149] Fig. 11B is a diagram showing the Fig.11A The programming mode information of each neighboring cell is shown in FIG. Fig. 11B , the first, fourth, fifth and eighth memory cells MC1, MC4, MC5 and MC8 may be in the first state, and the second, third, sixth and seventh memory cells MC2, MC3, MC6 and MC7 may be in the second state.

[0150] Fig. 11C is a diagram showing a portion of user data to be programmed to an n+1th word line WLn+1 (programming target word line) and a program state corresponding thereto according to an embodiment.

[0151] like Fig. 11C As shown, user data to be programmed into the n+1th word line WLn+1 may include data of a first logical page corresponding to LSBs, data of a second logical page corresponding to CSBs, and data of a third logical page corresponding to MSBs.

[0152] FIG. 12A to FIG. 12C is a diagram showing a method for performing a Fig. 11C FIG. 1 is a diagram of an operation of encoding data of a first logical page LSB to be programmed into the data in the n+1th word line WLn+1.

[0153] refer to Fig. 12A , the temporary encoder 100 may receive user data to be programmed into the n+1th word line WLn+1. For example, the temporary encoder 100 may receive Fig. 11C The user data shown in .

[0154] The temporary encoder 100 may apply a generation matrix of a polar code to the data of the first to third logical pages to generate temporary encoding data T_en_data. In an example embodiment, the temporary encoder 100 may apply an m×n generation matrix to the data of the first to third logical pages to generate temporary encoding data T_en_data, where m is a positive integer greater than zero (0), and n is equal to 2. a .like Fig. 12BThe 6×8 (e.g., m=6, a=3, n=8) generator matrix shown for use in the temporary encoder 100 is only a non-limiting example. That is, the present disclosure is not limited in this regard, and other examples of generator matrices with different dimensions are possible without departing from the scope of the present disclosure.

[0155] The mode checker 200 may receive data programmed into the nth word line WLn (eg, an adjacent word line). For example, the mode checker 200 may receive data such as Fig.11A The mode checker 200 may generate programming mode information P_inf for the received data.

[0156] The mode checker 200 may generate the programming mode information P_inf as, for example, P_L[10011001] and P_H[01100110]. P_L[10011001] may include position information of adjacent cells in a first state, and P_H[01100110] may include position information of adjacent cells in a second state.

[0157] The shaping position buffer 300 may generate shaping position information S_I_inf based on the programming mode information P_inf. When the encoding target is data of the first logical page (e.g., LSB), the shaping position information S_I_inf may be the same as the programming mode information P_inf. For example, the shaping position buffer 300 may determine that shaping may need to be performed on all target cells indicated in the programming mode information P_inf.

[0158] According to the shaping position information S_I_inf, it can be understood that the target units that need to meet the first data condition are the first, fourth, fifth and eighth storage cells MC1, MC4, MC5 and MC8, and the target units that need to meet the second data condition are the second, third, sixth and seventh storage cells MC2, MC3, MC6 and MC7.

[0159] The codeword selector 400 may receive temporary encoded data T_en_data corresponding to the first logical page LSB from the temporary encoder 100. For example, the temporary encoded data T_en_data may be LSB [11010100].

[0160] In this example, the codeword selector 400 may apply a plurality of codewords to the temporary encoded data T_en_data, LSB [11010100]. The codeword selector 400 may select and output a codeword S_codeword1 that satisfies the first data condition and the second data condition to the greatest extent from among the plurality of codewords.

[0161] refer to Fig. 12C, the first data condition may be a data condition that allows data to be programmed into a target cell corresponding to an adjacent cell in the first state P_L to have a programming mode other than the first shaping target mode. Since the LSB data is "1" when the first shaping target mode is P7, the data of the first shaping target mode may be "1". For example, the first data condition corresponding to the first logical page LSB of the temporary encoding data T_en_data may be non-"1". In this example, the codeword selector 400 may determine that the LSB data corresponding to the first storage cell MC1 and the fourth storage cell MC4 do not satisfy the first data condition.

[0162] The second data condition may be a data condition that prevents the data to be programmed into the target cell corresponding to the adjacent cell in the second state P_H from having the second shaping target pattern. Since the corresponding LSB data is "1" when the second shaping target pattern is E, the data of the second shaping target pattern corresponding to the data of the first logical page LSB of the temporary encoding data T_en_data may be "1". For example, the second data condition corresponding to the first logical page LSB of the temporary encoding data T_en_data may be non-"1". In this example, the codeword selector 400 may determine that the LSB data corresponding to the second storage cell MC2 and the sixth storage cell MC6 do not satisfy the second data condition.

[0163] As a result, the codeword selector 400 may determine that, in the first logical page LSB, data to be programmed into the first, second, fourth, and sixth memory cells MC1 , MC2 , MC4 , and MC6 do not satisfy the first or second data condition.

[0164] The codeword selector 400 may apply a plurality of codewords to the data of the first logical page LSB of the temporary encoded data T_en_data to generate data to which the codeword has been applied. In an example embodiment, the codeword selector 400 may perform an XOR operation on the data of the first logical page LSB of the temporary encoded data T_en_data and each of the plurality of codewords to generate data to which the codeword has been applied. However, the present disclosure is not limited thereto in this regard, and the codeword selector 400 may perform another type of operation to generate data to which the codeword has been applied.

[0165] The codeword selector 400 may select the codeword S_codeword1 so that the data to which the codeword has been applied satisfies the first data condition or the second data condition to the greatest extent. Fig. 12A In the example embodiment of FIG. 1 , the selected codeword S_codeword1 corresponding to the first logical page LSB may be “[01010101]”.

[0166] The operator 500 may perform an operation on the temporary encoded data LSB [11010100] corresponding to the first logical page LSB and the selected codeword S_codeword1 to generate the first encoded data En_data_WLn+1 corresponding to the first logical page LSB. For example, the encoded data En_data_WLn+1 corresponding to the first logical page LSB may be LSB [10000001]. In this example, it can be understood that in the encoded data En_data_WLn+1 corresponding to the first logical page LSB, compared with LSB [11010100] of the temporary encoded data T_en_data corresponding to the first logical page LSB, the data of the fourth target cell MC4 satisfies the first data condition, and the data of the second target cell MC2 and the sixth target cell MC6 satisfy the second data condition.

[0167] The encoded data En_data_WLn+1 corresponding to the first logical page LSB may be fed back to the shaping position buffer 300. Since the fourth target cell MC4 satisfies the first data condition and the data of the second target cell MC2 and the sixth target cell MC6 satisfy the second data condition through encoding, the information of the shaping position information S_I_inf corresponding to the second target cell MC2, the fourth target cell MC4 and the sixth target cell MC6 may be updated. In addition, in the encoded data En_data_WLn+1 corresponding to the first logical page, the fifth target cell MC5 satisfies the first data condition, and the third target cell MC3 and the seventh target cell MC7 satisfy the second data condition. Therefore, the information of the shaping position information S_I_inf corresponding to the third, fifth and seventh target cells MC3, MC5 and MC7 may be updated together.

[0168] As a result, the shaping position buffer 300 may update the shaping position information S_I_inf to exclude the second, third, fourth, fifth, sixth, and seventh target cells MC2, MC3, MC4, MC5, MC6, and MC7 from the shaping targets.

[0169] Fig.13A and Fig. 13B is a diagram showing a pair of Fig. 11C 0 is a diagram of an operation of encoding data of a second logical page CSB to be programmed into the data in the n+1th word line WLn+1.

[0170] As reference Fig. 12A As described, the shaping position buffer 300 may update the shaping position information S_I_inf to exclude the second, third, fourth, fifth, sixth, and seventh target cells MC2, MC3, MC4, MC5, MC6, and MC7 from the shaping target. Fig.13AAs shown, it can be understood from the shaping position information S_I_inf that the target cells that need to meet the first data condition are the first and eighth storage cells MC1 and MC8, and the cells that need to meet the second data condition do not exist.

[0171] The codeword selector 400 may receive temporary encoded data T_en_data corresponding to the second logical page CSB from the temporary encoder 100. The temporary encoded data T_en_data may be CSB[00010000].

[0172] In this example, the codeword selector 400 may apply a plurality of codewords to the temporary coded data T_en_data, CSB [00010000]. The codeword selector 400 may select and output a codeword S_codeword2 that satisfies the first data condition and the second data condition to the greatest extent from among the plurality of codewords.

[0173] refer to Fig. 13B , the first data condition may be a data condition that allows the data to be programmed into the target cell corresponding to the adjacent cell in the first state P_L to have a programming mode other than the first shaping target mode. When the CSB data corresponding to the first shaping target mode is "0", the data of the first shaping target mode corresponding to the second logical page CSB may be "0". For example, the first data condition corresponding to the second logical page CSB of the temporary encoding data T_en_data may be non-"0". Fig.13A In the example of , the codeword selector 400 may determine that the first data condition is not satisfied in the first storage cell MC1 and the eighth storage cell MC8.

[0174] The second data condition may be a data condition that prevents data to be programmed into a target cell corresponding to an adjacent cell in the second state P_H from having a second shaping target pattern. When the CSB data corresponding to the second shaping target pattern is "1", the second shaping target pattern corresponding to the second logical page CSB may be "1". For example, the second data condition corresponding to the second logical page CSB of the temporary encoding data T_en_data may be non-"1".

[0175] The codeword selector 400 may apply a plurality of codewords to data of the second logical page CSB, and may select the codeword S_codeword2 so that the data to which the codeword is applied satisfies the first data condition or the second data condition to the greatest extent in the cell position indicated by the shaping position information S_I_inf.

[0176] exist Fig.13AIn the example embodiment of , a codeword S_codeword2 corresponding to data that satisfies the first data condition to the greatest extent in the first storage cell MC1 and the eighth storage cell MC8 may be selected from among the codewords. Fig.13A In the example embodiment of FIG. 1 , the codeword S_codeword2 corresponding to the second logical page CSB selection may be “[11111111]”.

[0177] refer to Fig.13A , the operator 500 may perform an operation on the temporary coded data CSB[00010000] corresponding to the second logical page CSB and the codeword S_codeword2 to generate the coded data En_data_WLn+1 corresponding to the second logical page CSB. For example, the coded data En_data_WLn+1 corresponding to the second logical page CSB may be CSB[11101111].

[0178] The encoded data En_data_WLn+1 corresponding to the second logical page CSB may be fed back to the shaping position buffer 300. In the encoded data En_data_WLn+1 corresponding to the second logical page CSB, the data of the first target cell MC1 and the data of the eighth target cell MC8 satisfy the first data condition. Therefore, the information of the shaping position information S_I_inf corresponding to the first and eighth target cells MC1 and MC8 may be updated.

[0179] As a result, the shaping position buffer 300 may update the shaping position information S_I_inf to additionally exclude the first target cell MC1 and the eighth target cell MC8 from the shaping targets.

[0180] FIG. 14A to FIG. 14C is a diagram showing a pair of Fig. 11C 0 is a diagram of an operation of encoding data of a third logical page MSB among data to be programmed into the n+1th word line WLn+1.

[0181] like Fig.13A As described in , the shaping position buffer 300 may update the shaping position information S_I_inf to exclude the first target cell MC1 and the eighth target cell MC8 from the shaping targets.

[0182] Therefore, if Fig.14A As shown, it can be understood from the shaping position information S_I_inf that there is no unit that needs to meet the first or second data condition.

[0183] The codeword selector 400 may receive temporary encoded data T_en_data corresponding to the MSB of the third logical page from the temporary encoder 100. The temporary encoded data T_en_data may be MSB [10100100].

[0184] The codeword selector 400 may apply a plurality of codewords to the temporary encoded data T_en_data, MSB [10100100]. The codeword selector 400 may select a codeword that satisfies the first data condition or the second data condition to the greatest extent in the position of the target unit indicated by the shaping position information S_I_inf.

[0185] refer to Fig. 14B , each of the first data condition and the second data condition corresponding to the MSB of the third logical page may be non-"1". Fig.14A In the embodiment, according to the updated shaping position information (S_I_inf), there is no unit that needs to meet the first or second data condition. Therefore, any codeword can be selected and output. In the example embodiment, the codeword S_codeword3 can be selected and output, and the codeword S_codeword3 can be "[00000000]".

[0186] Continue to refer Fig.14A , the operator 500 may perform an operation on the temporary encoded data MSB[10100100] corresponding to the third logical page MSB and the codeword S_codeword3 to generate the encoded data En_data_WLn+1 corresponding to the third logical page MSB. For example, the encoded data En_data_WLn+1 corresponding to the third logical page MSB may be MSB[10100100].

[0187] and showing a programming state corresponding to user data before being encoded Fig. 11C compared to, Fig. 14C The programming state corresponding to the encoding data En_data_WLn+1 is shown. Fig. 11C It can be understood that the target cell MC5 adjacent to the cells of the adjacent word line in the first state has a first shaping target mode (e.g., state P7), and the target cells MC2 and MC3 adjacent to the adjacent word line cells in the second state have a second shaping target mode (e.g., state E).

[0188] Alternatively, from Fig. 14C It can be understood that the first, fourth, fifth and eighth target cells MC1, MC4, MC5 and MC8 adjacent to the adjacent word line cells in the first state do not have the first shaping target mode (e.g., state P7), and the second, third, sixth and seventh storage cells MC2, MC3, MC6 and MC7 adjacent to the adjacent word line cells in the second state do not have the second shaping target mode (e.g., state E).

[0189] In an example embodiment, the shaping encoder 1151A may set a first data condition and a second data condition for each of a plurality of logical page data in consideration of a programming state of an adjacent word line, and may sequentially perform encoding so that each logical page satisfies the first and second data conditions. Alternatively or additionally, the shaping encoder 1151A may update the position information of a cell that needs to satisfy the first data condition and the second data condition when encoding the next logical page data in consideration of a result obtained by previously performing encoding on the next logical page data. Therefore, when compared with a related memory device, a defective programming mode may be removed relatively efficiently and accurately.

[0190] Fig.15 is a diagram illustrating an example of the operation of the state shaping circuit 1150A according to an example embodiment.

[0191] In operation S210, the state shaping circuit 1150A may check a program state of each adjacent cell connected to an nth word line WLn that has been programmed. The nth word line may be a word line adjacent to an (n+1)th word line to be programmed.

[0192] In example embodiments, the state shaping circuit 1150A may classify the programming state of each adjacent cell into a first state and a second state. The first state may be a programming state corresponding to a low threshold voltage among programming states of each memory cell, and the second state may be a programming state corresponding to a high threshold voltage among programming states of each memory cell.

[0193] In an exemplary embodiment, when the number of bits stored in the memory cell is "a", the erase state and states P1 to P2 a -1 -1 can each be the first state, and state P2 a-1 To P2 a -1 may each be the second state, where a is a positive integer greater than zero (0). However, the present disclosure is not limited thereto.

[0194] In an example embodiment, the state shaping circuit 1150A may check the programming state of each adjacent cell to identify memory cells in the first state and the second state, and classify adjacent cells that are neither in the first state nor in the second state as a third state. In this example, when the adjacent cell has an erased state and "b" program states, the erased state and the lower (b-1) / 3 program states may be classified as the first state, and the upper (b-1) / 3 program states may be classified as the second state, where b is a positive integer greater than zero (0). In an embodiment, the remaining program states may be classified as the third state.

[0195] The state shaping circuit 1150A may generate programming mode information. The programming mode information may include position information of neighboring cells in the first state and position information of neighboring cells in the second state among the neighboring cells.

[0196] In operation S220 , a temporary encoding operation may be performed on user data to be programmed into the n+1th word line WLn+1 to generate temporary encoded data.

[0197] The state shaping circuit 1150A may apply a polar code generation matrix to generate temporary encoded data.

[0198] exist Fig.15 , operation S220 is shown as being performed after operation S210. However, example embodiments are not limited thereto. For example, operation S210 may be performed after operation S220.

[0199] In operation S230, the state shaping circuit 1150A may generate shaping position information about the k-1th logical page data based on the programming mode information, where k is a positive integer greater than one (1). The shaping position information S_l_inf about the k-1th logical page data may include position information of a target cell connected to the n+1th word line WLn+1 to be a shaping target during an encoding operation on the k-1th logical page data.

[0200] In example embodiments, the shaping position information S_1_inf about the k-1th logical page data may indicate that all target cells of the n+1th word line WLn+1 are shaping targets. That is, the target cells corresponding to the neighboring cells in the first state may need to have the first data condition, and the target cells corresponding to the neighboring cells in the second state may need to have the second data condition.

[0201] In operation S240, the state shaping circuit 1150A may select a codeword for data of the k-1th logical page. For example, when k is 2, when selecting a codeword for the first logical page data, the state shaping circuit 1150A may apply a plurality of codewords to the data of the first logical page among the temporary encoded data.

[0202] In example embodiments, the state shaping circuit 1150A may select a codeword that satisfies the first data condition and the second data condition to the greatest extent with respect to a target cell indicated by the shaping position information of the data of the first logical page.

[0203] In an example embodiment, the first data condition is a data condition that allows a target cell adjacent to a cell in a first programming state to have a programming mode other than the first shaping target mode, and the second data condition may be a data condition that allows a target cell adjacent to an adjacent cell in a second state to have a programming mode other than the second shaping target mode.

[0204] In example embodiments, the first shaping target mode may be a programming state corresponding to a highest threshold voltage among programming states, and the second shaping target mode may be a programming state corresponding to an erase state among programming states. However, the present disclosure is not limited thereto.

[0205] In operation S250 , the state shaping circuit 1150A may generate k-1th encoded data regarding the k-1th logical page data.

[0206] In example embodiments, the state shaping circuit 1150A may apply the selected codeword to temporary coded data corresponding to the k-1th logical page data to generate k-1th coded data.

[0207] In operation S260, the state shaping circuit 1150A may update shaping position information based on the k-1th encoded data. The updated shaping position information may be used as shaping position information about the kth logical page.

[0208] In an example embodiment, the state shaping circuit 1150A may update the shaping position information based on whether the k-1th coded data satisfies the first or second data condition of the k-1th logical page data. For example, the shaping position information may be updated by excluding the position information of the target cells that satisfy the first or second data condition for the k-1th logical page data from the target cells indicated in the shaping position information.

[0209] When the number of logical page data corresponding to the n+1th word line is 'a', operations S240 , S250 , and S260 may be repeated until 'k' becomes equal to 'a'.

[0210] When 'a' pieces of coded data are generated, the 'a' pieces of coded data may be transmitted to the nonvolatile memory device 1200 together with a codeword applied to each coded data.

[0211] According to example embodiments, a first data condition and a second data condition are set for each of a plurality of logical page data in consideration of a programming state of an adjacent word line, and encoding may be sequentially performed so that each logical page satisfies the first data condition and the second data condition. Alternatively or additionally, location information of cells that need to satisfy the first data condition and the second data condition when encoding the next logical page data may be updated in consideration of a result obtained by encoding previously performed on the logical page data, and thus, when compared to a related memory device, a defective programming mode may be removed more efficiently and accurately.

[0212] As described above, the memory device according to the example embodiment can encode the data to be programmed into the target word line to have a data condition that varies according to the programming state of the adjacent word line. Therefore, when compared with the related memory device, the interference between the word lines during the programming operation can be reduced, thereby improving the reliability of the data.

[0213] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A storage device, comprising: A nonvolatile memory device comprising a plurality of first memory cells coupled to a first word line and a plurality of second memory cells coupled to a second word line, the first word line and the second word line being adjacent to each other; as well as a memory controller configured to control the nonvolatile memory device, Wherein, the storage controller is further configured as: encoding data to be programmed into the plurality of second memory cells based on a programming state of each of the plurality of first memory cells, the programming state comprising a first state and a second state; as well as The data to be programmed into the second word line is encoded so that a first portion of the data to be written into a first portion of the plurality of second storage cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second storage cells satisfies a second condition, the first portion of the plurality of second storage cells being adjacent to a first portion of the plurality of first storage cells being in the first state, and the second portion of the plurality of second storage cells being adjacent to a second portion of the plurality of first storage cells being in the second state.

2. The storage device according to claim 1, wherein: the first condition being configured to allow the first portion of the data to have a first programming mode other than a first shaping target mode, wherein the first portion of the data is programmed into the first portion of the plurality of second memory cells adjacent to the first portion of the plurality of first memory cells in the first state, and wherein the second condition is configured to allow the second portion of the data to have a second programming mode other than a second shaping target mode, wherein the second portion of the data is programmed into the second portion of the plurality of second storage cells adjacent to the second portion of the plurality of first storage cells in the second state.

3. The storage device according to claim 2, wherein: The storage controller is further configured to: selecting a codeword from a plurality of codewords, the selected codeword corresponding to data that maximally satisfies at least one of the first condition and the second condition among data generated by applying the plurality of codewords to the data to be programmed into the plurality of second memory cells; encoding the data to be programmed into the plurality of second memory cells based on the selected codeword; as well as Output the encoded data as the encoding result value.

4. The storage device according to claim 2, wherein: The data to be programmed into the plurality of second memory cells includes a plurality of logical page data, and Wherein, the storage controller is further configured as: performing temporary encoding on the plurality of pieces of logical page data; selecting a codeword that maximally satisfies at least one of the first condition and the second condition set for each of the plurality of pieces of logical page data that are temporarily encoded; and The corresponding codeword is applied to each of the plurality of temporarily encoded pieces of logical page data to generate an encoding result value of each of the plurality of pieces of logical page data.

5. The storage device according to claim 4, wherein: The storage controller is configured to: generating shaping position information based on the programming state of each of the plurality of first memory cells; updating the shaping position information based on data generated by encoding the n-1th logical page data and based on at least one of the first condition and the second condition being satisfied by the encoded n-1th logical page data, where n is a positive integer greater than zero; as well as An encoding operation is performed on the nth logical page data based on the updated shaping position information.

6. The storage device according to claim 5, wherein: The shaping position information includes first position information of the plurality of second storage units that need to satisfy the first condition and second position information of the plurality of second storage units that need to satisfy the second condition.

7. The storage device according to claim 6, wherein: The storage controller is further configured to: updating the shaping position information by excluding position information of a second storage unit satisfying at least one of the first condition and the second condition for the n-1th logical page data; selecting a codeword that maximally satisfies at least one of the first condition and the second condition for data at the position of the second storage unit indicated by the updated shaping position information as the codeword of the nth logical page data; as well as Coded data obtained by applying the selected codeword to the temporarily encoded nth logical page data is output as an encoding result value of the nth logical page data.

8. A method for operating a storage device, the method comprising: checking whether a program state of each of a plurality of first memory cells connected to a first word line is at least one of a first state and a second state; as well as encoding data to be programmed into a plurality of second memory cells connected to a second word line based on the programmed state of each of the plurality of first memory cells, wherein the first word line and the second word line are adjacent to each other, Among them, encoding the data to be programmed into the multiple second storage cells includes: encoding the data to be programmed into the second word line so that the first part of the data to be written into the first part of the multiple second storage cells satisfies a first condition, and so that the second part of the data to be written into the second part of the multiple second storage cells satisfies a second condition.

9. The method according to claim 8, wherein: the first condition being configured to allow the first portion of the data to have a first programming mode other than a first shaping target mode, wherein the first portion of the data is programmed into the first portion of the plurality of second memory cells adjacent to a first portion of the plurality of first memory cells in the first state, and wherein the second condition is configured to allow the second portion of the data to have a second programming mode other than a second shaping target mode, wherein the second portion of the data is programmed into the second portion of the plurality of second storage cells adjacent to a second portion of the plurality of first storage cells in the second state.

10. The method according to claim 9, wherein: Encoding the data to be programmed into the plurality of second memory cells comprises: A codeword is selected from a plurality of codewords, the selected codeword corresponding to data maximally satisfying at least one of the first condition and the second condition among data generated by applying the plurality of codewords to data to be programmed into the plurality of second memory cells.

11. The method according to claim 8, wherein: The data to be programmed into the plurality of second memory cells includes a plurality of logical page data, and Wherein, encoding the data to be programmed into the plurality of second storage cells further comprises: performing temporary encoding on the plurality of pieces of logical page data; selecting a codeword that maximally satisfies at least one of the first condition and the second condition set for each of the plurality of pieces of logical page data that are temporarily encoded; and The selected codeword is applied to each of the corresponding temporarily encoded pieces of the logical page data to generate an encoding result value of each of the plurality of logical page data.

12. The method according to claim 11, wherein: Encoding the data to be programmed into the plurality of second memory cells further comprises: generating shaping position information based on the programming state of each of the plurality of first memory cells; updating the shaping position information based on data generated by encoding the n-1th logical page data and based on at least one of the first condition and the second condition being satisfied by the encoded n-1th logical page data, where n is a positive integer greater than zero; and An encoding operation is performed on the nth logical page data based on the updated shaping position information.

13. The method according to claim 12, wherein: The shaping position information includes first position information of the plurality of second storage units that need to satisfy the first condition and second position information of the plurality of second storage units that need to satisfy the second condition.

14. The method according to claim 13, wherein: Updating the shaping position information includes: The position information of the second storage unit satisfying at least one of the first condition and the second condition for the n-1th logical page data is excluded from the reshaped position information.

15. The method according to claim 14, wherein: Performing an encoding operation on the nth logical page data includes: selecting a codeword that maximally satisfies at least one of the first condition and the second condition for data of the second storage unit indicated by the updated shaping position information as the codeword of the nth logical page data; and Coded data generated by applying the selected codeword to the temporarily encoded nth logical page data is output as an encoding result value of the nth logical page data.

16. A method of operating a storage device, the method comprising: classifying a programming state of each of a plurality of first memory cells connected to a first word line into a plurality of states; encoding data to be programmed into a plurality of second memory cells connected to a second word line based on a programming state of each of the plurality of first memory cells; as well as programming the encoded programming data into the plurality of second memory cells, Among them, encoding the data to be programmed into the multiple second storage cells includes: encoding the data to be programmed into the multiple second storage cells so that a first part of the data to be written into a first part of the multiple second storage cells adjacent to a first storage cell in a first state among the multiple states satisfies a first condition, and so that a second part of the data to be written into a second part of the multiple second storage cells adjacent to a first storage cell in a second state among the multiple states satisfies a second condition.

17. The method according to claim 16, wherein: the first condition being configured to allow the first portion of the data to have a first programming mode other than a first shaping target mode, wherein the first portion of the data is programmed into the first portion of the plurality of second memory cells adjacent to a first portion of the plurality of first memory cells in the first state, and wherein the second condition is configured to allow the second portion of the data to have a second programming mode other than a second shaping target mode, wherein the second portion of the data is programmed into the second portion of the plurality of second storage cells adjacent to a second portion of the plurality of first storage cells in the second state.

18. The method according to claim 16, wherein: Classifying a programming state of each of the plurality of first memory cells comprises: Based on the plurality of first memory cells having b programming states, classifying lower (b-1) / 3 programming states as the first state, wherein b is a positive integer greater than zero; classifying the higher (b-1) / 3 programming states as the second state; and The remaining programmed states are classified as a third state.

19. The method according to claim 18, wherein: The data to be programmed into the plurality of second memory cells includes a plurality of logical page data, and Wherein, encoding the data to be programmed into the plurality of second storage cells further comprises: performing temporary encoding on the plurality of pieces of logical page data; selecting a codeword that maximally satisfies at least one of the first condition and the second condition set for each of the plurality of pieces of logical page data that are temporarily encoded; and The selected codeword is applied to each of the corresponding temporarily encoded pieces of the logical page data to generate an encoding result value of each of the plurality of logical page data.

20. The method according to claim 19, wherein: Encoding the data to be programmed into the plurality of second memory cells further comprises: generating shaping position information based on the programming state of each of the plurality of first memory cells; updating the shaping position information based on data generated by encoding the n-1th logical page data and based on at least one of the first condition and the second condition being satisfied by the encoded n-1th logical page data, where n is a positive integer greater than zero; and An encoding operation is performed on the nth logical page data based on the updated shaping position information.

Images