Method for improving HCI reliability of open-drain output device
By forming multiple gates and isolation structures on the substrate, LDD injection and silicon germanium annealing are implemented, the problem of poor reliability of open-drain output devices in the prior art is solved, and higher device performance and reliability are achieved .
Patent Information
- Application Number
- CN202411368588.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-01-07
AI Technical Summary
The thermal carrier effect (HCI) reliability of open-drain output devices prepared by existing integrated process platforms leads to poor device performance and insufficient reliability.
By forming multiple gate structures and isolation structures on the substrate, light doping drain (LDD) implantation and annealing are performed to form an IONLDD ion implantation region and activate and diffuse doped ions in silicon germanium annealing to improve HCI performance.
It effectively improves the HCI reliability of the open-drain output device, and does not affect the performance of other devices. By extending the annealing time, the ions are fully diffused, forming a more slow-changing junction, and reducing the channel doping concentration gradient.
Smart Images
Figure CN119275086A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving the reliability of an open-drain output device HCI. Background Art
[0002] When the characteristic size of semiconductor devices is very small, a strong electric field can be generated even at a low voltage, which can easily lead to the appearance of hot carriers. Therefore, hot carriers are prone to appear in small-sized devices and large-scale integrated circuits. Some effects caused by hot carriers are called hot carrier effects (HCI).
[0003] When a large voltage is applied to the drain end, a large lateral electric field exists in the channel. Under the action of the lateral electric field, the carriers in the channel are accelerated, and collision ionization produces hole-electron pairs. For NMOS, a positive voltage is applied to the gate end. Under the action of the vertical electric field, the holes flow out of the channel and enter the substrate, and high-speed hot electrons are injected into the oxide layer, causing the transistor threshold voltage to drift, resulting in the NMOS electrical properties changing with the working time, affecting the device reliability and causing the device to fail.
[0004] The existing integrated process platform can prepare different types of devices at the same time. The main direction of improving the HCI of these devices is to use lightly doped drain (LDD) to form a gradual junction, reduce the electric field strength, and reduce the impact of hot carriers to ionize electron-hole pairs. After these devices form LDD, spike annealing is performed to activate ions and promote diffusion. However, due to the short annealing time, the ions cannot be fully diffused, resulting in the HCI reliability of open-drain output devices (such as IO OD devices) in these devices not meeting the requirements. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving the reliability of an open-drain output device HCI, so as to solve the problem in the prior art that the reliability of the open-drain output device HCI prepared by an integrated process platform does not meet the requirements.
[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving the reliability of an open-drain output device HCI, comprising:
[0007] Step 1, providing a substrate, and forming a plurality of gate structures and isolation structures on the substrate;
[0008] Step 2, performing LDD implantation to form a plurality of LDD ion implantation regions in the substrate;
[0009] Step 3, after LDD annealing, an IONLDD ion implantation region is formed in the substrate;
[0010] Step 4: After the germanium silicon is formed, annealing of the germanium silicon is performed to activate and diffuse the doping ions in the IONLDD ion implantation region.
[0011] Preferably, in step 2, the ion implantation angle, ion implantation energy and ion implantation dose of LDD implantation are selected according to the device type.
[0012] Preferably, the LDD annealing is performed using a spike annealing process.
[0013] Preferably, the temperature of the spike annealing is 900° C.-950° C., and the duration is 15 s-20 s.
[0014] Preferably, the conductivity type of the doped ions in the IONLDD ion implantation region is N-type.
[0015] Preferably, in step 4, before forming silicon germanium, sidewall spacers are formed on both sides of the gate structure.
[0016] Preferably, the silicon germanium is formed by a selective silicon germanium epitaxial process.
[0017] Preferably, the SiGe annealing adopts any one of uniform temperature annealing, spike annealing, laser annealing and flash annealing.
[0018] Preferably, the gate structure includes a gate insulating layer and a gate layer stacked from bottom to top.
[0019] Preferably, the isolation structure is formed by a shallow trench isolation process.
[0020] As described above, the method for improving the HCI reliability of an open-drain output device provided in the present application has the following beneficial effects: after LDD annealing, LDD injection is performed on the NMOS serving as an IO device, and subsequent silicon-germanium annealing is used to activate the doped ions in the IONLDD ion injection region, thereby effectively improving the HCI reliability of the open-drain output device without affecting the performance of other devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0022] Figure 1 A flow chart showing a method for improving HCI reliability of an open-drain output device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0023] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0027] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0028] When different types of devices are prepared simultaneously using the existing integrated process platform, the LDD annealing performed after LDD implantation of different devices (such as ULVT, LVT, SVT, CVT, open-drain output devices) cannot fully diffuse the ions due to the short annealing time, resulting in the HCI reliability of the open-drain output devices in these devices failing to meet the requirements. If the LDD annealing is omitted and the subsequent silicon-germanium annealing is used to activate and diffuse the LDD implanted ions, the LDD can be fully diffused due to the sufficient annealing time, so that the channel doping concentration gradient is reduced to form a more gradual junction, effectively improving the HCI performance of the open-drain output device. However, omitting the LDD annealing will affect the performance of other devices.
[0029] In order to solve this problem, the present application provides a method for improving the reliability of an open-drain output device HCI.
[0030] See also Figure 1 , which shows a flow chart of a method for improving HCI reliability of an open-drain output device provided in an embodiment of the present application.
[0031] like Figure 1 As shown, the method for improving the HCI reliability of an open-drain output device comprises the following steps:
[0032] Step 1, providing a substrate, and forming a plurality of gate structures and isolation structures on the substrate;
[0033] Step 2, performing LDD implantation to form a plurality of LDD ion implantation regions in the substrate;
[0034] Step 3, after LDD annealing, an IONLDD ion implantation region is formed in the substrate;
[0035] Step 4: After the germanium silicon is formed, annealing of the germanium silicon is performed to activate and diffuse the doping ions in the IONLDD ion implantation region.
[0036] In step 1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.
[0037] As an example, the isolation structure divides the substrate into multiple regions. For example, the threshold voltages of devices formed in different regions are different, and open-drain output devices (such as IO OD devices) are formed in certain regions.
[0038] The isolation structure may be composed of any insulating material such as silicon dioxide (SiO2), or a "high-k" dielectric having a high dielectric constant, which may be greater than 3.9, for example. In some cases, the isolation structure may be composed of an oxide material. Examples of materials suitable for forming the isolation structure may include silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials now known or later developed with similar properties.
[0039] Exemplarily, the isolation structure is formed by a shallow trench isolation (STI) process, where the shallow trench isolation process includes but is not limited to shallow trench etching, oxide filling, and oxide planarization.
[0040] Shallow trench etching includes but is not limited to isolation oxide layer, nitride precipitation, shallow trench isolation using mask, and STI shallow trench etching. STI oxide filling includes but is not limited to trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling or PVD (physical vapor deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by a variety of methods. The planarization of the silicon wafer can be achieved by filling the gap with SOG (spin-on-glass). SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, SOG is baked to evaporate the solvent and leave silicon dioxide in the gap. The entire surface can also be reversed to reduce the thickness of the entire silicon wafer. The planarization process can also be effectively performed by CMP process (also known as chemical mechanical polishing process), including but not limited to polishing the trench oxide (chemical mechanical polishing can be used) and nitride removal.
[0041] As an example, the gate structure includes a gate insulating layer and a gate layer stacked from bottom to top.
[0042] In a specific embodiment, the steps of forming a gate structure may include: first forming a gate insulating layer on a substrate using a suitable deposition process; then depositing a gate layer on the gate insulating layer, the material of the gate insulating layer may include silicon oxide, and the material of the gate layer may include polysilicon; spin coating photoresist on the gate layer, and then patterning the photoresist using a mask to form a patterned photoresist layer; then etching the gate layer using the patterned photoresist layer, and removing the patterned photoresist layer after etching is completed.
[0043] In step 2, different devices have different LDD implantation conditions, and the ion implantation angle, ion implantation energy and ion implantation dose of the LDD implantation are selected according to the device type. After the LDD implantation is performed, the substrate regions where the devices other than the IONMOS are located form LDD ion implantation regions.
[0044] In step three, illustratively, LDD annealing is performed using a spike annealing process to activate and diffuse the ions in the formed LDD ion implantation region. illustratively, the temperature of the spike annealing is 900° C.-950° C., and the duration is 15s-20s.
[0045] As an example, the conductivity type of the doped ions in the IONLDD ion implantation region formed in the substrate region where the IONMOS is located is N-type.
[0046] In step 4, before forming the silicon germanium, sidewall spacers are formed on both sides of the gate structure. Exemplarily, the silicon germanium is formed by a selective silicon germanium epitaxial process.
[0047] Exemplarily, the SiGe annealing adopts any one of uniform temperature annealing, spike annealing, laser annealing and flash annealing.
[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0049] In summary, the method for improving the HCI reliability of the open-drain output device provided by the present application implements LDD implantation on the NMOS as the IO device after LDD annealing, and uses the subsequent silicon germanium annealing to activate the doped ions in the IONLDD ion implantation region, effectively improving the HCI reliability of the open-drain output device without affecting the performance of other devices. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0050] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. A method for improving the reliability of an open-drain output device HCI, characterized in that: The method comprises: Step 1, providing a substrate, and forming a plurality of gate structures and isolation structures on the substrate; Step 2, performing LDD implantation to form a plurality of LDD ion implantation regions in the substrate; Step 3, after performing LDD annealing, forming an IONLDD ion implantation region in the substrate; Step 4: After forming the silicon germanium, annealing of the silicon germanium is performed to activate and diffuse the doping ions in the IONLDD ion implantation region.
2. The method according to claim 1, characterized in that In the step 2, the ion implantation angle, ion implantation energy and ion implantation dose of the LDD implantation are selected according to the device type.
3. The method according to claim 1, characterized in that The LDD annealing is performed using a spike annealing process.
4. The method according to claim 3, characterized in that: The temperature of the spike annealing is 900° C.-950° C., and the duration is 15s-20s.
5. The method according to claim 1, characterized in that The conductivity type of the doped ions in the IONLDD ion implantation region is N-type.
6. The method according to claim 1, characterized in that In the step 4, before forming the silicon germanium, sidewalls are formed on both sides of the gate structure.
7. The method according to claim 1, characterized in that The silicon germanium is formed by a selective silicon germanium epitaxial process.
8. The method according to claim 1, characterized in that: The germanium silicon annealing adopts any one of uniform temperature annealing, spike annealing, laser annealing and flash annealing.
9. The method according to claim 1, characterized in that: The gate structure includes a gate insulating layer and a gate layer stacked from bottom to top.
10. The method according to claim 1, characterized in that The isolation structure is formed by a shallow trench isolation process.